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| m pd784938 subseries 16-bit single-chip microcontrollers hardware m pd784935 m pd784936 m pd784937 m pd784938 m pd78f4938 document no. u13987ej1v0um00 (1st edition) date published september 1999 n cp(k) preliminary user? manual printed in japan 1999
2 preliminary users manual u13987ej1v0um00 [memo] 3 preliminary users manual u13987ej1v0um00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 preliminary users manual u13987ej1v0um00 fip, iebus, inter equipment bus, and eeprom are trademarks of nec corporation. ms-dos, windows, and windows nt are either trademarks or registered trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. news and news-os are trademarks of sony corporation. ethernet is a trademark of xerox corporation. osf/motif is a trademark of open software foundation, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. 5 preliminary users manual u13987ej1v0um00 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12 license not needed: m pd78f4938 the customer must judge the need for license: m pd784935, 784936, 784937, 784938 the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. 6 preliminary users manual u13987ej1v0um00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1 7 preliminary users manual u13987ej1v0um00 introduction target readers this manual is intended for users who understand the functions of the m pd784938 subseries to design application systems. purpose the purpose of this manual is to give users an understanding of the various hardware functions of the m pd784938 subseries. organization the m pd784938 subseries users manual is divided into two volumes C hardware (this manual) and instruction. hardware instruction pin functions cpu functions internal block functions addressing interrupts instruction set other internal peripheral functions certain operating precautions apply to these products. these precautions are stated at the relevant points in the text of each chapter, and are also summarized at the end of each chapter. be sure to read them. 8 preliminary users manual u13987ej1v0um00 how to read this manual readers are required to have a general knowledge of electric engineering, logic circuits and microcomputers. ? unless otherwise specified the m pd784938 is treated as the representative model. if using the m pd784935, 784936, 784937, and 78f4938, take the m pd784938 for the m pd784935, 784936, 784937, and 78f4938. to understand overall functions of the m pd784938 subseries: ? read this manual in the order of the contents . to learn about differences from the m pd784908 subseries: ? see 1.8 main differences with m pd784908 subseries . if the device operates strangely after debugging: ? cautions are summarized at the end of each chapter, so refer to the cautions for the relevant function. to learn the detailed functions of a register whose register name is known: ? use appendix c register index . to learn the details of the instruction functions: ? refer to 78k/iv series users manual-instruction (u10905e) separately available. to learn about the electrical characteristics: ? refer to data sheets. to learn about application examples of each function: ? refer to application note separately available. conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ......................... b or decimal ...................... hexadecimal ............... h 9 preliminary users manual u13987ej1v0um00 register notation 7 b edc 6 1 5 0 4 3 a 2 1 1 0 0 write operation read operation 0 or 1 is written. the operation is not affected by either value. 0 must be written 1 must be written a value is written according to the function to be used. a value is read according to the operating status. 0 or 1 is read. where the bit number is marked with a circle, the bit name is reserved for nec?s assembler and is defined as an sfr variable by the #pragma sfr directive for c compiler. code combinations marked setting prohibited in the register notations in the text must not be written. easily confused characters : 0 (zero), o (letter o) : 1 (one), l (lowercase letter l), i (uppercase letter i) related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. device related documents document name document no. japanese english m pd784935, 784936, 784937, 784938 data sheet u13572j u13572e m pd78f4938 preliminary product information u13573j u13573e m pd784938 subseries special function register table to be prepared m pd784938 subseries users manual - hardware u13987j this manual 78k/iv series application note - software basics u10095j u10095e 78k/iv series user's manual - instruction u10905j u10905e 78k/iv series instruction table u10594j 78k/iv series instruction set u10595j 10 preliminary users manual u13987ej1v0um00 documents for development tools (users manuals) document name document no. japanese english ra78k4 assembler package operation u11334j u11334e language u11162j u11162e ra78k4 structured assembler preprocessor u11743j u11743e cc78k4 c compiler operation u11517j u11517e language u11518j u11518e ie-78k4-ns u13356j u13356e ie-784000-r u12903j eeu-1534 ie-784937-ns-em1 to be prepared to be prepared ie-784937-r-em1 to be prepared ep-78064 eeu-934 eeu-1469 sm78k4 system simulator windows tm based reference u10093j u10093e sm78k series system simulator external component user u10092j u10092e open interface specification id-78k4-ns integrated debugger reference u12796j u12796e id78k4 integrated debugger windows based reference u10440j u10440e id78k4 integrated debugger hp-ux tm , sunos tm , reference u11960j u11960e news-os tm based documents for embedded software (users manuals) document name document no. japanese english 78k/iv series real-time os fundamental u10603j u10603e installation u10604j u10604e debugger u10364j 78k/iv series os mx78k4 basics u11779j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 11 preliminary users manual u13987ej1v0um00 other documents document name document no. japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcomputer-related products by third party u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. 12 preliminary users manual u13987ej1v0um00 [memo] 13 preliminary users manual u13987ej1v0um00 contents chapter 1 general ........................................................................................................................... 39 1.1 features ............................................................................................................................... ..... 41 1.2 ordering information ............................................................................................................... 42 1.3 pin configuration (top view) ................................................................................................. 43 1.3.1 normal operation mode ............................................................................................................... 43 1.4 application system configuration example (car audio (tuner, deck)) .......................... 45 1.5 block diagram .......................................................................................................................... 46 1.6 list of functions ...................................................................................................................... 47 1.7 differences among products in m pd784938 subseries ..................................................... 50 1.8 main differences with m pd784908 subseries ...................................................................... 50 chapter 2 pin functions ............................................................................................................... 51 2.1 pin function lists .................................................................................................................... 51 2.1.1 normal operation mode ............................................................................................................... 51 2.2 pin functions ........................................................................................................................... 55 2.2.1 normal operation mode ............................................................................................................... 55 2.3 input/output circuits and connection of unused pins ..................................................... 62 2.4 cautions .................................................................................................................... ................ 65 chapter 3 cpu architecture ...................................................................................................... 67 3.1 memory space .......................................................................................................................... 67 3.2 internal rom area .................................................................................................................... 73 3.3 base area ............................................................................................................................... ... 74 3.3.1 vector table area .......................................................................................................................... 75 3.3.2 callt instruction table area ....................................................................................................... 76 3.3.3 callf instruction entry area ...................................................................................................... 76 3.4 internal data area .................................................................................................................... 77 3.4.1 internal ram area ........................................................................................................................ 78 3.4.2 special function register (sfr) area ........................................................................................... 81 3.4.3 external sfr area ....................................................................................................................... 81 3.5 external memory space .......................................................................................................... 81 3.6 m pd78f4938 memory mapping ............................................................................................... 82 3.7 control registers ..................................................................................................................... 83 3.7.1 program counter (pc) .................................................................................................................. 83 3.7.2 program status word (psw) ........................................................................................................ 83 3.7.3 use of rss bit ............................................................................................................................. 86 3.7.4 stack pointer (sp) ........................................................................................................................ 88 3.8 general-purpose registers .................................................................................................... 92 3.8.1 configuration ............................................................................................................................... .92 3.8.2 functions ............................................................................................................................... ....... 94 3.9 special function registers (sfr) ......................................................................................... 97 3.10 cautions ................................................................................................................... ................. 103 chapter 4 clock generator ...................................................................................................... 105 4.1 configuration and function ................................................................................................... 105 14 preliminary users manual u13987ej1v0um00 4.2 control registers ..................................................................................................................... 107 4.2.1 standby control register (stbc) ................................................................................................. 107 4.2.2 oscillation stabilization time specification register (osts) ....................................................... 109 4.3 clock generator operation .................................................................................................... 110 4.3.1 clock oscillator ............................................................................................................................. 11 0 4.3.2 divider ............................................................................................................................... ........... 110 4.4 cautions .................................................................................................................... ................ 111 4.4.1 when an external clock is input .................................................................................................. 111 4.4.2 when crystal/ceramic oscillation is used .................................................................................... 112 chapter 5 regulator ...................................................................................................................... 115 5.1 outline of regulator ................................................................................................................ 115 chapter 6 port functions ........................................................................................................... 117 6.1 digital input/output ports ....................................................................................................... 117 6.2 port 0 ............................................................................................................................... .......... 119 6.2.1 hardware configuration ................................................................................................................ 119 6.2.2 i/o mode/control mode setting .................................................................................................... 120 6.2.3 operating status ........................................................................................................................... 121 6.2.4 on-chip pull-up resistors .............................................................................................................. 123 6.2.5 transistor drive ............................................................................................................................ 125 6.3 port 1 ............................................................................................................................... .......... 126 6.3.1 hardware configuration ................................................................................................................ 127 6.3.2 i/o mode/control mode setting .................................................................................................... 131 6.3.3 operating status ........................................................................................................................... 132 6.3.4 on-chip pull-up resistors .............................................................................................................. 135 6.3.5 direct led drive ........................................................................................................................... 136 6.4 port 2 ............................................................................................................................... .......... 137 6.4.1 hardware configuration ................................................................................................................ 139 6.4.2 input mode/control mode setting ................................................................................................. 141 6.4.3 operating status ........................................................................................................................... 141 6.4.4 on-chip pull-up resistors .............................................................................................................. 141 6.5 port 3 ............................................................................................................................... .......... 143 6.5.1 hardware configuration ................................................................................................................ 144 6.5.2 i/o mode/control mode setting .................................................................................................... 148 6.5.3 operating status ........................................................................................................................... 150 6.5.4 on-chip pull-up resistors .............................................................................................................. 153 6.6 port 4 ............................................................................................................................... .......... 155 6.6.1 hardware configuration ................................................................................................................ 155 6.6.2 i/o mode/control mode setting .................................................................................................... 156 6.6.3 operating status ........................................................................................................................... 157 6.6.4 on-chip pull-up resistors .............................................................................................................. 159 6.6.5 direct led drive ........................................................................................................................... 161 6.7 port 5 ............................................................................................................................... .......... 162 6.7.1 hardware configuration ................................................................................................................ 162 6.7.2 i/o mode/control mode setting .................................................................................................... 163 6.7.3 operating status ........................................................................................................................... 164 6.7.4 on-chip pull-up resistors .............................................................................................................. 166 15 preliminary users manual u13987ej1v0um00 6.7.5 direct led drive ........................................................................................................................... 168 6.8 port 6 ............................................................................................................................... .......... 169 6.8.1 hardware configuration ................................................................................................................ 170 6.8.2 i/o mode/control mode setting .................................................................................................... 174 6.8.3 operating status ........................................................................................................................... 176 6.8.4 on-chip pull-up resistors .............................................................................................................. 178 6.9 port 7 ............................................................................................................................... .......... 179 6.9.1 hardware configuration ................................................................................................................ 179 6.9.2 i/o mode/control mode setting .................................................................................................... 180 6.9.3 operating status ........................................................................................................................... 181 6.9.4 on-chip pull-up resistors .............................................................................................................. 182 6.9.5 caution ............................................................................................................................... .......... 182 6.10 port 9 ............................................................................................................................... .......... 183 6.10.1 hardware configuration ................................................................................................................ 183 6.10.2 i/o mode/control mode setting .................................................................................................... 184 6.10.3 operating status ........................................................................................................................... 185 6.10.4 on-chip pull-up resistors .............................................................................................................. 187 6.11 port 10 ............................................................................................................................... ........ 188 6.11.1 hardware configuration ................................................................................................................ 189 6.11.2 i/o mode/control mode setting .................................................................................................... 193 6.11.3 operating status ........................................................................................................................... 194 6.11.4 on-chip pull-up resistors .............................................................................................................. 197 6.12 port output check function .................................................................................................. 198 6.13 cautions ................................................................................................................... ................. 199 chapter 7 real-time output function .................................................................................. 201 7.1 configuration and function ................................................................................................... 201 7.2 real-time output port control register (rtpc) .................................................................. 203 7.3 real-time output port accesses ........................................................................................... 204 7.4 operation ............................................................................................................................... ... 206 7.5 example of use ........................................................................................................................ 209 7.6 cautions .................................................................................................................... ................ 211 chapter 8 outline of timer ....................................................................................................... 213 chapter 9 timer/event counter 0 ........................................................................................... 215 9.1 functions ............................................................................................................................... ... 215 9.2 configuration ............................................................................................................................ 218 9.3 timer/event counter 0 control registers ......................................................................... 221 9.4 timer counter 0 (tm0) operation .......................................................................................... 226 9.4.1 basic operation ............................................................................................................................ 226 9.4.2 clear operation ............................................................................................................................. 22 8 9.5 external event counter function .......................................................................................... 230 9.6 compare register and capture register operation ........................................................... 233 9.6.1 compare operations .................................................................................................................... 233 9.6.2 capture operations ...................................................................................................................... 235 9.7 basic operation of output control circuit .......................................................................... 236 9.7.1 basic operation ............................................................................................................................ 238 16 preliminary users manual u13987ej1v0um00 9.7.2 toggle output ............................................................................................................................... . 238 9.7.3 pwm output ............................................................................................................................... ... 240 9.7.4 ppg output ............................................................................................................................... .... 245 9.7.5 software triggered one-shot pulse output ................................................................................... 251 9.8 examples of use ...................................................................................................................... 252 9.8.1 operation as interval timer (1) .................................................................................................... 252 9.8.2 operation as interval timer (2) .................................................................................................... 254 9.8.3 pulse width measurement operation ........................................................................................... 256 9.8.4 operation as pwm output ........................................................................................................... 259 9.8.5 operation as ppg output ............................................................................................................ 262 9.8.6 example of software triggered one-shot pulse output ............................................................... 265 9.9 cautions .................................................................................................................... ................ 268 chapter 10 timer/event counter 1 ......................................................................................... 271 10.1 functions ............................................................................................................................... ... 271 10.2 configuration ............................................................................................................................ 273 10.3 timer/event counter 1 control registers ............................................................................ 277 10.4 timer counter 1 (tm1) operation .......................................................................................... 280 10.4.1 basic operation ............................................................................................................................ 280 10.4.2 clear operation ............................................................................................................................. 28 3 10.5 external event counter function .......................................................................................... 285 10.6 compare register and capture/compare register operation .......................................... 288 10.6.1 compare operations .................................................................................................................... 288 10.6.2 capture operations ...................................................................................................................... 290 10.7 examples of use ...................................................................................................................... 293 10.7.1 operation as interval timer (1) .................................................................................................... 293 10.7.2 operation as interval timer (2) .................................................................................................... 296 10.7.3 pulse width measurement operation ........................................................................................... 298 10.8 cautions ................................................................................................................... ................. 301 chapter 11 timer/event counter 2 ......................................................................................... 305 11.1 functions ............................................................................................................................... ... 305 11.2 configuration ............................................................................................................................ 308 11.3 timer/event counter 2 control registers ............................................................................ 312 11.4 timer counter 2 (tm2) operation .......................................................................................... 316 11.4.1 basic operation ............................................................................................................................ 316 11.4.2 clear operation ............................................................................................................................. 31 9 11.5 external event counter function .......................................................................................... 321 11.6 one-shot timer function ....................................................................................................... 324 11.7 compare register, capture/compare register, and capture register operation ......... 325 11.7.1 compare operations .................................................................................................................... 325 11.7.2 capture operations ...................................................................................................................... 327 11.8 basic operation of output control circuit .......................................................................... 330 11.8.1 basic operation ............................................................................................................................ 332 11.8.2 toggle output ............................................................................................................................... . 332 11.8.3 pwm output ............................................................................................................................... ... 334 11.8.4 ppg output ............................................................................................................................... .... 340 11.9 examples of use ...................................................................................................................... 347 17 preliminary users manual u13987ej1v0um00 11.9.1 operation as interval timer (1) .................................................................................................... 347 11.9.2 operation as interval timer (2) .................................................................................................... 350 11.9.3 pulse width measurement operation ........................................................................................... 353 11.9.4 operation as pwm output ........................................................................................................... 356 11.9.5 operation as ppg output ............................................................................................................ 360 11.9.6 operation as external event counter ........................................................................................... 364 11.9.7 operation as one-shot timer ........................................................................................................ 366 11.10 cautions .................................................................................................................. .................. 369 chapter 12 timer 3 ........................................................................................................................... 373 12.1 function ............................................................................................................................... ..... 373 12.2 configuration ............................................................................................................................ 374 12.3 timer 3 control registers ...................................................................................................... 376 12.4 timer counter 3 (tm3) operation .......................................................................................... 378 12.4.1 basic operation ............................................................................................................................ 378 12.4.2 clear operation ............................................................................................................................. 38 0 12.5 compare register operation ................................................................................................. 382 12.6 example of use ........................................................................................................................ 383 12.7 cautions ................................................................................................................... ................. 385 chapter 13 watchdog timer ....................................................................................................... 387 13.1 configuration ............................................................................................................................ 387 13.2 watchdog timer mode register (wdm) ................................................................................ 388 13.3 operation ............................................................................................................................... ... 390 13.3.1 count operation ............................................................................................................................ 390 13.3.2 interrupt priorities ......................................................................................................................... 390 13.4 cautions ................................................................................................................... ................. 391 13.4.1 general cautions on use of watchdog timer ............................................................................... 391 13.4.2 cautions on m pd784938 subseries watchdog timer .................................................................. 392 chapter 14 watch timer ................................................................................................................ 393 chapter 15 pwm output unit ..................................................................................................... 395 15.1 pwm output unit configuration ............................................................................................ 395 15.2 pwm output unit control registers ..................................................................................... 397 15.2.1 pwm control register (pwmc) .................................................................................................... 397 15.2.2 pwm prescaler register (pwpr) ................................................................................................ 398 15.2.3 pwm modulo registers (pwm0, pwm1) ..................................................................................... 398 15.3 pwm output unit operation ................................................................................................... 399 15.3.1 basic pwm output operation ....................................................................................................... 399 15.3.2 pwm pulse output enabling/disabling ......................................................................................... 400 15.3.3 pwm pulse active level specification .......................................................................................... 400 15.3.4 pwm pulse width rewrite cycle specification .............................................................................. 401 15.4 caution .................................................................................................................... .................. 402 chapter 16 a/d converter ........................................................................................................... 403 16.1 configuration ............................................................................................................................ 403 16.2 a/d converter mode register (adm) .................................................................................... 407 18 preliminary users manual u13987ej1v0um00 16.3 a/d current cut select register (iead) ............................................................................... 410 16.4 operation ............................................................................................................................... ... 411 16.4.1 basic a/d converter operation ..................................................................................................... 411 16.4.2 select mode ............................................................................................................................... .. 415 16.4.3 scan mode ............................................................................................................................... .... 416 16.4.4 a/d conversion operation start by software ................................................................................ 418 16.4.5 a/d conversion operation start by hardware .............................................................................. 420 16.5 external circuit of a/d converter .......................................................................................... 423 16.6 cautions ................................................................................................................... ................. 423 chapter 17 outline of serial interface ............................................................................ 425 chapter 18 asynchronous serial interface/3-wire serial i/o ............................... 427 18.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode . 428 18.2 asynchronous serial interface mode ................................................................................... 429 18.2.1 configuration in asynchronous serial interface mode ................................................................ 429 18.2.2 asynchronous serial interface control registers ......................................................................... 432 18.2.3 data format ............................................................................................................................... .... 435 18.2.4 parity types and operations ......................................................................................................... 436 18.2.5 transmission ............................................................................................................................... . 437 18.2.6 reception ............................................................................................................................... ...... 438 18.2.7 receive errors .............................................................................................................................. 4 39 18.3 3-wire serial i/o mode ............................................................................................................ 440 18.3.1 configuration in 3-wire serial i/o mode ...................................................................................... 440 18.3.2 clocked serial interface mode registers (csim1, csim2) ......................................................... 443 18.3.3 basic operation timing ................................................................................................................. 444 18.3.4 operation when transmission only is enabled ............................................................................ 446 18.3.5 operation when reception only is enabled ................................................................................. 446 18.3.6 operation when transmission/reception is enabled ................................................................... 447 18.3.7 corrective action in case of slippage of serial clock and shift operations ................................ 447 18.4 baud rate generator ............................................................................................................... 448 18.4.1 baud rate generator configuration .............................................................................................. 448 18.4.2 baud rate generator control register (brgc, brgc2) .............................................................. 450 18.4.3 baud rate generator operation .................................................................................................... 452 18.4.4 baud rate setting in asynchronous serial interface mode .......................................................... 454 18.5 cautions ................................................................................................................... ................. 456 chapter 19 3-wire serial i/o mode ......................................................................................... 457 19.1 function ............................................................................................................................... ..... 457 19.2 configuration ............................................................................................................................ 458 19.3 control registers ..................................................................................................................... 459 19.3.1 clocked serial interface mode register (csim, csim3) ............................................................. 459 19.4 3-wire serial i/o mode ............................................................................................................ 461 19.4.1 basic operation timing ................................................................................................................. 462 19.4.2 operation when transmission only is enabled ............................................................................ 464 19.4.3 operation when reception only is enabled ................................................................................. 465 19.4.4 operation when transmission/reception is enabled ................................................................... 465 19.4.5 corrective action in case of slippage of serial clock and shift operations ................................ 465 19 preliminary users manual u13987ej1v0um00 chapter 20 iebus controller ..................................................................................................... 467 20.1 iebus controller function ...................................................................................................... 467 20.1.1 communication protocol of iebus ............................................................................................... 467 20.1.2 determination of bus mastership (arbitration) ............................................................................ 468 20.1.3 communication mode .................................................................................................................. 468 20.1.4 communication address .............................................................................................................. 468 20.1.5 broadcasting communication ...................................................................................................... 469 20.1.6 transmission format of iebus ..................................................................................................... 469 20.1.7 transmit data ............................................................................................................................... 477 20.1.8 bit format ............................................................................................................................... ....... 479 20.2 simple iebus controller ......................................................................................................... 480 20.3 iebus controller configuration ............................................................................................. 481 20.4 internal registers of iebus controller ................................................................................. 483 20.4.1 internal register list ...................................................................................................................... 483 20.4.2 description of internal registers .................................................................................................. 484 20.5 interrupt operations of iebus controller ............................................................................. 500 20.5.1 interrupt control block .................................................................................................................. 500 20.5.2 interrupt source list ...................................................................................................................... 501 20.6 interrupt generation timing and main cpu processing .................................................... 502 20.6.1 master transmission ..................................................................................................................... 502 20.6.2 master reception .......................................................................................................................... 504 20.6.3 slave transmission ....................................................................................................................... 505 20.6.4 slave reception ............................................................................................................................ 506 20.6.5 interval of occurrence of interrupt for iebus control .................................................................. 507 20.7 cautions when using iebus controller ................................................................................ 510 chapter 21 clock output function ....................................................................................... 511 21.1 configuration ............................................................................................................................ 511 21.2 clock output mode register (clom) ................................................................................... 513 21.3 operation ............................................................................................................................... ... 514 21.3.1 clock output ............................................................................................................................... .. 514 21.3.2 1-bit output port ............................................................................................................................ 515 21.3.3 operation in standby mode ......................................................................................................... 515 21.4 cautions ................................................................................................................... ................. 515 chapter 22 edge detection function ................................................................................... 517 22.1 edge detection function control registers ........................................................................ 517 22.1.1 external interrupt mode registers (intm0, intm1) .................................................................... 517 22.1.2 sampling clock selection register (scs0) .................................................................................. 520 22.2 edge detection for pins p20, p25, and p26 ......................................................................... 521 22.3 p21 pin edge detection .......................................................................................................... 522 22.4 pin edge detection for pins p22 to p24 ............................................................................... 523 22.5 cautions ................................................................................................................... ................. 524 chapter 23 interrupt functions .............................................................................................. 525 23.1 interrupt request sources ..................................................................................................... 526 23.1.1 software interrupts ....................................................................................................................... 528 23.1.2 operand error interrupts .............................................................................................................. 528 20 preliminary users manual u13987ej1v0um00 23.1.3 non-maskable interrupts .............................................................................................................. 528 23.1.4 maskable interrupts ...................................................................................................................... 528 23.2 interrupt service modes ......................................................................................................... 529 23.2.1 vectored interrupt service ............................................................................................................ 529 23.2.2 macro service ............................................................................................................................... 529 23.2.3 context switching ......................................................................................................................... 529 23.3 interrupt service control registers ...................................................................................... 530 23.3.1 interrupt control registers ............................................................................................................ 533 23.3.2 interrupt mask registers (mk0/mk1) ........................................................................................... 538 23.3.3 in-service priority register (ispr) ................................................................................................ 540 23.3.4 interrupt mode control register (imc) .......................................................................................... 541 23.3.5 watchdog timer mode register (wdm) ....................................................................................... 542 23.3.6 program status word (psw) ........................................................................................................ 543 23.4 software interrupt acknowledgment operations ................................................................ 544 23.4.1 brk instruction software interrupt acknowledgment operation ................................................. 544 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation .......................................................................................................... 544 23.5 operand error interrupt acknowledgment operation ........................................................ 546 23.6 non-maskable interrupt acknowledgment operation ........................................................ 546 23.7 maskable interrupt acknowledgment operation ................................................................. 550 23.7.1 vectored interrupt ......................................................................................................................... 552 23.7.2 context switching ......................................................................................................................... 552 23.7.3 maskable interrupt priority levels ................................................................................................ 554 23.8 macro service function .......................................................................................................... 560 23.8.1 outline of macro service function ................................................................................................ 560 23.8.2 types of macro service ................................................................................................................ 560 23.8.3 basic macro service operation .................................................................................................... 563 23.8.4 operation at end of macro service .............................................................................................. 564 23.8.5 macro service control registers ................................................................................................... 566 23.8.6 macro service type a ................................................................................................................... 569 23.8.7 macro service type b ................................................................................................................... 574 23.8.8 macro service type c ................................................................................................................... 579 23.8.9 counter mode ............................................................................................................................... 592 23.9 when interrupt requests and macro service are temporarily held pending ................ 594 23.10 instructions whose execution is temporarily suspended by an interrupt or macro service ........................................................................................................................... 596 23.11 interrupt and macro service operation timing ................................................................... 596 23.11.1 interrupt acknowledge processing time ...................................................................................... 597 23.11.2 processing time of macro service ............................................................................................... 598 23.12 restoring interrupt function to initial state ........................................................................ 599 23.13 cautions ............................................................................................................................... ..... 600 chapter 24 local bus interface function ........................................................................ 603 24.1 memory expansion function ................................................................................................. 603 24.1.1 memory expansion mode register (mm) ..................................................................................... 603 24.1.2 memory map with external memory expansion .......................................................................... 605 24.1.3 basic operation of local bus interface ......................................................................................... 614 24.2 wait function ........................................................................................................................... 615 21 preliminary users manual u13987ej1v0um00 24.2.1 wait function control registers ..................................................................................................... 615 24.2.2 address waits ............................................................................................................................... 618 24.2.3 access waits ............................................................................................................................... .. 621 24.3 pseudo-static ram refresh function .................................................................................. 628 24.3.1 control registers ........................................................................................................................... 629 24.3.2 operations ............................................................................................................................... ..... 630 24.4 bus hold function ................................................................................................................... 634 24.4.1 hold mode register (hldm) ........................................................................................................ 634 24.4.2 operation ............................................................................................................................... ....... 635 24.5 cautions ................................................................................................................... ................. 636 chapter 25 standby function .................................................................................................... 637 25.1 configuration and function ................................................................................................... 637 25.2 control registers ..................................................................................................................... 639 25.2.1 standby control register (stbc) ................................................................................................. 639 25.2.2 oscillation stabilization time specification register (osts) ....................................................... 641 25.3 halt mode .................................................................................................................. .............. 642 25.3.1 halt mode setting and operating status .................................................................................... 642 25.3.2 halt mode release ..................................................................................................................... 642 25.4 stop mode .................................................................................................................. ............. 646 25.4.1 stop mode setting and operating status ................................................................................... 646 25.4.2 stop mode release .................................................................................................................... 647 25.5 idle mode .................................................................................................................. ............... 650 25.5.1 idle mode setting and operating status .................................................................................... 650 25.5.2 idle mode release ...................................................................................................................... 651 25.6 check items when stop mode/idle mode is used ........................................................... 653 25.7 cautions ................................................................................................................... ................. 655 chapter 26 reset function ......................................................................................................... 657 26.1 reset function ......................................................................................................................... 657 26.2 caution .................................................................................................................... .................. 662 chapter 27 rom correction ....................................................................................................... 663 27.1 rom correction functions ..................................................................................................... 663 27.2 rom correction configuration .............................................................................................. 665 27.3 control register for rom correction ................................................................................... 667 27.4 use of rom correction ........................................................................................................... 669 27.5 conditions for executing rom correction .......................................................................... 670 chapter 28 m pd78f4938 programming ...................................................................................... 671 28.1 internal memory size switching register (ims) .................................................................. 672 28.2 flash memory programming using flashpro ii and flashpro iii ...................................... 673 28.2.1 selecting communication mode .................................................................................................. 673 28.2.2 flash memory programming functions ........................................................................................ 674 28.2.3 connecting flashpro ii or flashpro iii ........................................................................................ 675 chapter 29 instruction operations ....................................................................................... 677 29.1 conventions ............................................................................................................................. 67 7 22 preliminary users manual u13987ej1v0um00 29.2 list of operations .................................................................................................................... 681 29.3 instructions listed by type of addressing .......................................................................... 705 appendix a development tools ................................................................................................ 709 a.1 language processing software ............................................................................................. 712 a.2 flash memory programming tools ....................................................................................... 713 a.3 debugging tools ...................................................................................................................... 714 a.3.1 hardware ............................................................................................................................... ....... 714 a.3.2 software ............................................................................................................................... ........ 716 a.4 drawings of conversion socket (ev-9200gf-100) and recommended board mounting pattern .............................................................................. 718 a.5 check sheet for m pd784938 subseries development tools ............................................. 720 appendix b embedded software ................................................................................................ 723 appendix c register index ........................................................................................................... 725 c.1 register name index ............................................................................................................... 725 c.2 register symbol index ............................................................................................................ 728 23 preliminary users manual u13987ej1v0um00 2-1 pin input/output circuits ............................................................................................................................. 64 3-1 m pd784935 memory map ............................................................................................................................ 69 3-2 m pd784936 memory map ............................................................................................................................ 70 3-3 m pd784937 memory map ............................................................................................................................ 71 3-4 m pd784938, 78f4938 memory map ........................................................................................................... 72 3-5 internal ram memory map ......................................................................................................................... 79 3-6 internal memory size switching register (ims) ......................................................................................... 82 3-7 program counter (pc) format .................................................................................................................... 83 3-8 program status word (psw) format ......................................................................................................... 83 3-9 stack pointer (sp) format .......................................................................................................................... 88 3-10 data saved to stack area ........................................................................................................................... 89 3-11 data restored from stack area .................................................................................................................. 90 3-12 general-purpose register format .............................................................................................................. 92 3-13 general-purpose register addresses ........................................................................................................ 93 4-1 clock generator block diagram .................................................................................................................. 105 4-2 clock oscillator external circuitry .............................................................................................................. 106 4-3 standby control register (stbc) format .................................................................................................. 108 4-4 oscillation stabilization time specification register (osts) format ....................................................... 109 4-5 signal extraction with external clock input ................................................................................................ 111 4-6 cautions on resonator connection ............................................................................................................ 112 4-7 incorrect example of resonator connection .............................................................................................. 113 5-1 regulator peripherals block diagram ......................................................................................................... 115 6-1 port configuration ............................................................................................................................... ......... 117 6-2 port 0 block diagram ............................................................................................................................... .... 119 6-3 port 0 mode register (pm0) format ........................................................................................................... 120 6-4 port specified as output port ..................................................................................................................... 121 6-5 port specified as input port ........................................................................................................................ 122 6-6 pull-up resistor option register l (puol) format .................................................................................. 123 6-7 pull-up resistor specification (port 0) ....................................................................................................... 124 6-8 example of transistor drive ........................................................................................................................ 125 6-9 p12 (port 1) block diagram ........................................................................................................................ 127 6-10 p13 (port 1) block diagram ........................................................................................................................ 128 6-11 p14 (port 1) block diagram ........................................................................................................................ 129 6-12 block diagram of p10, p11, and p15 to p17 (port 1) ................................................................................ 130 6-13 port 1 mode register (pm1) format ........................................................................................................... 131 6-14 port 1 mode control register (pmc1) format ........................................................................................... 131 6-15 port specified as output port ..................................................................................................................... 132 list of figures (1/12) figure no. title page 24 preliminary users manual u13987ej1v0um00 6-16 port specified as input port ........................................................................................................................ 133 6-17 control specification ............................................................................................................................... ..... 134 6-18 pull-up resistor option register l (puol) format .................................................................................. 135 6-19 pull-up resistor specification (port 1) ....................................................................................................... 136 6-20 example of direct led drive ...................................................................................................................... 136 6-21 block diagram of p20 to p24, p26, and p27 (port 2) ............................................................................... 139 6-22 p25 (port 2) block diagram ........................................................................................................................ 140 6-23 port specified as input port ........................................................................................................................ 141 6-24 pull-up resistor option register l (puol) format .................................................................................. 141 6-25 pull-up specification (port 2) ...................................................................................................................... 142 6-26 p30 (port 3) block diagram ........................................................................................................................ 144 6-27 block diagram of p31 and p34 to p37 (port 3) ......................................................................................... 145 6-28 p32 (port 3) block diagram ........................................................................................................................ 146 6-29 p33 (port 3) block diagram ........................................................................................................................ 147 6-30 port 3 mode register (pm3) format ........................................................................................................... 148 6-31 port 3 mode control register (pmc3) format ........................................................................................... 149 6-32 port specified as output port ..................................................................................................................... 150 6-33 port specified as input port ........................................................................................................................ 151 6-34 control specification ............................................................................................................................... ..... 152 6-35 pull-up resistor option register l (puol) format .................................................................................. 153 6-36 pull-up specification (port 3) ...................................................................................................................... 154 6-37 port 4 block diagram ............................................................................................................................... .... 155 6-38 port 4 mode register (pm4) format ........................................................................................................... 156 6-39 port specified as output port ..................................................................................................................... 157 6-40 port specified as input port ........................................................................................................................ 158 6-41 pull-up resistor option register l (puol) format .................................................................................. 159 6-42 pull-up specification (port 4) ...................................................................................................................... 160 6-43 example of direct led drive ...................................................................................................................... 161 6-44 port 5 block diagram ............................................................................................................................... .... 162 6-45 port 5 mode register (pm5) format ........................................................................................................... 163 6-46 port specified as output port ..................................................................................................................... 164 6-47 port specified as input port ........................................................................................................................ 165 6-48 pull-up resistor option register l (puol) format .................................................................................. 166 6-49 pull-up specification (port 5) ...................................................................................................................... 167 6-50 example of direct led drive ...................................................................................................................... 168 6-51 p60 to p63 (port 6) block diagram ............................................................................................................ 170 6-52 p64 and p65 (port 6) block diagram ......................................................................................................... 171 6-53 p66 (port 6) block diagram ........................................................................................................................ 172 6-54 p67 (port 6) block diagram ........................................................................................................................ 173 6-55 port 6 mode register (pm6) format ........................................................................................................... 175 6-56 port specified as output port ..................................................................................................................... 176 list of figures (2/12) figure no. title page 25 preliminary users manual u13987ej1v0um00 6-57 port specified as input port ........................................................................................................................ 177 6-58 pull-up resistor option register l (puol) format .................................................................................. 178 6-59 pull-up specification (port 6) ...................................................................................................................... 178 6-60 port 7 block diagram ............................................................................................................................... .... 179 6-61 port 7 mode register (pm7) format ........................................................................................................... 180 6-62 port specified as output port ..................................................................................................................... 181 6-63 port specified as input port ........................................................................................................................ 182 6-64 port 9 block diagram ............................................................................................................................... .... 183 6-65 port 9 mode register (pm9) format ........................................................................................................... 184 6-66 port specified as output port ..................................................................................................................... 185 6-67 port specified as input port ........................................................................................................................ 186 6-68 pull-up resistor option register h (puoh) format ................................................................................. 187 6-69 pull-up specification (port 9) ...................................................................................................................... 187 6-70 p100 to p104 (port 10) block diagram ...................................................................................................... 189 6-71 p105 (port 10) block diagram .................................................................................................................... 190 6-72 p106 (port 10) block diagram .................................................................................................................... 191 6-73 p107 (port 10) block diagram .................................................................................................................... 192 6-74 port 10 mode register (pm10) format ...................................................................................................... 193 6-75 port 10 mode control register (pmc10) format ....................................................................................... 193 6-76 port specified as output port ..................................................................................................................... 194 6-77 port specified as input port ........................................................................................................................ 195 6-78 control specification ............................................................................................................................... ..... 196 6-79 pull-up resistor option register h (puoh) format ................................................................................. 197 6-80 pull-up specification (port 10) .................................................................................................................... 197 7-1 real-time output port block diagram ........................................................................................................ 202 7-2 real-time output port control register (rtpc) format .......................................................................... 203 7-3 port 0 buffer register (p0h, p0l) configuration ....................................................................................... 204 7-4 real-time output port operation timing ................................................................................................... 207 7-5 real-time output port operation timing (2-channel independent control example) ............................... 208 7-6 real-time output port operation timing ................................................................................................... 209 7-7 real-time output function control register settings ............................................................................... 210 7-8 real-time output function setting procedure ........................................................................................... 210 7-9 interrupt request servicing when real-time output function is used .................................................... 211 8-1 timer block diagram ............................................................................................................................... .... 214 9-1 timer/event counter 0 block diagram ....................................................................................................... 219 9-2 timer control register 0 (tmc0) format ................................................................................................... 221 9-3 prescaler mode register 0 (prm0) format ............................................................................................... 222 9-4 capture/compare control register 0 (crc0) format ............................................................................... 223 list of figures (3/12) figure no. title page 26 preliminary users manual u13987ej1v0um00 9-5 timer output control register (toc) format ............................................................................................ 224 9-6 one-shot pulse output control register (ospc) format ......................................................................... 225 9-7 basic operation of timer counter 0 (tm0) ................................................................................................ 227 9-8 tm0 clearance by match with compare register (cr01) ........................................................................ 228 9-9 clear operation when ce0 bit is cleared (0) ............................................................................................ 229 9-10 timer/event counter 0 external event count timing ................................................................................ 230 9-11 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 231 9-12 to distinguish whether one or no valid edge has been input with external event counter .................. 232 9-13 compare operation ............................................................................................................................... ...... 233 9-14 tm0 clearance after match detection ........................................................................................................ 234 9-15 capture operation ............................................................................................................................... ........ 235 9-16 toggle output operation ............................................................................................................................. 23 8 9-17 pwm pulse output ............................................................................................................................... ....... 240 9-18 example of pwm output using tm0 .......................................................................................................... 241 9-19 example of pwm output when cr00 = ffffh ........................................................................................ 241 9-20 example of compare register (cr00) rewrite ......................................................................................... 242 9-21 example of 100% duty with pwm output .................................................................................................. 243 9-22 when timer/event counter 0 is stopped during pwm signal output ..................................................... 244 9-23 example of ppg output using tm0 ........................................................................................................... 245 9-24 example of ppg output when cr00 = cr01 ............................................................................................ 246 9-25 example of compare register (cr00) rewrite ......................................................................................... 247 9-26 example of 100% duty with ppg output ................................................................................................... 248 9-27 example of extended ppg output cycle ................................................................................................... 249 9-28 when timer/event counter 0 is stopped during ppg signal output ....................................................... 250 9-29 example of software triggered one-shot pulse output ........................................................................... 251 9-30 interval timer operation (1) timing ............................................................................................................ 252 9-31 control register settings for interval timer operation (1) ........................................................................ 253 9-32 interval timer operation (1) setting procedure ......................................................................................... 253 9-33 interval timer operation (1) interrupt request servicing .......................................................................... 253 9-34 interval timer operation (2) timing ............................................................................................................ 254 9-35 control register settings for interval timer operation (2) ........................................................................ 255 9-36 interval timer operation (2) setting procedure ......................................................................................... 255 9-37 pulse width measurement timing .............................................................................................................. 256 9-38 control register settings for pulse width measurement .......................................................................... 257 9-39 pulse width measurement setting procedure ........................................................................................... 257 9-40 interrupt request servicing that calculates pulse width .......................................................................... 258 9-41 example of timer/event counter 0 pwm signal output ........................................................................... 259 9-42 control register settings for pwm output operation ............................................................................... 259 9-43 pwm output setting procedure .................................................................................................................. 260 9-44 changing pwm output duty ....................................................................................................................... 261 list of figures (4/12) figure no. title page 27 preliminary users manual u13987ej1v0um00 9-45 example of timer/event counter 0 ppg signal output ............................................................................ 262 9-46 control register settings for ppg output operation ................................................................................ 262 9-47 ppg output setting procedure ................................................................................................................... 263 9-48 changing ppg output duty ........................................................................................................................ 264 9-49 example of timer/event counter 0 one-shot pulse output ..................................................................... 265 9-50 control register settings for one-shot pulse output ............................................................................... 266 9-51 one-shot pulse output setting procedure ................................................................................................. 267 9-52 operation when counting is started ........................................................................................................... 268 9-53 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 269 9-54 to distinguish whether one or no valid edge has been input with external event counter .................. 270 10-1 timer/event counter 1 block diagram ....................................................................................................... 274 10-2 timer control register 1 (tmc1) format ................................................................................................... 277 10-3 prescaler mode register 1 (prm1) format ............................................................................................... 278 10-4 capture/compare control register 1 (crc1) format ............................................................................... 279 10-5 basic operation in 8-bit operation mode (bw1 = 0) ................................................................................. 281 10-6 basic operation in 16-bit operation mode (bw1 = 1) ............................................................................... 282 10-7 tm1 clearance by match with compare register (cr10, cr11) ............................................................. 283 10-8 tm1 clearance after capture operation .................................................................................................... 283 10-9 clear operation when ce1 bit is cleared (to 0) ........................................................................................ 284 10-10 timer/event counter 1 external event count timing ................................................................................ 285 10-11 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 286 10-12 to distinguish whether one or no valid edge has been input with external event counter .................. 287 10-13 compare operation in 8-bit operation mode ............................................................................................. 288 10-14 compare operation in 16-bit operation mode ........................................................................................... 289 10-15 tm1 clearance after match detection ........................................................................................................ 289 10-16 capture operation in 8-bit operation mode ............................................................................................... 290 10-17 capture operation in 16-bit operation mode ............................................................................................. 291 10-18 tm1 clearance after capture operation .................................................................................................... 292 10-19 interval timer operation (1) timing ............................................................................................................ 293 10-20 control register settings for interval timer operation (1) ........................................................................ 294 10-21 interval timer operation (1) setting procedure ......................................................................................... 295 10-22 interval timer operation (1) interrupt request servicing .......................................................................... 295 10-23 interval timer operation (2) timing (when cr11 is used as compare register) .................................... 296 10-24 control register settings for interval timer operation (2) ........................................................................ 297 10-25 interval timer operation (2) setting procedure ......................................................................................... 297 10-26 pulse width measurement timing (when cr11 is used as capture register) ........................................ 298 10-27 control register settings for pulse width measurement .......................................................................... 299 10-28 pulse width measurement setting procedure ........................................................................................... 300 list of figures (5/12) figure no. title page 28 preliminary users manual u13987ej1v0um00 10-29 interrupt request servicing that calculates pulse width .......................................................................... 300 10-30 operation when counting is started ........................................................................................................... 301 10-31 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 302 10-32 to distinguish whether one or no valid edge has been input with external event counter .................. 303 11-1 timer/event counter 2 block diagram ....................................................................................................... 309 11-2 timer control register 1 (tmc1) format ................................................................................................... 312 11-3 prescaler mode register 1 (prm1) format ............................................................................................... 313 11-4 capture/compare control register 2 (crc2) format ............................................................................... 314 11-5 timer output control register (toc) format ............................................................................................ 315 11-6 basic operation in 8-bit operation mode (bw2 = 0) ................................................................................. 317 11-7 basic operation in 16-bit operation mode (bw2 = 1) ............................................................................... 318 11-8 tm2 clearance by match with compare register (cr20/cr21) .............................................................. 319 11-9 tm2 clearance after capture operation .................................................................................................... 319 11-10 clear operation when ce2 bit is cleared (0) ............................................................................................ 320 11-11 timer/event counter 2 external event count timing ................................................................................ 321 11-12 example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 322 11-13 to distinguish whether one or no valid edge has been input with external event counter .................. 323 11-14 one-shot timer operation .......................................................................................................................... 324 11-15 compare operation in 8-bit operation mode ............................................................................................. 325 11-16 compare operation in 16-bit operation mode ........................................................................................... 326 11-17 tm2 clearance after match detection ........................................................................................................ 327 11-18 capture operation in 8-bit operation mode ............................................................................................... 328 11-19 capture operation in 16-bit operation mode ............................................................................................. 329 11-20 tm2 clearance after capture operation .................................................................................................... 330 11-21 toggle output operation ............................................................................................................................. 33 2 11-22 pwm pulse output (bw2 = 0) .................................................................................................................... 335 11-23 pwm pulse output (bw2 = 1) .................................................................................................................... 336 11-24 example of pwm output using tm2w ....................................................................................................... 337 11-25 example of pwm output when cr20w = ffffh ..................................................................................... 337 11-26 example of compare register (cr20w) rewrite ...................................................................................... 338 11-27 example of 100% duty with pwm output .................................................................................................. 338 11-28 when timer/event counter 2 is stopped during pwm signal output ..................................................... 339 11-29 example of ppg output using tm2 ........................................................................................................... 341 11-30 example of ppg output when cr20 = cr21 ............................................................................................ 342 11-31 example of compare register rewrite ...................................................................................................... 343 11-32 example of 100% duty with ppg output ................................................................................................... 344 11-33 example of extended ppg output cycle ................................................................................................... 345 11-34 when timer/event counter 2 is stopped during ppg signal output ....................................................... 346 list of figures (6/12) figure no. title page 29 preliminary users manual u13987ej1v0um00 11-35 interval timer operation (1) timing ............................................................................................................ 347 11-36 control register settings for interval timer operation (1) ........................................................................ 348 11-37 interval timer operation (1) setting procedure ......................................................................................... 349 11-38 interval timer operation (1) interrupt request servicing .......................................................................... 349 11-39 interval timer operation (2) timing ............................................................................................................ 350 11-40 control register settings for interval timer operation (2) ........................................................................ 351 11-41 interval timer operation (2) setting procedure ......................................................................................... 352 11-42 pulse width measurement timing .............................................................................................................. 353 11-43 control register settings for pulse width measurement .......................................................................... 354 11-44 pulse width measurement setting procedure ........................................................................................... 355 11-45 interrupt request servicing that calculates pulse width .......................................................................... 355 11-46 example of timer/event counter 2 pwm signal output ........................................................................... 356 11-47 control register settings for pwm output operation ............................................................................... 357 11-48 pwm output setting procedure .................................................................................................................. 358 11-49 changing pwm output duty ....................................................................................................................... 359 11-50 example of timer/event counter 2 ppg signal output ............................................................................ 360 11-51 control register settings for ppg output operation ................................................................................ 361 11-52 ppg output setting procedure ................................................................................................................... 362 11-53 changing ppg output duty ........................................................................................................................ 363 11-54 external event counter operation (single edge) ....................................................................................... 364 11-55 control register settings for external event counter operation .............................................................. 365 11-56 external event counter operation setting procedure ............................................................................... 365 11-57 one-shot timer operation .......................................................................................................................... 366 11-58 control register settings for one-shot timer operation .......................................................................... 367 11-59 one-shot timer operation setting procedure ........................................................................................... 368 11-60 one-shot timer operation start procedure from second time onward .................................................. 368 11-61 operation when counting is started ........................................................................................................... 369 11-62 example of the case where external event counter does not distinguish between one valid edge input and no valid edge input ......................................................................................... 370 11-63 to distinguish whether one or no valid edge has been input with external event counter .................. 371 12-1 timer 3 block diagram ............................................................................................................................... . 374 12-2 timer control register 0 (tmc0) format ................................................................................................... 376 12-3 prescaler mode register 0 (prm0) format ............................................................................................... 377 12-4 basic operation in 8-bit operation mode (bw3 = 0) ................................................................................. 378 12-5 basic operation in 16-bit operation mode (bw3 = 1) ............................................................................... 379 12-6 tm3 clearance by match with compare register (cr30) ........................................................................ 380 12-7 clear operation when ce3 bit is cleared (0) ............................................................................................ 381 12-8 compare operation ............................................................................................................................... ...... 382 12-9 interval timer operation timing .................................................................................................................. 383 12-10 control register settings for interval timer operation .............................................................................. 384 list of figures (7/12) figure no. title page 30 preliminary users manual u13987ej1v0um00 12-11 interval timer operation setting procedure ............................................................................................... 384 12-12 operation when counting is started ........................................................................................................... 385 13-1 watchdog timer block diagram .................................................................................................................. 387 13-2 watchdog timer mode register (wdm) format ........................................................................................ 389 14-1 watch timer mode register (wm) format ................................................................................................. 393 14-2 block diagram of watch timer .................................................................................................................... 394 15-1 pwm output unit configuration .................................................................................................................. 395 15-2 pwm control register (pwmc) format ..................................................................................................... 397 15-3 pwm prescaler register (pwpr) format .................................................................................................. 398 15-4 basic pwm output operation ..................................................................................................................... 399 15-5 pwm output active level setting ............................................................................................................... 400 15-6 pwm output timing example 1 (pwm pulse width rewrite cycle = 2 12 /f pwmc ) ......................................... 401 15-7 pwm output timing example 2 (pwm pulse width rewrite cycle = 2 8 /f pwmc ) .......................................... 402 16-1 a/d converter block diagram ..................................................................................................................... 404 16-2 example of capacitor connection on a/d converter pins ........................................................................ 405 16-3 a/d converter mode register (adm) format ............................................................................................ 408 16-4 a/d current cut select register (iead) format ........................................................................................ 410 16-5 a/d current cut select register function .................................................................................................. 410 16-6 basic a/d converter operation ................................................................................................................... 412 16-7 relationship between analog input voltage and a/d conversion result ................................................. 413 16-8 select mode operation timing .................................................................................................................... 415 16-9 scan mode 0 operation timing ................................................................................................................... 416 16-10 scan mode 1 operation timing ................................................................................................................... 417 16-11 software start select mode a/d conversion operation ............................................................................ 418 16-12 software start scan mode a/d conversion operation .............................................................................. 419 16-13 hardware start select mode a/d conversion operation ........................................................................... 421 16-14 hardware start scan mode a/d conversion operation ............................................................................. 422 16-15 example of capacitor connection on a/d converter pins ........................................................................ 424 17-1 example of serial interface ......................................................................................................................... 425 18-1 switching between asynchronous serial interface mode and 3-wire serial i/o mode ............................ 428 18-2 asynchronous serial interface block diagram ........................................................................................... 430 18-3 format of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) ......................................................................... 433 18-4 format of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) ........................................................................ 434 18-5 asynchronous serial interface transmit/receive data format ................................................................. 435 list of figures (8/12) figure no. title page 31 preliminary users manual u13987ej1v0um00 18-6 asynchronous serial interface transmission completion interrupt timing .............................................. 437 18-7 asynchronous serial interface reception completion interrupt timing .................................................... 438 18-8 receive error timing ............................................................................................................................... .... 439 18-9 example of 3-wire serial i/o system configuration .................................................................................. 440 18-10 3-wire serial i/o mode block diagram ....................................................................................................... 441 18-11 format of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) ................................................................................... 443 18-12 3-wire serial i/o mode timing .................................................................................................................... 444 18-13 example of connection to 2-wire serial i/o .............................................................................................. 445 18-14 baud rate generator block diagram ......................................................................................................... 449 18-15 format of baud rate generator control register (brgc) and baud rate generator control register 2 (brgc2) ................................................................................... 451 19-1 clocked serial interface block diagram ..................................................................................................... 458 19-2 format of clocked serial interface mode register (csim) and clocked serial interface mode register 3 (csim3) ................................................................................... 459 19-3 example of 3-wire serial i/o system configuration .................................................................................. 461 19-4 3-wire serial i/o mode timing .................................................................................................................... 462 19-5 operation when reception is disabled ....................................................................................................... 464 20-1 iebus transmission signal format ............................................................................................................. 469 20-2 master address field ............................................................................................................................... .... 470 20-3 slave address field ............................................................................................................................... ...... 471 20-4 control field ............................................................................................................................... .................. 473 20-5 telegraph length field ............................................................................................................................... . 473 20-6 data field ............................................................................................................................... ...................... 474 20-7 bit configuration of slave status ................................................................................................................ 477 20-8 configuration of lock address .................................................................................................................... 478 20-9 bit format of iebus ............................................................................................................................... ...... 479 20-10 iebus controller block diagram .................................................................................................................. 481 20-11 bus control register (bcr) format ........................................................................................................... 484 20-12 unit address register (uar) format .......................................................................................................... 486 20-13 slave address register (sar) format ....................................................................................................... 486 20-14 partner address register (par) format ..................................................................................................... 486 20-15 control data register (cdr) format .......................................................................................................... 487 20-16 interrupt generation timing (in case of <1>, <3>, <4>) ............................................................................ 488 20-17 interrupt generation timing (in case of <2>, <5>) ..................................................................................... 488 20-18 intie2 interrupt generation timing in locked status (in case of <4>, <5>) ........................................... 489 20-19 intie2 interrupt generation timing in locked status (in case of <3>) .................................................... 489 20-20 telegraph length register (dlr) format .................................................................................................. 490 20-21 data register (dr) format ......................................................................................................................... 491 list of figures (9/12) figure no. title page 32 preliminary users manual u13987ej1v0um00 20-22 unit status register (usr) format ............................................................................................................ 492 20-23 broadcasting communication flag operation example ............................................................................ 493 20-24 interrupt status register (isr) format ....................................................................................................... 494 20-25 slave status register (ssr) format .......................................................................................................... 498 20-26 success count register (scr) format ...................................................................................................... 499 20-27 communication count register (ccr) format .......................................................................................... 499 20-28 configuration of interrupt control block ..................................................................................................... 500 21-1 clock output function configuration .......................................................................................................... 511 21-2 clock output mode register (clom) format ............................................................................................ 513 21-3 clock output operation timing ................................................................................................................... 514 21-4 one-bit output port operation .................................................................................................................... 515 22-1 external interrupt mode register 0 (intm0) format ................................................................................. 518 22-2 external interrupt mode register 1 (intm1) format ................................................................................. 519 22-3 sampling clock selection register (scs0) format ................................................................................... 520 22-4 edge detection for pins p20, p25, and p26 .............................................................................................. 521 22-5 p21 pin edge detection .............................................................................................................................. 5 22 22-6 edge detection for pins p22 to p24 ........................................................................................................... 523 23-1 interrupt control registers ( icn) ............................................................................................................. 534 23-2 interrupt mask register (mk0, mk1) format ............................................................................................. 538 23-3 in-service priority register (ispr) format ................................................................................................ 540 23-4 interrupt mode control register (imc) format .......................................................................................... 541 23-5 watchdog timer mode register (wdm) format ........................................................................................ 542 23-6 program status word (pswl) format ....................................................................................................... 543 23-7 context switching operation by execution of a brkcs instruction ......................................................... 544 23-8 return from brkcs instruction software interrupt (retcsb instruction operation) .............................. 545 23-9 non-maskable interrupt request acknowledgment operations ................................................................ 547 23-10 interrupt acknowledgment processing algorithm ....................................................................................... 551 23-11 context switching operation by generation of an interrupt request ....................................................... 552 23-12 return from interrupt that uses context switching by means of retcs instruction .............................. 553 23-13 examples of servicing when another interrupt request is generated during interrupt service ............ 555 23-14 examples of servicing of simultaneously generated interrupts ............................................................... 558 23-15 differences in level 3 interrupt acknowledgment according to imc register setting ............................. 559 23-16 differences between vectored interrupt and macro service processing .................................................. 560 23-17 macro service processing sequence ......................................................................................................... 563 23-18 operation at end of macro service when vcie = 0 .................................................................................. 564 23-19 operation at end of macro service when vcie = 1 .................................................................................. 565 23-20 macro service control word format .......................................................................................................... 566 23-21 macro service mode register format ........................................................................................................ 567 list of figures (10/12) figure no. title page 33 preliminary users manual u13987ej1v0um00 23-22 macro service data transfer processing flow (type a) ........................................................................... 570 23-23 type a macro service channel ................................................................................................................... 572 23-24 asynchronous serial reception .................................................................................................................. 573 23-25 macro service data transfer processing flow (type b) ........................................................................... 575 23-26 type b macro service channel ................................................................................................................... 576 23-27 parallel data input synchronized with external interrupts ........................................................................ 577 23-28 parallel data input timing ........................................................................................................................... 578 23-29 macro service data transfer processing flow (type c) ........................................................................... 580 23-30 type c macro service channel .................................................................................................................. 582 23-31 stepping motor open loop control by real-time output port ................................................................. 584 23-32 data transfer control timing ...................................................................................................................... 585 23-33 single-phase excitation of 4-phase stepping motor ................................................................................. 587 23-34 1-2-phase excitation of 4-phase stepping motor ...................................................................................... 587 23-35 automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) ............................................................................... 588 23-36 automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) ............................................................................... 589 23-37 automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) ..................................................................................... 590 23-38 automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) ..................................................................................... 591 23-39 macro service data transfer processing flow (counter mode) ................................................................ 592 23-40 counter mode ............................................................................................................................... ............... 593 23-41 counting number of edges ......................................................................................................................... 593 23-42 interrupt request generation and acknowledgment (unit: clocks) ........................................................... 596 24-1 memory expansion mode register (mm) format ...................................................................................... 604 24-2 m pd784935 memory map ............................................................................................................................ 606 24-3 m pd784936 memory map ............................................................................................................................ 608 24-4 m pd784937 memory map ............................................................................................................................ 610 24-5 m pd784938 memory map ............................................................................................................................ 612 24-6 read timing ............................................................................................................................... .................. 614 24-7 write timing ............................................................................................................................... .................. 614 24-8 memory expansion mode register (mm) format ...................................................................................... 615 24-9 programmable wait control register (pwc1/pwc2) format ................................................................... 616 24-10 address wait function read/write timing ................................................................................................. 618 24-11 wait control spaces ............................................................................................................................... ..... 622 24-12 access wait function read timing ............................................................................................................ 623 24-13 access wait function write timing ............................................................................................................ 625 24-14 timing with external wait signal ................................................................................................................. 627 24-15 refresh mode register (rfm) format ....................................................................................................... 629 list of figures (11/12) figure no. title page 34 preliminary users manual u13987ej1v0um00 24-16 refresh area specification register (rfa) format ................................................................................... 630 24-17 pulse refresh operation in internal memory access ................................................................................ 631 24-18 refresh pulse output operation ................................................................................................................. 632 24-19 timing for return from self-refresh operation .......................................................................................... 633 24-20 hold mode register (hldm) format .......................................................................................................... 634 24-21 hold mode timing ............................................................................................................................... ......... 635 25-1 standby mode transition diagram .............................................................................................................. 637 25-2 standby function block diagram ................................................................................................................ 638 25-3 standby control register (stbc) format .................................................................................................. 640 25-4 oscillation stabilization time specification register (osts) format ....................................................... 641 25-5 stop mode release by nmi input ............................................................................................................. 648 25-6 stop mode release by intp4/intp5 input ............................................................................................. 649 25-7 example of address/data bus processing ................................................................................................. 654 26-1 reset signal acknowledgment .................................................................................................................... 657 26-2 power-on reset operation ......................................................................................................................... 658 26-3 reset input timing ............................................................................................................................... ........ 661 27-1 rom correction block diagram .................................................................................................................. 665 27-2 memory mapping example ( m pd784938) ................................................................................................... 666 27-3 rom correction address register (corah, coral) format ................................................................. 667 27-4 rom correction control register (corc) format .................................................................................... 668 28-1 internal memory size switching register (ims) format ............................................................................ 672 28-2 communication mode selection format ..................................................................................................... 673 28-3 flashpro ii and flashpro iii connection in 3-wire serial i/o mode .......................................................... 675 28-4 flashpro ii and flashpro iii connection in uart mode ............................................................................ 675 a-1 development tool configuration ................................................................................................................. 710 a-2 package drawing of ev-9200gf-100 (reference) (unit: mm) .................................................................... 718 a-3 recommended board mounting pattern of ev-9200gf-100 (reference) (unit: mm) ............................... 719 list of figures (12/12) figure no. title page 35 preliminary users manual u13987ej1v0um00 2-1 port 1 operation modes .............................................................................................................................. 5 5 2-2 port 2 operation modes .............................................................................................................................. 5 6 2-3 port 3 operation modes .............................................................................................................................. 5 7 2-4 port 6 operation modes .............................................................................................................................. 5 8 2-5 pin input/output circuit types and recommended connection of unused pins ..................................... 62 3-1 vector table ............................................................................................................................... ................... 75 3-2 internal ram area ............................................................................................................................... ........ 78 3-3 internal memory size switching register (ims) setting value .................................................................. 82 3-4 register bank selection .............................................................................................................................. 8 5 3-5 correspondence between function names and absolute names ............................................................ 96 3-6 list of special function registers (sfrs) .................................................................................................. 98 4-1 time required to change division ratio ................................................................................................... 110 6-1 port functions ............................................................................................................................... ............... 118 6-2 number of input/output ports ..................................................................................................................... 118 6-3 port 1 operation modes .............................................................................................................................. 1 26 6-4 port 2 operation modes .............................................................................................................................. 1 37 6-5 port 3 operation modes .............................................................................................................................. 1 43 6-6 port 4 operation modes .............................................................................................................................. 1 56 6-7 port 5 operation modes .............................................................................................................................. 1 63 6-8 port 6 operation modes .............................................................................................................................. 1 69 6-9 port 6 control pin function ......................................................................................................................... 174 6-10 p60 to p65 control pin specification .......................................................................................................... 174 6-11 port 10 operation modes ............................................................................................................................ 188 7-1 operations when port 0 and port 0 buffer registers (p0h, p0l) are manipulated ................................. 204 7-2 real-time output port output triggers (when p0mh = p0ml = 1) .......................................................... 206 8-1 operations of timer ............................................................................................................................... ...... 213 9-1 timer/event counter 0 interval time .......................................................................................................... 215 9-2 timer/event counter 0 programmable square-wave output setting range ........................................... 216 9-3 timer/event counter 0 pulse width measurement range ........................................................................ 217 9-4 timer/event counter 0 pulse width measurement time ........................................................................... 218 9-5 timer output (to0/to1) operations .......................................................................................................... 237 9-6 to0, to1 toggle output (f xx = 12.58 mhz) ............................................................................................... 239 9-7 to0, to1 pwm cycle (f xx = 12.58 mhz) ................................................................................................... 240 9-8 to0 ppg output (f xx = 12.58 mhz) ........................................................................................................... 246 list of tables (1/3) table no. title page 36 preliminary users manual u13987ej1v0um00 list of tables (2/3) table no. title page 10-1 timer/event counter 1 intervals ................................................................................................................. 271 10-2 timer/event counter 1 pulse width measurement range ........................................................................ 272 10-3 timer/event counter 1 pulse width measurement time ........................................................................... 273 10-4 maximum input frequency and minimum input pulse width that can be counted as events ................ 285 11-1 timer/event counter 2 intervals ................................................................................................................. 305 11-2 timer/event counter 2 programmable square-wave output setting range ........................................... 306 11-3 timer/event counter 2 pulse width measurement range ........................................................................ 307 11-4 clocks enabled to be input to timer/event counter 2 ............................................................................... 307 11-5 timer output (to2/to3) operations .......................................................................................................... 331 11-6 to2/to3 toggle output (f xx = 12.58 mhz) ................................................................................................ 333 11-7 to2/to3 pwm cycle (f xx = 12.58 mhz, bw2 = 0) ................................................................................... 335 11-8 to2/to3 pwm cycle (f xx = 12.58 mhz, bw2 = 1) ................................................................................... 336 11-9 to2 ppg output (f xx = 12.58 mhz) ........................................................................................................... 341 12-1 timer 3 intervals ............................................................................................................................... ........... 373 14-1 relation between count clock and watch timer operation ..................................................................... 394 16-1 a/d conversion time ............................................................................................................................... .... 414 18-1 differences between uart/ioe1 and uart2/ioe2 names ..................................................................... 427 18-2 receive error causes ............................................................................................................................... ... 439 18-3 baud rate setting methods ........................................................................................................................ 454 18-4 examples of brgc settings when baud rate generator is used ........................................................... 454 18-5 examples of settings when external baud rate input (asck) is used ................................................... 455 19-1 differences in name between ioe0 and ioe3 ........................................................................................... 457 20-1 transfer rate and maximum number of transmit bytes in communication mode 1 .............................. 468 20-2 contents of control bits .............................................................................................................................. 4 72 20-3 control field for locked slave unit ............................................................................................................ 473 20-4 control field for unlocked slave unit ......................................................................................................... 473 20-5 contents of telegraph length bit ................................................................................................................ 473 20-6 meaning of slave status ............................................................................................................................. 47 7 20-7 comparison between existing and simple iebus interface functions ..................................................... 480 20-8 internal registers of iebus controller ........................................................................................................ 483 20-9 interrupt source list ............................................................................................................................... ..... 501 20-10 iebus controller operation (slave status request) of m pd784938 subseries ....................................... 510 22-1 pins p20 to p26 and use of detected edge .............................................................................................. 517 37 preliminary users manual u13987ej1v0um00 23-1 interrupt request service modes ............................................................................................................... 525 23-2 interrupt request sources .......................................................................................................................... 526 23-3 control registers ............................................................................................................................... .......... 530 23-4 interrupt control register flags corresponding to interrupt request ...................................................... 531 23-5 multiple interrupt servicing .......................................................................................................................... 554 23-6 interrupts for which macro service can be used ....................................................................................... 561 23-7 interrupt acknowledge processing time ..................................................................................................... 597 23-8 macro service processing time .................................................................................................................. 598 24-1 system clock frequency and refresh pulse output cycle when pseudo-static ram is used ............. 630 25-1 operating states in halt mode ................................................................................................................. 642 25-2 halt mode release and operations after release .................................................................................. 643 25-3 halt mode release by maskable interrupt request ................................................................................ 645 25-4 operating states in stop mode ................................................................................................................. 646 25-5 stop mode release and operations after release ................................................................................. 647 25-6 operating states in idle mode .................................................................................................................. 650 25-7 idle mode release and operations after release ................................................................................... 651 26-1 pin statuses during reset input and after reset release ....................................................................... 658 26-2 hardware status after reset ....................................................................................................................... 659 27-1 differences between 78k/iv rom correction and 78k/0 rom correction .............................................. 664 27-2 rom correction configuration .................................................................................................................... 665 28-1 differences between the m pd78f4938 mask rom versions .................................................................... 671 28-2 internal memory size switching register (ims) settings .......................................................................... 672 28-3 communication mode ............................................................................................................................... ... 673 28-4 flash memory programming functions ...................................................................................................... 674 29-1 list of instructions by 8-bit addressing ...................................................................................................... 705 29-2 list of instructions by 16-bit addressing .................................................................................................... 706 29-3 list of instructions by 24-bit addressing .................................................................................................... 707 29-4 list of instructions by bit manipulation instruction addressing ................................................................. 707 29-5 list of instructions by call/return instruction/branch instruction addressing .......................................... 708 list of tables (3/3) table no. title page 38 preliminary users manual u13987ej1v0um00 [memo] 39 preliminary users manual u13987ej1v0um00 chapter 1 general the m pd784938 subseries consists of 78k/iv series products that combine a 78k/iv series cpu core enabling mounting large-capacity memory and a iebus tm (inter equipment bus tm ) controller. the 78k/iv series consists of 16-bit single-chip microcontrollers, and comes with a high-performance cpu that has various functions including a function to access 1-mbyte memory spaces. the m pd784938 subseries is based on the m pd784908 subseries. it features expanded internal rom and ram capacities and the addition of a rom correction function. the m pd784938 has a 256-kbyte mask rom and 10,240-byte ram on chip. besides an iebus controller, it features among other things a high-performance timer counter, an 8-bit a/d converter, a pwm output function, a 2-channel independent serial interface, and a watch timer. the m pd784937 replaces the mask rom of the m pd784938 with a 192-kbyte mask rom. the m pd784936 replaces the mask rom and ram of the m pd784938 with a 128-kbyte mask rom and a 6,656-byte ram. the m pd784935 replaces the mask rom and ram of the m pd784938 with a 96-kbyte mask rom and a 5,120-byte ram. the m pd78f4938 replaces the mask rom of the m pd784938 with flash memory. the m pd784938 subseries product lineup is as follows. these models can be used in the following fields: ? car audio, etc. pd784936 pd78f4938 flash memory ram 256 kbytes 10,240 bytes flash memory models pd784938 rom ram 256 kbytes 10,240 bytes mask rom models pd784937 rom ram 192 kbytes 8,192 bytes rom ram 128 kbytes 6,656 bytes pd784935 rom ram 96 kbytes 5,120 bytes m m m m m chapter 1 general 40 preliminary users manual u13987ej1v0um00 78k/iv series product lineup pd784026 pd784038y i 2 c bus supported pd784038 enhanced internal memory capacity, pin compatible with the pd784026 pd784225y multi-master i 2 c bus supported pd784225 80 pins, added rom correction pd784218y multi-master i 2 c bus supported multi-master i 2 c bus supported pd784218 enhanced internal memory capacity, added rom correction pd784928y multi-master i 2 c bus supported pd784928 enhanced function of the pd784915 pd784216y/ 784216ay pd784054 pd784216/ 784216a pd784046 pd784908 on-chip 10-bit a/d 100 pins, enhanced i/o and internal memory capacity enhanced a/d, 16-bit timer, and power management pd784915 for software servo control, on-chip analog circuit for vcr, enhanced timer enhanced function of the pd784908, enhanced internal memory capacity, added rom correction on-chip iebus controller pd784955 for dc inverter control pd784938 standard models assp models : in mass production : under development m m m m m m m m m m m m m m m m m m m m chapter 1 general 41 preliminary users manual u13987ej1v0um00 1.1 features 78k/iv series high-speed instruction execution ? minimum instruction execution time: 320 ns (@ 6.29-mhz operation) 160 ns (@ 12.58-mhz operation) instruction set suitable for control applications data memory expansion function (1-mbyte memory space: 2 bank specification pointers) interrupt controller (4-level priority system) ? vectored interrupt service/macro service/context switching standby functions: halt/stop/idle modes internal memory: ? rom mask rom: 256 kbytes ( m pd784938) 192 kbytes ( m pd784937) 128 kbytes ( m pd784936) 96 kbytes ( m pd784935) flash memory: 256 kbytes ( m pd78f4938) ? ram: 10,240 bytes ( m pd784938, 78f4938) 8,192 bytes ( m pd784937) 6,656 bytes ( m pd784936) 5,120 bytes ( m pd784935) i/o pins: 80 ? software programmable pull-up: 70 inputs ? direct led drive capability: 24 outputs ? direct transistor drive capability: 8 outputs ? n-ch open-drain: 4 outputs serial interface ? uart/ioe (3-wire serial i/o): 2 channels (with on-chip baud rate generator) ? csi (3-wire serial i/o): 2 channels real-time output ports (combination with timer/counter allows independent control of 2-system stepping motors) a/d converter (8-bit resolution 8 channels) pwm outputs (12-bit resolution 2 channels) on-chip simple model with iebus controller watch timer (operation with main clock possible in the idle mode) power-saving regulator high-performance timer/counter ? timer/event counter (16 bits) 3 units ? timer (16 bits) 1 unit watchdog timer: 1 channel clock output function: f clk , f clk /2, f clk /4, f clk /8, f clk /16 can be selected on-chip rom correction function chapter 1 general 42 preliminary users manual u13987ej1v0um00 1.2 ordering information part number package internal rom m pd784935gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784936gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784937gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784938gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4938gf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. chapter 1 general 43 preliminary users manual u13987ej1v0um00 1.3 pin configuration (top view) 1.3.1 normal operation mode ? 100-pin plastic qfp (14 20 mm) m pd784935gf- -3ba, 784936gf- -3ba, 784937gf- -3ba, 784938gf- -3ba, 78f4938gf-3ba notes 1. connect the ic (internally connected)/v pp pin directly to v ss . 2. connect the av dd pin directly to v dd . 3. connect the av ss pin directly to v ss . 4. the v pp pin is used only in the m pd78f4938. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p36/t02 p37/t03 p100 p101 p102 p103 p104 p105/sck3 p106/si3 p107/so3 reset xt2 xt1 v ss x2 x1 regoff regc v dd p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p66/wait/hldrq p65/wr p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 ic/v pp notes 1, 4 pwm1 pwm0 p17 p16 p15 p14/txd2/so2 p13/rxd2/si2 p12/asck2/sck2 p11 p10 astb/clkout p90 p91 p92 p93 p94 p95 p96 p97 p40/ad0 p41/ad1 p42/ad2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p35/to1 p34/to0 p33/so0 p32/sck0 p31/txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi tx rx av ss note 3 av ref1 av dd note 2 p77/ani7 p64/rd p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 v ss v dd p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 chapter 1 general 44 preliminary users manual u13987ej1v0um00 a8 to a19: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input asck, asck2: asynchronous serial clock astb: address strobe av dd : analog power supply av ref1 : analog reference voltage av ss : analog ground ci: clock input clkout: clock output hldak: hold acknowledge hldrq: hold request intp0 to intp5: interrupt from peripherals nmi: non-maskable interrupt p00 to p07: port0 p10 to p17: port1 p20 to p27: port2 p30 to p37: port3 p40 to p47: port4 p50 to p57: port5 p60 to p67: port6 p70 to p77: port7 p90 to p97: port9 p100 to p107: port10 pwm0, pwm1: pulse width modulation 0, 1 rd: read strobe refrq: refresh request regc: regulator capacitance regoff: regulator off reset: reset rx: iebus receive data rxd, rxd2: receive data sck0 to sck3: serial clock si0 to si3: serial input so0 to so3: serial output test: test to0 to to3: timer output txd, txd2: transmit data tx: iebus transmit data v dd : power supply v pp note : programming power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (watch) note the v pp pin is used only in the m pd78f4938. chapter 1 general 45 preliminary users manual u13987ej1v0um00 1.4 application system configuration example (car audio (tuner, deck)) remote controller signal receiver circuit fip tm led fip controller/driver key matrix audio system control circuit electronic volume eeprom tm pd16312, etc. pc2800a, etc. front panel pd784938 interrupt input general-purpose port 3-wire serial i/o iebus controller sio with automatic transmit/receive function 3-wire serial i/o cassette deck unit tuner pack iebus driver/ receiver iebus cd unit (changer, single cd, etc.) dsp unit tv unit m m m chapter 1 general 46 preliminary users manual u13987ej1v0um00 1.5 block diagram note m pd78f4938 only remark the capacities of the internal rom and ram varies depending on the product. programmable interrupt controller timer/event counter0 (16 bits) timer/event counter1 (16 bits) timer/event counter2 (16 bits) timer3 (16 bits) real-time output port a/d converter pwm 78 k/iv cpu core rom ram uart/ioe2 uart/ioe1 baud-rate generator baud-rate generator clocked serial interface clock output bus i/f port0 port1 port2 port3 port4 port5 port6 port7 nmi intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 av dd av ref1 av ss intp5 ani0 to ani7 intp0 to intp5 rxd/si1 txd/so1 asck/sck1 rxd2/si2 asck2/sck2 txd2/so2 sck0 so0 si0 astb/clkout ad0 to ad7 a8 to a15 a16 to a19 rd wr wait/hldrq refrq/hldak d0 to d7 note ce note a0 to a16 note oe note pgm note p00 to p07 p10 to p17 p30 to p37 p40 to p47 p50 to p57 p20 to p27 p60 to p67 p70 to p77 clocked serial interface3 sck3 so3 si3 port9 port10 p90 to p97 p100 to p107 tx rx reset test x1 x2 regc regoff v pp note v dd v ss xt1 xt2 system control (regulator) iebus controller watch timer watchdog timer chapter 1 general 47 preliminary users manual u13987ej1v0um00 1.6 list of functions part number m pd784935 m pd784936 m pd784937 m pd784938 m pd78f4938 item number of basic instructions 113 (mnemonics) general-purpose register 8 bits 32 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 320 ns/636 ns/1.27 m s/2.54 m s (@6.29-mhz operation) 160 ns/320 ns/636 ns/1.27 m s (@12.58-mhz operation) internal rom 96 kbytes 128 kbytes 192 kbytes 256 kbytes 256 kbytes memory (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) ram 5,120 bytes 6,656 bytes 8,192 bytes 10,240 bytes memory space 1 mbyte with program and data memories combined i/o port total 80 input 8 i/o 72 pins with led direct drive output 24 ancillary transistor direct drive 8 functions note n-ch open-drain 4 real-time output port 4 bits 2, or 8 bits 1 iebus controller internal (simple version) timer/counter timer/event counter 0 (16 bits): timer counter 1 pulse output capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/event counter 1 (16 bits): timer counter 1 real-time output port capture register 1 capture/compare register 1 compare register 1 timer/event counter 2: timer counter 1 pulse output capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer counter 1 compare register 1 watch timer generates interrupt request at intervals of 0.5 second (internal watch clock oscillator) main clock (12.58 mhz (max.)) or watch clock (32.7 khz) selectable as input clock clock output selectable from f clk , f clk /2, f clk /4, f clk /8, and f clk /16 (can also be used as 1-bit output port) pwm output 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) csi (3-wire serial i/o): 2 channels a/d converter 8-bit resolution 8 channels watchdog timer 1 channel standby halt/stop/idle mode note the pins with ancillary functions are included in the i/o pins. chapter 1 general 48 preliminary users manual u13987ej1v0um00 part number m pd784935 m pd784936 m pd784937 m pd784938 m pd78f4938 item interrupt hardware source 27 (internal: 20, external: 7 (sampling clock variable input: 1)) software source brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 6 4 levels of programmable priority 3 processing type: vectored interrupt/macro service/context switching supply voltage v dd = 4.0 to 5.5 v v dd = 4.5 to 5.5 v (main clock: @ f xx = 12.58-mhz operation, (main clock: internal system clock = @ f xx , f cyk = 79 ns) @ f xx = 12.58- v dd = 3.5 to 5.5 v mhz operation, (other than above, f cyk = 159 ns) internal system clock = @ f xx , f cyk = 79 ns) v dd = 4.0 to 5.5 v (other than above, f cyk = 159 ns) package 100-pin plastic qfp (14 20 mm) chapter 1 general 49 preliminary users manual u13987ej1v0um00 the outline of the timer is as follows (for details, refer to chapter 8 outline of timer ) name timer/event timer/event timer/event timer 3 item counter 0 counter 1 counter 2 count width 8 bits 16 bits operation mode interval timer 2ch 2ch 2ch 1ch external event counter one-shot timer function timer output 2ch 2ch toggle output pwm/ppg output one-shot pulse output note real-time output pulse width measurement 1 input 1 input 2 inputs number of interrupt requests 2 2 2 1 note the one-shot pulse output function is used to make a pulse output level active by software and inactive by hardware (interrupt request signal). this function is different from the one-shot timer function of timer/event counter 2 in nature. the outline of the serial interface is as follows (for details, refer to chapter 17 outline of serial interface ). function uart/ioe1 uart/ioe2 ioe0 ioe3 3-wire serial i/o mode (msb first/lsb first (msb first/lsb first (msb first/lsb first (msb first/lsb first switchable) switchable) switchable) switchable) asynchronous serial (on-chip dedicated (on-chip dedicated i/o mode baud rate generator ) baud rate generator ) sbi mode (msb first/lsb first (msb first/lsb first switchable) switchable) chapter 1 general 50 preliminary users manual u13987ej1v0um00 1.7 differences among products in m pd784938 subseries part number m pd784935 m pd784936 m pd784937 m pd784938 m pd78f4938 item internal memory rom 96 kbytes 128 kbytes 192 kbytes 256 kbytes 256 kbytes (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) ram 5,120 bytes 6,656 bytes 8,192 bytes 10,240 bytes 1.8 main differences with m pd784908 subseries the m pd784938 subseries replaces the prom of prom products in the m pd784908 subseries with flash memory and added a rom correction function. 51 preliminary users manual u13987ej1v0um00 chapter 2 pin functions 2.1 pin function lists 2.1.1 normal operation mode (1) port pins (1/2) pin name input/output alternate function function p00 to p07 input/output port 0 (p0): ? 8-bit input/output port ? can be used as real-time output ports (4 bits 2) ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? transistor drive capability p10 input/output p11 p12 asck2/sck2 p13 rxd2/si2 p14 txd2/so2 p15 to p17 p20 input nmi p21 intp0 p22 intp1 p23 intp2/ci p24 intp3 p25 intp4/asck/sck1 p26 intp5 p27 si0 p30 input/output rxd/si1 p31 txd/so1 p32 sck0 p33 so0 p34 to p37 to0 to to3 port 1 (p1): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? led drive capability port 2 (p2): ? 8-bit input/output port ? p20 cannot be used as a general-purpose port (non-maskable interrupt). input level can be confirmed in the interrupt routine. ? for p22 to p27, on-chip pull-up resistor connection can be specified by means of software in 6-bit units ? the p25/intp4/asck/sck1 pin operates as the sck1 output pin in accordance with the csim1 register specification port 3 (p3): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? p32 and p33 can be set in n-ch open-drain mode chapter 2 pin functions 52 preliminary users manual u13987ej1v0um00 (1) port pins (2/2) pin name input/output alternate function function p40 to p47 input/output ad0 to ad7 port 4 (p4): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? led drive capability p50 to p57 input/output a8 to a15 port 5 (p5): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? led drive capability p60 to p63 input/output a16 to a19 p64 rd p65 wr p66 wait/hldrq p67 refrq/hldak p70 to p77 input/output ani0 to ani7 port 7 (p7): ? 8-bit input/output port ? input/output can be specified in 1-bit units p90 to p97 input/output port 9 (p9): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software p100 to p104 input/output p105 sck3 p106 si3 p107 so3 port 6 (p6): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software port 10 (p10): ? 8-bit input/output port ? input/output can be specified in 1-bit units ? for input mode pins, on-chip pull-up resistor connection can be specified at once by means of software ? p105 and p107 can be set in n-ch open-drain mode chapter 2 pin functions 53 preliminary users manual u13987ej1v0um00 (2) non-port pins (1/2) pin name input/output alternate function function to0/to3 output p34 to p37 timer output ci input p23/intp2 count clock input to timer/event counter 2 rxd input p30/si1 serial data input (uart0) rxd2 p13/si2 serial data input (uart2) txd output p31/so1 serial data output (uart0) txd2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/rxd serial data input (3-wire serial i/o1) si2 p13/rxd2 serial data input (3-wire serial i/o2) si3 p106 serial data input (3-wire serial i/o3) so0 output p33 serial data output (3-wire serial i/o0) so1 p31/txd serial data output (3-wire serial i/o1) so2 p14/txd2 serial data output (3-wire serial i/o2) so3 p107 serial data output (3-wire serial i/o3) sck0 input/output p32 serial clock input/output (3-wire serial i/o0) sck1 p25/intp4/asck serial clock input/output (3-wire serial i/o1) sck2 p12/asck2 serial clock input/output (3-wire serial i/o2) sck3 p105 serial clock input/output (3-wire serial i/o3) nmi input p20 external interrupt requests intp0 p21 ? count clock input to timer/event counter 1 ? cr11 or cr12 capture trigger signal intp1 p22 ? count clock input to timer/event counter 2 ? cr22 capture trigger signal intp2 p23/ci ? count clock input to timer/event counter 2 ? cr21 capture trigger signal intp3 p24 ? count clock input to timer/event counter 0 ? cr02 capture trigger signal intp4 p25/asck0/sck1 intp5 p26 a/d converter conversion start trigger input ad0 to ad7 input/output p40 to p47 time division address/data bus (external memory connection) a8 to a15 output p50 to p57 upper address bus (external memory connection) a16 to a19 output p60 to p63 upper address with address extension (external memory connection) rd output p64 external memory read strobe wr output p65 external memory write strobe wait input p66/hldrq wait insertion refrq output p67/hldak external pseudo-static memory refresh pulse output hldrq input p66/wait bus hold request input hldak output p67/refrq bus hold response output chapter 2 pin functions 54 preliminary users manual u13987ej1v0um00 (2) non-port pins (2/2) pin name input/output alternate function function astb output clkout time division address (a0 to a7) latch timing output (during external memory access) clkout output astb clock output pwm0 output pwm output 0 pwm1 output pwm output 1 rx input data input (iebus) tx output data output (iebus) regc connection of capacitor for regulator output stabilization/power supply when regulator stops regoff regulator operation specification signal reset input chip reset x1 input system clock oscillation crystal connections x2 (clock can also be input to x1) xt1 input watch clock connection xt2 ani0 to ani7 input p70 to p77 a/d converter analog voltage inputs av ref1 a/d converter reference voltage application av dd a/d converter positive power supply av ss a/d converter gnd v dd positive power supply v ss gnd ic input v pp internally connected. connect directly to v ss (ic test pin). v pp ic flash memory programming mode setting. high voltage application during program write/verify. connect directly to v ss in normal operating mode. chapter 2 pin functions 55 preliminary users manual u13987ej1v0um00 2.2 pin functions 2.2.1 normal operation mode (1) p00 to p07 (port 0) ... 3-state input/output port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. input/output can be spe cified in 1-bit units by setting the port 0 mode register (pm0). each pin incorporates a software programmable pull-up resistor. p00 to p03 and p04 to p07 can output the port 0 buffer register (p0l, p0h) contents at any time interval as 4-bit or 8-bit real-time output port. the real-time output port control register (rtpc) is used to select whether this port is used as a norm al output port or a real-time output port. when reset is input, port 0 is set as an input port (output high-impedance state), and the output latch contents become undefined. (2) p10 to p17 (port 1) ... 3-state input/output port 1 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 1 m ode register (pm1). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. pins p12 to p14 can also be made to function as serial input/output pins by setting the port 1 mode control register (pmc1). when reset is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 2-1. port 1 operation modes pin name port mode control signal input/output mode operation to operate as control pin p10 input/output port p11 p12 asck2/sck2 input/output set (to 1) pmc12 bit of pmc1 p13 rxd2/si2 input set (to 1) pmc13 bit of pmc1 p14 txd2/so2 output set (to 1) pmc14 bit of pmc1 p15 to p17 (a) port mode p12 to p14 operate as port mode pins when the relevant bits of the port 1 mode control (pmc1) register are cleared (0), and p10 and p11 and p15 to p17 always operate as port mode pins. input/output can be specified in 1-bit units by setting the port 1 mode register (pm1). (b) control signal input/output mode p12 to p14 can be set as control pins in 1-bit units by setting the port 1 mode control (pmc1) register. (i) asck2/sck2 asck2 is the asynchronous serial interface baud rate clock input pin. sck2 is the serial clock input/output pin (in 3-wire serial i/o2 mode). (ii) rxd2/si2 rxd2 is the asynchronous serial interface serial data input pin. si2 is the serial data input pin (in 3-wire serial i/o2 mode). (iii) txd2/so2 txd2 is the asynchronous serial interface serial data output pin. so2 is the serial data output pin (in 3-wire serial i/o2 mode). chapter 2 pin functions 56 preliminary users manual u13987ej1v0um00 (3) p20 to p27 (port 2) ... input port 2 is an 8-bit input-only port. p22 to p27 incorporate a software programmable pull-up resistor. as well as operating as an input port, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see table 2-2 ). all 8 pins are schmitt-triggered inputs to prevent misoperation due to noise. also, pin p25 can also be made to function as a serial clock output pin by selecting the external clock as serial operation enabled with the clocked serial interface mode register 1 (csim1). table 2-2. port 2 operation modes port function p20 input port/nmi input note p21 input port/intp0 input/cr11 capture trigger input/ timer/event counter 1 count clock/real-time output port trigger signal p22 input port/intp1 input/cr22 capture trigger input p23 input port/intp2 input/ci input p24 input port/intp3 input/cr02 capture trigger input/ timer/event counter 0 count clock p25 input port/intp4 input/asck input/sck1 input/output p26 input port/intp5 input/a/d converter external trigger input p27 input port/si0 input note nmi input is acknowledged regardless of whether interrupts are enabled or disabled. (a) function as port pins the pin level can always be read or tested regardless of the alternate function pin operation. (b) functions as control signal input pins (i) nmi (non-maskable interrupt) the external non-maskable interrupt request input pin. rising edge detection or falling edge detection can be specified by setting the external interrupt mode register 0 (intm0). (ii) intp0 to intp5 (interrupt from peripherals) external interrupt request input pins. when the valid edge specified by the external interrupt mode register 0, 1 (intm0/intm1) is detected by pins intp0 to intp5, an interrupt is generated (see chapter 22 edge detection function ). in addition, pins intp0 to intp3 and intp5 are also used as external trigger input pins with the various functions shown below. ? intp0 ....... timer/event counter 1 capture trigger input pin timer/event counter 1 external count clock input pin real-time output port trigger input pin ? intp1 ....... timer/event counter 2 capture trigger input pin to capture register (cr22) ? intp2 ....... timer/event counter 2 external count clock input pin capture trigger input pin to capture/compare register (cr21) ? intp3 ....... timer/event counter 0 capture trigger input pin timer/event counter 0 external count clock input pin ? intp5 ....... a/d converter external trigger input pin chapter 2 pin functions 57 preliminary users manual u13987ej1v0um00 (iii) ci (clock input) the timer/event counter 2 external clock input pin. (iv) asck (asynchronous serial clock) the external baud rate clock input pin. (v) sck1 (serial clock) the serial clock input/output pin (in 3-wire serial i/o1 mode). (vi) si0 (serial input 0) the serial data input pin (in 3-wire serial i/o0 mode). (4) p30 to p37 (port 3) ... 3-state input/output port 3 is an 8-bit input/output port with an output latch. input/output can be specified bit-wise by setting the port 3 mode register (pm3). each pin incorporates a software programmable pull-up resistor. p32 and p33 can be set in the n-ch open- drain mode. in addition to its function as an input/output port, port 3 also has various control signal pin alternate functions. the operation mode can be specified in 1-bit units by setting the port 3 mode control register (pmc3), as shown in table 2-3. the pin level of any pin can always be read or tested regardless of the alternate-function operation. when reset is input, port 3 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 2-3. port 3 operation modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc3n = 0 pmc3n = 1 p30 input/output port rxd input / si1 input p31 txd output / so1 output p32 sck0 input/output p33 so0 output p34 to0 output p35 to1 output p36 to2 output p37 to3 output (a) port mode each port specified as port mode by the port 3 mode control register (pmc3) can be specified as input/output in 1- bit units by setting the port 3 mode register (pm3). (b) control signal input/output mode pins can be set as control pins in 1-bit units by setting the port 3 mode control register (pmc3). (i) rxd (receive data) /si1 (serial input 1) rxd is the asynchronous serial interface serial data input pin. si1 is the serial data input pin (in 3-wire serial i/o1 mode). chapter 2 pin functions 58 preliminary users manual u13987ej1v0um00 (ii) txd (transmit data) /so1 (serial output 1) txd is the asynchronous serial interface serial data output pin. so1 is the serial data output pin (in 3-wire serial i/o1 mode). (iii) sck0 (serial clock 0) sck0 is the clocked serial interface serial clock input/output pin (in 3-wire serial i/o 0 mode). (iv) so0 (serial output 0) so0 is the serial data output pin (in 3-wire serial i/o 0 mode). (v) to0 to to3 (timer output) the timer output pins. (5) p40 to p47 (port 4) ... 3-state input/output port 4 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 4 m ode register (pm4). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. port 4 also functions as the time division address/data bus (ad0 to ad7) by the memory expansion mode register (mm) when external memory or i/os are expanded. when reset is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. (6) p50 to p57 (port 5) ... 3-state input/output port 5 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 5 mode register (pm5). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. in addition, p50 to p57 can be selected by means of the memory expansion mode register (mm) in 2-bit units as pins that function as the address bus (a8 to a15) when external memory or i/os are expanded. when reset is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. (7) p60 to p67 (port 6) ... 3-state input/output port 6 is an 8-bit input/output port with an output latch. p60 to p67 incorporate a software programmable pull-up resistor. in addition to its function as a port, port 6 also has various alternate-function control signal pin functions, as shown in tab le 2-4. operations as control pins are performed by the respective function operations. when reset is input, p60 to p67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. table 2-4. port 6 operation modes pin name port mode control signal input/output mode operation to operate as control pin p60 to p63 input/output ports a16 to a19 output specified in 2-bit units by bits mm3 to mm0 of the mm p64 rd output external memory expansion mode is specified by bits mm3 p65 wr output to mm0 of the mm p66 wait input specified by setting bits pwn1 & pwn0 (n = 0 to 7) of the pwc1 & pwc2 and p66 to input mode hldrq input bus hold enabled by the hlde bit of the hldm p67 hldak output refrq output set (to 1) the rfen bit of the rfm chapter 2 pin functions 59 preliminary users manual u13987ej1v0um00 (a) port mode each port not set in the control mode can be set in the input or output mode in 1-bit units by using the port 6 mode register (pm6). (b) control signal input/output mode (i) a16 to a19 (address bus) upper address bus output pins in case of external memory space expansion (10000h to fffffh). these pins operate in accordance with the memory expansion mode register (mm). (ii) rd (read strobe) pin that outputs the strobe signal for an external memory read operation. operates in accordance with the memory expansion mode register (mm). (iii) wr (write strobe) pin that outputs the strobe signal for an external memory write operation. operates in accordance with the memory expansion mode register (mm). (iv) wait (wait) wait signal input pin. operates in accordance with the programmable wait control registers (pwc1, pwc2). (v) refrq (refresh request) this pin outputs refresh pulses to pseudo-static memory when this memory is connected externally. operates in accordance with the refresh mode register (rfm). (vi) hldrq (hold request) external bus hold request signal input pin. operates in accordance with the hold mode register (hldm). (vii) hldak (hold acknowledge) bus hold acknowledge signal output pin. operates in accordance with the hold mode register (hldm). (8) p70 to p77 (port 7) ... 3-state input/output port 7 is an 8-bit input/output port. in addition to operating as an input/output port, it also operates as the a/d converter analog input pins (ani0 to ani7). input/output can be specified in 1-bit units by setting the port 7 mode register (pm7). the levels of these pins can always be read or tested, regardless of the alternate-function operation. when reset is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. (9) p90 to p97 (port 9) ... 3-state input/output port 9 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 9 mode register (pm9). each pin incorporates a software programmable pull-up resistor. when reset is input, port 9 is set as an input port (output high-impedance state), and the output latch contents are undefined. chapter 2 pin functions 60 preliminary users manual u13987ej1v0um00 (10) p100 to p107 (port 10) ... 3-state input/output port 10 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 1 0 mode register (pm10). each pin incorporates a software programmable pull-up resistor. p105 and p107 can be set in the n-ch open-drain mode. p105 to p107 pins also function as the serial input/output pin by the port 10 mode control register (pmc10). when reset is input, port 10 is set as an input port (output high-impedance state), and the output latch contents are undefined. (11) astb (address strobe)/clkout (clock output) ... output this pin outputs the timing signal that latches address information externally in order to access an external address. it also operates as the pin that supplies the clock to an external device. (12) x1, x2 (crystal) the internal clock oscillation crystal connection pins. when the clock is supplied externally, it is input to the x1 pin. usu ally signal with the inverse phase of the x1 pin signal phase is input to the x2 pin (refer to 4.3.1 clock oscillator ). (13) reset (reset) ... input active-low reset input (14) av ref1 a/d converter reference voltage input pin (15) av dd a/d converter power supply pin. this should be made at the same potential as the v dd pin. (16) av ss a/d converter gnd pin. this should be made at the same potential as the v ss pin. (17) v dd positive power supply pins. all v dd pins should be connected to the positive power supply. (18) v ss gnd potential pins. all v ss pins should be connected to the ground. (19) xt1 and xt2 these pins connect a crystal for watch clock oscillation. (20) pwm0 and pwm1 these pins function as pwm output pins when so specified by the pwm control register (pwmc). (21) rx iebus data input pin (22) tx iebus data output pin (23) regc this pin connects a capacitor for stabilizing the regulator output. supply a voltage same as v dd to this pin when the regulator is stopped (refer to figure 5-1. regulator peripherals block diagram ). chapter 2 pin functions 61 preliminary users manual u13987ej1v0um00 (24) regoff this pin controls the regulator operation by operating or stopping the regulator. (25) v pp ( m pd78f4938) only high-voltage apply pin for flash memory programming mode setting and program write/verify (26) ic ic test pin. connect directly to v ss . chapter 2 pin functions 62 preliminary users manual u13987ej1v0um00 2.3 input/output circuits and connection of unused pins table 2-5 shows the input/output circuit types of the pins that have functions, and the connection method when that function is not used. each input/output circuit type is shown in figure 2-1. table 2-5. pin input/output circuit types and recommended connection of unused pins (1/2) pin name input/output input/output recommended connection circuit type of unused pins p00 to p07 5-a input/output input: connect to v dd p10, p11 output: leave open p12/asck2/sck2 8-a p13/rxd2/si2 5-a p14/txd2/so2 p15 to p17 p20/nmi 2 input connect to v dd or v ss p21/intp0 p22/intp1 2-a connect to v dd p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-a input/output input: connect to v dd output: leave open p26/intp5 2-a input connect to v dd p27/si0 p30/rxd/si1 5-a input/output input: connect to v dd p31/txd/so1 output: leave open p32/sck0 10-a p33/so0 p34/to0 to p37/to3 5-a p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p65/wr p66/wait/hldrq p67/refrq/hldak chapter 2 pin functions 63 preliminary users manual u13987ej1v0um00 table 2-5. pin input/output circuit types and recommended connection of unused pins (2/2) pin name input/output input/output recommended connection circuit type of unused pins p70/ani0 to p77/ani7 20 input/output input: connect to v dd or v ss p90 to p97 5-a output: leave open p100 to p104 p105/sck3 10-a p106/si3 8-a p107/so3 10-a astb/clkout 4 output leave open reset 2 input ic/v pp note 1 directly connect to v ss xt2 leave open xt1 input connect to v ss regoff 1 connect to v dd regc pwm0, pwm1 3 output leave open rx 2 input connect to v dd or v ss tx 3 output leave open av ref1 input connect to v ss av ss av dd connect to v dd note the v pp pin is used only in the m pd78f4938. caution if the input/output mode is undefined for an input/output alternate-function pin, it should be connected to v dd via a resistor of several tens of k w (especially when the reset input pin goes to the low-level input voltage or over upon powering on, and when input/output is switched by software.) remark the type numbers are standard for the 78k series, and therefore are not necessarily serial numbers within each product (there are non-incorporated circuits). chapter 2 pin functions 64 preliminary users manual u13987ej1v0um00 figure 2-1. pin input/output circuits p n in type 1 v dd type 2 type 4 type 8-a type 10-a type 2-a type 5-a type 20 in schmitt-triggered input with hysteresis characteristics. schmitt-triggered input with hysteresis characteristics. push-pull output allowing output to be set to high impedance (p-ch & n-ch both off). p n data output disable out v dd p n data output disable in/out in/out v dd p pullup enable v dd p n data output disable in/out p pullup enable open drain v dd v dd p in pullup enable v dd p n data output disable in/out p pullup enable v dd v dd input enable p n data output disable v dd input enable comparator p n v ref (threshold voltage) + - type 3 v dd p-ch n-ch out data chapter 2 pin functions 65 preliminary users manual u13987ej1v0um00 2.4 cautions when connecting unused pins, if the input/output mode is undefined for an input/output alternate function, it should be connected to v dd with a resistor of several tens of k w (especially when the reset input pin becomes the low-level input voltage or over upon powering on, and when input/output is switched by software.) 66 preliminary users manual u13987ej1v0um00 [memo] 67 preliminary users manual u13987ej1v0um00 chapter 3 cpu architecture 3.1 memory space the m pd784938 can access a 1-mbyte memory space. the mapping of the internal data area (special function registers and internal ram) depends on the location instruction. a location instruction must be executed after reset release, and can only be used once. the program after reset release must be as follows: rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn 68 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 (1) when location 0 instruction is executed ? internal memory the internal data area and internal rom area are follows: part number internal data area internal rom area m pd784935 0eb00h to 0ffffh 00000h to 0eaffh 10000h to 17fffh m pd784936 0e500h to 0ffffh 00000h to 0e4ffh 10000h to 1ffffh m pd784937 0df00h to 0ffffh 00000h to 0deffh 10000h to 2ffffh m pd784938 0d600h to 0ffffh 00000h to 0d5ffh m pd78f4938 10000h to 3ffffh caution the following areas of the internal rom that overlap the internal data area cannot be used when the location 0 instruction is executed. part number area that cannot be used m pd784935 0eb00h to 0ffffh (5,376 bytes) m pd784936 0e500h to 0ffffh (6,192 bytes) m pd784937 0df00h to 0ffffh (8,448 bytes) m pd784938 0d600h to 0ffffh (10,752 bytes) m pd78f4938 ? external memory the external memory is accessed in the external memory expansion mode. (2) when location 0fh instruction is executed ? internal memory the internal data area and internal rom area are follows: part number internal data area internal rom area m pd784935 feb00h to fffffh 00000h to 17fffh m pd784936 fe500h to fffffh 00000h to 1ffffh m pd784937 fdf00h to fffffh 00000h to 2ffffh m pd784938 fd600h to fffffh 00000h to 3ffffh m pd78f4938 ? external memory the external memory is accessed in the external memory expansion mode. 69 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-1. m pd784935 memory map notes 1. accessed in external memory expansion mode. 2. the 5,376 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 92,928 bytes when the location 0 instruction is executed, and 98,304 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. internal rom (32,768 bytes) (256 bytes) special function registers (sfrs) internal rom (60,160 bytes) internal ram (5,120 bytes) external memory note 1 (928 kbytes) note 1 note 2 internal rom (96 kbytes) when location 0 instruction is executed general-purpose registers (128 bytes) data area (512 bytes) program/data area (4,608 bytes) macro service control word area (42 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (5,120 bytes) external memory note 1 (944,896 bytes) (256 bytes) special function registers (sfrs) when location 0fh instruction is executed note 1 1 8 0 0 0 h 1 7 f f f h 0 e b 0 0 h 0 e a f f h 0 f f d f h 0 f f d 0 h 0 f f 0 0 h 0 f e f f h f f f f f h 0 0 8 0 0 h 0 0 7 f f h 0 f e f f h f f e f f h 0 f e 8 0 h 0 f e 7 f h 0 f e 3 9 h 0 f e 0 6 h 0 f d 0 0 h 0 f c f f h 0 e b 0 0 h 0 1 0 0 0 h 0 0 f f f h 0 0 0 8 0 h 0 0 0 7 f h 0 0 0 4 0 h 0 0 0 3 f h 0 0 0 0 0 h f f e 8 0 h f f e 7 f h f f e 2 f h f f e 0 6 h f f d 0 0 h f f c f f h f e b 0 0 h f f f f f h f f f d f h f f f d 0 h f f f 0 0 h f f e f f h f e b 0 0 h f e a f f h 0 0 0 0 0 h 0 0 0 0 0 h 0 e a f f h 1 8 0 0 0 h 1 7 f f f h 1 7 f f f h 1 0 0 0 0 h 0 f f f f h 1 7 f f f h 1 0 0 0 0 h note 4 note 4 70 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-2. m pd784936 memory map notes 1. accessed in external memory expansion mode. 2. the 6,912 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 124,160 bytes when the location 0 instruction is executed, and 131,072 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. internal rom (65,536 bytes) (256 bytes) special function registers (sfrs) internal rom (58,624 bytes) internal ram (6,656 bytes) external memory note 1 note 1 (896 kbytes) note 1 note 2 internal rom (128 kbytes) when location 0 instruction is executed general-purpose registers (128 bytes) data area (512 bytes) program/data area (6,144 bytes) macro service control word area (42 bytes) callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (6,656 bytes) external memory note 1 (910,720 bytes) (256 bytes) special function registers (sfrs) when location 0fh instruction is executed 2 0 0 0 0 h 1 f f f f h 0 e 5 0 0 h 0 e 4 f f h 0 f f d f h 0 f f d 0 h 0 f f 0 0 h 0 f e f f h f f f f f h 0 0 8 0 0 h 0 0 7 f f h 0 f e f f h f f e f f h 0 f e 8 0 h 0 f e 7 f h 0 f e 3 9 h 0 f e 0 6 h 0 f d 0 0 h 0 f c f f h 0 e 5 0 0 h 0 1 0 0 0 h 0 0 f f f h 0 0 0 8 0 h 0 0 0 7 f h 0 0 0 4 0 h 0 0 0 3 f h 0 0 0 0 0 h f f e 8 0 h f f e 7 f h f f e 2 f h f f e 0 6 h f f d 0 0 h f f c f f h f e 5 0 0 h f f f f f h f f f d f h f f f d 0 h f f f 0 0 h f f e f f h f e 5 0 0 h f e 4 f f h 0 0 0 0 0 h 0 0 0 0 0 h 0 e 4 f f h 2 0 0 0 0 h 1 f f f f h 1 f f f f h 1 0 0 0 0 h 0 f f f f h 1 f f f f h 1 0 0 0 0 h note 4 note 4 71 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-3. m pd784937 memory map notes 1. accessed in external memory expansion mode. 2. the 8,488 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 188,160 bytes when the location 0 instruction is executed, and 196,608 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. (256 bytes) special function registers (sfrs) internal rom (57,088 bytes) internal ram (8,192 bytes) external memory (832 kbytes) note 1 general-purpose registers (128 bytes) data area (512 bytes) program/data area (7,680 bytes) note 2 callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (8,192 bytes) external memory note 1 (843,520 bytes) (256 bytes) special function registers (sfr) internal rom (192 kbytes) note 4 note 4 when location 0 instruction is executed fdf00h fdeffh 30000h 2ffffh 00000h 0feffh 0fe80h 0fe7fh 00800h 007ffh 00000h 0fe39h 0fe06h 0fd00h 0fcffh 0df00h 2ffffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 0df00h 0deffh 00000h ffeffh ffe80h ffe7fh ffe2fh ffe06h ffd00h ffcffh fdf00h note 1 when location 0fh instruction is executed fffffh 2ffffh internal rom (131,072 bytes) 30000h 2ffffh 10000h 0deffh macro service control word area (42 bytes) 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh fffffh fffdfh fffd0h fff00h ffeffh 72 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-4. m pd784938, 78f4938 memory map notes 1. accessed in external memory expansion mode. 2. the 10,496 bytes of this area can be used as internal rom only when the location 0fh instruction is executed. 3. 251,647 bytes when the location 0 instruction is executed, and 262,143 bytes when the location 0fh instruction is executed. 4. base area, reset or interrupt entry area, excluding internal ram in the case of reset. 5. in the case of m pd78f4938: flash memory note 4 note 4 f f f f f h f f f d f h f f f d 0 h f f f 0 0 h f f e f f h f d 6 0 0 h f d 5 f f h 4 0 0 0 0 h 3 f f f f h 0 0 0 0 0 h 0 f e f f h 0 f e 8 0 h 0 f e 7 f h 0 0 8 0 0 h 0 0 7 f f h 0 0 0 0 0 h 0 f e 3 9 h 0 f e 0 6 h 0 f d 0 0 h 0 f c f f h 0 d 6 0 0 h 3 f f f f h 0 1 0 0 0 h 0 0 f f f h 0 0 0 8 0 h 0 0 0 7 f h 0 0 0 4 0 h 0 0 0 3 f h 0 d 6 0 0 h 0 d 5 f f h 00000h f f e f f h f f e 8 0 h f f e 7 f h f f e 3 9 h f f e 0 6 h f f d 0 0 h f f c f f h f d 6 0 0 h f f f f f h 1 0 0 0 0 h 0 f f f f h 0 f f d f h 0 f f d 0 h 0 f f 0 0 h 0 f e f f h 3 f f f f h 4 0 0 0 0 h 3 f f f f h 1 0 0 0 0 h 0 d e f f h (256 bytes) special function registers (sfrs) internal rom (54,768 bytes) internal ram (10,240 bytes ) external memory note 1 (832 kbytes) note 1 general-purpose register (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (9,728 bytes) note 2 callf entry area (2 kbytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (10,240 bytes) external memory note 1 (843,520 bytes) (256 bytes) special function registers (sfrs) internal rom (256 kbytes) when location 0 instruction is executed note 1 when location 0fh instruction is executed internal rom (196,608 bytes) 73 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.2 internal rom area the m pd784938 subseries products shown below incorporate rom which is used to store programs, table data, etc. if the internal rom area and internal data area overlap when the location 0 instruction is executed, the internal data area is accessed, and the overlapping part of the internal rom area cannot be accessed. part number internal rom address space location 0 instruction location 0fh instruction m pd784935 96 kbytes 8 bits 00000h to 0eaffh 00000h to 17fffh 10000h to 17fffh m pd784936 128 kbytes 8 bits 00000h to 0e4ffh 00000h to 1ffffh 10000h to 1ffffh m pd784937 192 kbytes 8 bits 00000h to 0deffh 00000h to 2ffffh 10000h to 2ffffh m pd784938 256 kbytes 8 bits 00000h to 0d5ffh 00000h to 3ffffh m pd78f4938 10000h to 3ffffh the internal rom can be accessed at high speed. normally, fetches are performed at the same speed as external rom, but if the ifch bit of the memory expansion mode register (mm) is set (to 1), the high-speed fetch function is used and interna l rom fetches are performed at high speed (2-byte fetch performed in 2 system clocks). when the instruction execution cycle equal to an external rom fetch is selected, wait insertion is performed by the wait function, but when high-speed fetches are used, wait insertion is not performed for internal rom. reset input sets the instruction execution cycle equal to the external rom fetch cycle. 74 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.3 base area the space from 0 to ffffh comprises the base area. the base area is the object for the following uses: ? reset entry address ? interrupt entry address ? callt instruction entry address ? 16-bit immediate addressing mode (with instruction address addressing) ? 16-bit direct addressing mode ? 16-bit register addressing mode (with instruction address addressing) ? 16-bit register indirect addressing mode ? short direct 16-bit memory indirect addressing mode the vector table area, callt instruction table area and callf instruction entry area are allocated to the base area. when the location 0 instruction is executed, the internal data area is located in the base area. note that, in the internal data area, program fetches cannot be performed from the internal high-speed ram area or special function register (sfr) area. also, internal ram area data should only be used after initialization has been performed. 75 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.3.1 vector table area the 64-byte area from 00000h to 0003fh is reserved as the vector table area. the vector table area stores the program start addresses used when a branch is made as the result of reset input or generation of an interrupt request. when context switching is used by an interrupt, the number of the register bank to be switched to is stored here. any portion not used as the vector table can be used as program memory or data memory. 16-bit values can be written to the vector table. therefore, branches can only be made within the base area. table 3-1. vector table vector table address interrupt source 0003ch operand error 0003eh brk 00000h reset (reset input) 00002h nmi 00004h wdt 00006h intp0 00008h intp1 0000ah intp2 0000ch intp3 0000eh intc00 00010h intc01 00012h intc10 00014h intc11 00016h intc20 00018h intc21 0001ah intc30 0001ch intp4 0001eh intp5 00020h intad 00022h intser1 00024h intsr1/intcsi1 00026h intst1 00028h intcsi 0002ah intser2 0002ch intsr2/intcsi2 0002eh intst2 00032h intie1 00034h intie2 00036h intw 00038h intcsi3 76 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.3.2 callt instruction table area the 1-byte call instruction (callt) subroutine entry addresses can be stored in the 64-byte area from 00040h to 0007fh. the callt instruction references this table, and branches to a base area address written in the table as a subroutine. as the callt instruction is one byte in length, use of the callt instruction for subroutine calls written frequently throughout th e program enables the program object size to be reduced. the table can contain up to 32 subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency. if this area is not used as the callt instruction table, it can be used as ordinary program memory or data memory. 3.3.3 callf instruction entry area a subroutine call can be made directly to the area from 00800h to 00fffh with the 2-byte call instruction (callf). as the callf instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of the dire ct subroutine call call instruction (3 or 4 bytes). writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device. if you wish to reduce the object size, writing an unconditional branch (br) instruction in this area and locating the subroutin e itself outside this area will result in a reduced object size for subroutines that are called from five or more points. in thi s case, only the 4 bytes of the br instruction are occupied in the callf entry area, enabling the object size to be reduced in a large number of subroutines. 77 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.4 internal data area the internal data area consists of the internal ram area and special function register area (see figures 3-1, 3-2, and 3-3 ). the final address of the internal data area can be specified by means of the location instruction as either 0ffffh (when a location 0 instruction is executed) or fffffh (when a location 0fh instruction is executed). selection of the addresses of the internal data area by means of the location instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. the program after reset release must be as shown in the example below. if the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the othe r area cannot be accessed. example rstvct cseg at 0 dw rststrt to initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn caution when the location 0 instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. it is also necessary to make sure that the entry addresses of the service routines for non-maskable interrupts such as nmi do not overlap the internal data area. also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced. 78 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.4.1 internal ram area the m pd784938 incorporates general-purpose static ram. this area is configured as follows: peripheral ram (pram) internal ram area internal high-speed ram (iram) table 3-2. internal ram area internal ram internal ram area part number peripheral ram: pram internal high-speed ram: iram m pd784935 5,120 bytes 4,608 bytes 512 bytes (0eb00h to 0feffh) (0eb00h to 0fcffh) (0fd00h to 0feffh) m pd784936 6,656 bytes 6,144 bytes (0e500h to 0feffh) (0e500h to 0fcffh) m pd784937 8,192 bytes 7,680 bytes (0df00h to 0feffh) (0df00h to 0fcffh) m pd784938 10,240 bytes 9,728 bytes m pd78f4938 (0d600h to 0feffh) (0d600h to 0fcffh) remark the addresses in the table are the values that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. 79 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 the internal ram memory map is shown in figure 3-5. figure 3-5. internal ram memory map note m pd784935: 00eb00h m pd784936: 00e500h m pd784937: 00df00h m pd784938, 78f4938: 00d600h remark the addresses in the figure are the values that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. 00feffh 00fe80h 00fe39h 00fe06h 00fe00h 00fdffh peripheral ram internal high-speed ram macro service control word area general-purpose register area short direct addressing 1 permissible range short direct addressing 2 permissible range 00fd20h 00fd1fh 00fd00h 00fcffh differs depending on product note 80 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 (1) internal high-speed ram (iram) the internal high-speed ram (iram) allows high-speed accesses to be made. the short direct addressing mode for high- speed accesses can be used on fd20h to feffh in this area. there are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address. the function is the same in both of these addressing modes. with some instructions, the word length is shorter with short direct addressing 2 than with short direct addressing 1. see the 78k/iv series users manual instructions for details. a program fetch cannot be performed from iram. if a program fetch is performed from an address onto which iram is mapped, cpu inadvertent loop will result. the following areas are reserved in iram. ? general-purpose register area: fe80h to feffh ? macro service control word area: fe06h to fe39h (excluding 0fe22h, 0fe23h, 0fe2ah, 0fe2bh, 0fe30h, 0fe31h) ? macro service channel area: fe00h to feffh (the address is specified by the macro service control word) if the reserved function is not used in these areas, they can be used as ordinary data memory. remark the addresses in this text are those that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. (2) peripheral ram (pram) the peripheral ram (pram) is used as ordinary program memory or data memory. when used as program memory, the program must be written to the peripheral ram beforehand by a program. program fetches from peripheral ram are fast, with a 2-byte fetch being executed in 2 clocks. 81 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.4.2 special function register (sfr) area the on-chip peripheral hardware special function registers (sfrs) are mapped onto the area from 0ff00h to 0ffffh (see figures 3-1, 3-2, 3-3, and 3-4 ). the area from 0ffd0h to 0ffdfh is mapped as an external sfr area, and allows externally connected peripheral i/os, etc., to be accessed in external memory expansion mode (specified by the memory expansion mode register (mm)) by the rom- less product or on-chip rom products. caution addresses onto which sfrs are not mapped should not be accessed in this area. if such an address is accessed by mistake, the cpu may become deadlocked. a deadlock can only be released by reset input. remark the addresses in this text are those that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown in the text. 3.4.3 external sfr area in m pd784938 subseries products, the 16-byte area from 0ffd0h to 0ffdfh in the sfr area (when the location 0 is executed; 0fffd0h to 0fffdfh when the location 0fh instruction is executed) is mapped as an external sfr area. when the external memory expansion mode is set in a rom-less product or on-chip rom product, externally connected peripheral i/os, etc., can be accessed using the address bus or address/data bus, etc. as the external sfr area can be accessed by sfr addressing, peripheral i/o and similar operations can be performed easily, the object size can be reduced, and macro service can be used. bus operations for accesses to the external sfr area are performed in the same way as for ordinary memory accesses. 3.5 external memory space the external memory space is a memory space that can be accessed in accordance with the setting of the memory expansion mode register (mm). it can store programs, table data, etc., and can have peripheral i/o devices allocated to it. 82 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.6 m pd78f4938 memory mapping the memory size switching register (ims) specifies the internal memory size. with the m pd78f4938, users are able to select the internal memory capacity using the ims so that the same memory map as that of mask rom versions with a different internal memory capacity can be achieved. the ims is set with an 8-bit memory manipulation instruction. reset input sets ims to ffh. figure 3-6. internal memory size switching register (ims) caution the ims is not contained in mask rom products ( m pd784935, 784936, 784937, 784938). the ims setting to obtain the same memory map as mask rom products are shown in table 3-3. table 3-3. internal memory size switching register (ims) setting value mask rom product ims setting value m pd784935 ddh m pd784936 eeh m pd784937 ffh m pd784938 cch 7 1 address: 0fffcch after reset: ffh w/r 6 1 5 rom1 4 rom0 3 1 2 1 1 ram1 0 ram0 ims internal rom capacity selection rom1 rom0 internal ram capacity selection ram1 ram0 0 0 1 1 0 1 0 1 10,240 bytes 5,120 bytes 6,656 bytes 8,192 bytes 0 0 1 1 0 1 0 1 256 kbytes 96 kbytes 128 kbytes 192 kbytes 83 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.7 control registers control registers consist of the program counter (pc), program status word (psw), and stack pointer (sp). 3.7.1 program counter (pc) this is a 20-bit binary counter that holds address information on the next program to be executed (see figure 3-7 ). normally, the pc is incremented automatically by the number of bytes in the fetched instruction. when an instruction associated with a branch is executed, the immediate data or register contents are set in the pc. upon reset input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits of the pc. figure 3-7. program counter (pc) format 19 pc 0 3.7.2 program status word (psw) the program status word (psw) is a 16-bit register comprising various flags that are set or reset according to the result of instruction execution. read accesses and write accesses are performed in high-order 8-bit (pswh) and low-order 8-bit (pswl) units. individual flags can be manipulated by bit-manipulation instructions. the contents of the psw are automatically saved to the stack when a vectored interrupt request is acknowledged or a brk instruction is executed, and automatically restored when an reti or retb instruction is executed. when context switching is used, the contents are automatically saved in rp3, and automatically restored when an retcs or retcsb instruction is executed. reset input resets (to 0) all bits. 0 must always be written to the bits written as 0 in figure 3-8 . the contents of bits written as - are undefined when read. figure 3-8. program status word (psw) format 7 uf pswh symbol 6 rbs2 5 rbs1 4 rbs0 3 C 2 C 1 C 0 C 7 s pswl 6 z 5 rss 4 ac 3 ie 2 p/v 1 0 0 cy the flags are described below. (1) carry flag (cy) the carry flag records a carry or borrow resulting from an operation. this flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit accumulator when a bit-manipulation instruction is executed. the status of the cy flag can be tested with a conditional branch instruction. 84 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 (2) parity/overflow flag (p/v) the p/v flag performs the following two kinds of operation associated with execution of an operation instruction. the status of the p/v flag can be tested with a conditional branch instruction. ? parity flag operation set (to 1) when the number of bits set (to 1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a chkl or chkla instruction is even, and reset (to 0) if odd. when a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. ? overflow flag operation set (1) only when the numeric range expressed as a twos complement is exceeded as the result of execution of a arithmetic operation instruction, and reset (to 0) otherwise. more specifically, the value of this flag is the exclusive or of the carry into the msb and the carry out of the msb. for example, the twos complement range in an 8-bit arithmetic operation is 80h (C128) to 7fh (+127), and the flag is set (to 1) if the operation result is outside this range, and reset (to 0) if within this range. example the operation of the overflow flag when an 8-bit addition instruction is executed is shown below. when the addition of 78h (+120) and 69h (+105) is performed, the operation result is e1h (+225), and the twos complement limit is exceeded, with the result that the p/v flag is set (to 1). expressed as a twos complement, e1h is -31. 78h (+120) = 0111 1000 +) 69h (+105) = +) 0110 1001 0 1110 0001 = C31 p/v = 1 - cy when the following two negative numbers are added together, the operation result is within the twos complement range, and therefore the p/v flag is reset (to 0). fbh (C5) = 1111 1011 +) f0h (C16) = +) 1111 0000 1 1110 1011 = C21 p/v = 0 - cy (3) interrupt request enable flag (ie) this flag controls cpu interrupt request acknowledgment operations. when 0, interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be acknowledged. all other interrupts are disabled. when 1, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. the ie flag is set (to 1) by execution of an ei instruction, and reset (to 0) by execution of a di instruction or acknowledgmen t of an interrupt. 85 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 (4) auxiliary carry flag (ac) the ac flag is set (to 1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset (t o 0) otherwise. this flag is used when the adjba or adjbs instruction is executed. (5) register set selection flag (rss) the rss flag specifies the general-purpose registers that function as x, a, c, and b, and the general-purpose register pairs (16-bit) that function as ax and bc. this flag is provided to maintain compatibility with the 78k/iii series, and must be set to 0 except when using a 78k/iii serie s program. (6) zero flag (z) the z flag records the fact that the result of an operation is 0. it is set (to 1) when the result of an operation is 0, and reset (to 0) otherwise. the status of the z flag can be tested wi th a conditional branch instruction. (7) sign flag (s) the s flag records the fact that the msb is 1 as the result of an operation. it is set (to 1) when the msb is 1 as the result of an operation, and reset (to 0) otherwise. the status of the s flag can b e tested with a conditional branch instruction. (8) register bank selection flag (rbs0 to rbs2) this is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (see table 3-4 ). it stores 3-bit information which indicates the register bank selected by execution of a sel rbn instruction, etc. table 3-4. register bank selection rbs2 rbs1 rbs0 specified register bank 0 0 0 register bank 0 0 0 1 register bank 1 0 1 0 register bank 2 0 1 1 register bank 3 1 0 0 register bank 4 1 0 1 register bank 5 1 1 0 register bank 6 1 1 1 register bank 7 (9) user flag (uf) this flag can be set and reset in the user program, and used for program control. 86 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.7.3 use of rss bit basically, the rss bit should be fixed at 0 at all times. the following explanation refers to the case where a 78k/iii series program is used, and the program used sets the rss bit to 1. this explanation can be skipped if the rss bit is fixed at 0. the rss bit is provided to allow the functions of a (r1), x (r0), b (r3), c (r2), ax (rp0), and bc (rp1) to be used by register s r4 to r7 (rp2, rp3) as well. effective use of this bit enables efficient programs to be written in terms of program size and program execution. however, careless use can result in unforeseen problems. therefore, the rss bit should always be set to 0. the rss bit should only be set to 1 when a 78k/iii series program is used. use of the rss bit set to 0 in all programs will improve programming and debugging efficiency. even when using a program in which the rss bit set to 1 is used, it is recommended that the program be amended if possible so that it does not set the rss bit to 1. (1) rss bit specification ? registers used by instructions for which the a, x, b, c, and ax registers are directly entered in the operand column of the operation list (see 28.2 ) ? registers specified as implied by instructions that use the a, ax, b, and c registers by means of implied addressing ? registers used in addressing by instructions that use the a, b, and c registers in indexed addressing and based indexed addressing the registers used in these cases are switched as follows according to the rss bit. ? when rss = 0 a ? r1, x ? r0, b ? r3, c ? r2, ax ? rp0, bc ? rp1 ? when rss = 1 a ? r5, x ? r4, b ? r7, c ? r6, ax ? rp2, bc ? rp3 registers used other than those mentioned above are always the same irrespective of the value of the rss bit. with the nec assembler (ra78k4), the register operation code generated when the a, x, b, c, ax, and bc registers are described by those names is determined by the assembler rss pseudo-instruction. when the rss bit is set or reset, an rss pseudo-instruction must be written immediately before (or immediately after) the relevant instruction (see example below). 87 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 (2) operation code generation method with ra78k4 ? with ra78k4, if there is an instruction with the same function as an instruction for which a or ax is directly entered in the operand column of the instruction operation list, the operation code for which a or ax is directly entered in the operand column is generated first. example the function is the same when b is used as r in a mov a,r instruction, and when a is used as r and b is used as r in a movr,r instruction, and the same description (mov,a,b) is used in the assembler source program. in this case, ra78k4 generates code equivalent to the mov a, r instruction. ? if a, x, b, c, ax, or bc is written in an instruction for which r, r, rp, and rp are specified in the operand column, the a, x, b, c, ax, and bc instructions generate an operation code that specifies the following registers according to the operand of the ra78k4 rss pseudo-instruction. register rss = 0 rss = 1 ar1r5 xr0r4 br3r7 cr2r6 ax rp0 rp2 bc rp1 rp3 ? if r0 to r7 or rp0 to rp4 is written as r, r, rp, or rp in the operand column, an operation code in accordance with that specification is output (an operation code for which a or ax is directly entered in the operand column is not output.) ? descriptions r1, r3, r2 or r5, r7, r6 cannot be used for registers a, b, and c used in indexed addressing and based indexed addressing. (3) operating precautions switching the rss bit has the same effect as having two register sets. however, when writing a program, care must be taken to ensure that the static program description and dynamic rss bit changes at the time of program execution always coincide. also, a program that sets rss to 1 cannot be used by a program that uses the context switching function, and therefore program usability is poor. moreover, since different registers are used with the same name, program readability is poor and debugging is difficult. therefore, if it is necessary to set rss to 1, these disadvantages must be fully taken into considerat ion when writing a program. a register not specified by the rss bit can be accessed by writing its absolute name. 88 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.7.4 stack pointer (sp) the stack pointer is a 24-bit register that holds the start address of the stack area (lifo type: 00000h to ffffffh) (see figure 3-9 ). it is used to address the stack area when subroutine processing or interrupt servicing is performed. be sure to write 0 in the high-order 4 bits. the contents of the sp are decremented before a write to the stack area and incremented after a read from the stack area (see figures 3-10 and 3-11 ). the sp is accessed by dedicated instructions. the sp contents are undefined after reset input, and therefore the sp must always be initialized by an initialization program directly after reset release (before a subroutine call or interrupt acknowledgment). example sp initialization movg sp, #0fee0h;sp ? 0fee0h (when used from fedfh) figure 3-9. stack pointer (sp) format 23 sp 0 89 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-10. data saved to stack area push sfr instruction stack push sfrp instruction stack upper byte lower byte upper byte undefined undefined pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle byte lower byte push rg instruction stack push psw instruction stack call, callf, callt instruction stack vectored interrupt stack push post, pushu post instruction (in case of push ax, rp2, rp3) stack sp spe 1 sp ? spe 1 sp spe 1 spe 2 sp ? spe 2 sp spe 1 spe 2 sp ? spe 2 sp spe 1 spe 2 spe 3 sp ? spe 3 sp spe 1 spe 2 spe 3 sp ? spe 3 sp spe 1 spe 2 spe 3 spe 4 sp ? spe 4 sp spe 1 spe 2 spe 3 spe 4 spe 5 spe 6 sp ? spe 6 y t y t y t 90 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-11. data restored from stack area note this 4-bit data is ignored. pop sfr instruction stack pop sfrp instruction stack upper byte lower byte upper byte C note pc15 to pc8 pc7 to pc0 pc15 to pc8 pc7 to pc0 pc19 to pc16 pc19 to pc16 pswh 7 to pswh 4 pswh 7 to pswh 4 pswl pswl r7 r6 r5 r4 rp3 rp2 ax a x middle byte lower byte pop rg instruction stack pop psw instruction stack ret instruction stack reti, retb instruction stack pop post, popu post instruction (in case of pop ax, rp2, rp3) stack sp ? sp+1 sp+1 - sp sp ? sp+2 - sp+1 - sp sp ? sp+3 sp+2 - sp+1 - sp sp ? sp+3 sp+2 - sp+1 - sp sp ? sp+4 sp+3 - sp+2 - sp+1 - sp sp ? sp+6 sp+5 - sp+4 - sp+3 - sp+2 - sp+1 - sp sp ? sp+2 sp+1 - sp y t y t y t e note 91 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 cautions 1. with stack addressing, the entire 1-mbyte space can be accessed but a stack area cannot be reserved in the sfr area or internal rom area. 2. the stack pointer (sp) is undefined after reset input. moreover, non-maskable interrupts can still be acknowledged when the sp is in an undefined state. an unanticipated operation may therefore be performed if a non-maskable interrupt request is generated when the sp is in the undefined state directly after reset release. to avoid this risk, the program after reset release must be written as follows. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn 92 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.8 general- purpose registers 3.8.1 configuration there are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. in addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register for address extension, and used as 24-bit address specification registers. general-purpose registers other than the v, u, t, and w registers for address extension are mapped onto internal ram. these register sets are provided in 8 banks, and can be switched by means of software or the context switching function. upon reset input, register bank 0 is selected. the register bank used during program execution can be checked by reading the register bank selection flag (rbs0, rbs1, rbs2) in the psw. figure 3-12. general-purpose register format 7070 a (r1) x (r0) ax (rp0) b (r3) c (r2) bc (rp1) r5 r4 rp2 r7 r6 rp3 r9 r8 vp (rp4) v vvp (rg4) r11 r10 up (rp5) u uup (rg5) d (r13) e (r12) de (rp6) t tde (rg6) h (r15) l (r14) hl (rp7) w whl (rg7) 0 23 15 8 banks remark absolute names are shown in parentheses. 93 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 figure 3-13. general-purpose register addresses rbnk0 feffh note fe80h note rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk6 rbnk7 h (r15) (fh) 8-bit processing 16-bit processing d (r13) (dh) r11 (bh) r9 (9h) r7 (7h) r5 (5h) b (r3) (3h) a (r1) (1h) 77 0 0 15 0 l (r14) (eh) e (r12) (ch) r10 (ah) r8 (8h) r6 (6h) r4 (4h) c (r2) (2h) x (r0) (0h) hl (rp7) (eh) de (rp6) (ch) up (rp5) (ah) vp (rp4) (8h) rp3 (6h) rp2 (4h) bc (rp1) (2h) ax (rp0) (0h) note when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the address values shown above. caution r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers respectively by setting the rss bit of the psw to 1, but this function should only be used when using a 78k/iii series program. remark when the register bank is changed, and it is necessary to return to the original register bank, an sel rbn instruction should be executed after saving the psw to the stack with a push psw instruction. when returning to the original register bank, if the stack location does not change the pop psw instruction should be used. when the register bank is changed by a vectored interrupt service program, etc., the psw is automatically saved to the stack when an interrupt is acknowledged and restored by an reti or retb instruction, so that, if only one register bank is used in the interrupt service routine, only an sel rbn instruction needs be executed, and execution of a push psw and pop psw instruction is not necessary. example when register bank 2 is specified push psw sel rb2 operations in register bank 2 pop psw operations in original register bank ? ? y ? ? t ...... ...... ...... 94 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.8.2 functions in addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairi ng two 8-bit registers. also, four of the 16-bit registers can be combined with an 8-bit register for address extension and manip ulated in 24-bit units. each register can be used in a general-purpose way for temporary storage of an operation result and as the operand of an inter-register operation instruction. the area from 0fe80h to 0feffh (when the location 0 instruction is executed; 0ffe80h to 0ffeffh when the location 0fh instruction is executed) can be given an address specification and accessed as ordinary data memory irrespective of whether or not it is used as the general-purpose register area. as 8 register banks are provided in the 78k/iv series, efficient programs can be written by using different register banks for normal processing and processing in the event of an interrupt. the registers have the following specific functions. a (r1): ? register mainly used for 8-bit data transfers and operation processing. can be used in combination with all addressing modes for 8-bit data. ? can also be used for bit data storage. ? can be used as the register that stores the offset value in indexed addressing and based indexed addressing. x (r0): ? can be used for bit data storage. ax (rp0): ? register mainly used for 16-bit data transfers and operation processing. can be used in combination with all addressing modes for 16-bit data. axde: ? used for 32-bit data storage when a divux, macw, or macsw instruction is executed. b (r3): ? has a loop counter function, and can be used by the dbnz instruction. ? can be used as the register that stores the offset value in indexed addressing and based indexed addressing. ? used as the macw and macsw instruction data pointer. c (r2): ? has a loop counter function, and can be used by the dbnz instruction. ? can be used as the register that stores the offset value in based indexed addressing. ? used as the counter in a string instruction and the sacw instruction. ? used as the macw and macsw instruction data pointer. rp2: ? used to save the low-order 16 bits of the program counter (pc) when context switching is used. rp3: ? used to save the high-order 4 bits of the program counter (pc) and the program status word (psw) (excluding bits 0 to 3 of pswh) when context switching is used. 95 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 vvp (rg4): ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. uup (rg5): ? has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the pushu and popu instructions. ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. de (rp6), hl (rp7): ? operate as the registers that store the offset value in indexed addressing and based indexed addressing. tde (rg6): ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. ? used as the pointer in a string instruction and the sacw instruction. whl (rg7): ? register used mainly for 24-bit data transfers and operation processing. ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. ? used as the pointer in a string instruction and the sacw instruction. 96 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 in addition to the function name that emphasizes the specific function of the register (x, a, c, b, e, d, l, h, ax, bc, vp, up, de, hl, vvp, uup, tde, whl), each register can also be described by its absolute name (r0 to r15, rp0 to rp7, rg4 to rg7). the correspondence between these names is shown in table 3-5. table 3-5. correspondence between function names and absolute names note rss should only be set to 1 when a 78k/iii series program is used. remark r8 to r11 have no function name. (b) 16-bit registers absolute name function name rss = 0 rss = 1 note rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp rp5 up up rp6 de de rp7 hl hl (c) 24-bit registers absolute name function name rg4 vvp rg5 uup rg6 tde rg7 whl (a) 8-bit registers absolute name function name rss = 0 rss = 1 note r0 x r1 a r2 c r3 b r4 x r5 a r6 c r7 b r8 r9 r10 r11 r12 e e r13 d d r14 l l r15 h h 97 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.9 special function registers (sfr) these are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control registers, etc. they are mapped onto the 256-byte space from 0ff00h to 0ffffh note . note when the location 0 instruction is executed. when the location 0fh instruction is executed, the area is fff00h to fffffh. caution addresses onto which sfrs are not assigned should not be accessed in this area. if such an address is as accessed by mistake, the m pd784938 may become deadlocked. a deadlock can only be released by reset input. a list of special function registers (sfrs) is given in table 3-6. the meaning of the items in the table is as explained below . ? symbol ............................... symbol that indicates the incorporated sfr. this is a reserved word in the nec assembler (ra78k4). with the c compiler (cc78k4), this symbol can be used as an sfr variable by means of a #pragma sfr command. ? r/w .................................... indicates whether the corresponding sfr is read/write enabled. r/w: read/write enabled r: read-only w: write-only ? manipulable bit units ......... indicates the applicable manipulation bit units when the corresponding sfr is manipulated. a 16-bit-manipulable sfr can be written in the operand sfrp, and when specified by an address, an even address is specified. a bit-manipulable sfr can be written in a bit manipulation instruction. ? after reset ......................... indicates the status of the register after reset input. 98 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 table 3-6. list of special function registers (sfrs) (1/5) address note special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w ?? undefined 0ff01h port 1 p1 ?? 0ff02h port 2 p2 r ?? 0ff03h port 3 p3 r/w ?? 0ff04h port 4 p4 ?? 0ff05h port 5 p5 ?? 0ff06h port 6 p6 ?? 00h 0ff07h port 7 p7 ?? undefined 0ff09h port 9 p9 ?? 0ff0ah port 10 p10 ?? 0ff0eh port 0 buffer register p0l ?? 0ff0fh port 0 buffer register h p0h ?? 0ff10h compare register (timer/event counter 0) cr00 ? 0ff12h capture/compare register (timer/event counter 0) cr01 ? 0ff14h compare register l (timer/event counter 1) cr10 cr10w ?? 0ff15h compare register h (timer/event counter 1) 0ff16h capture/compare register l (timer/event counter 1) cr11 cr11w ?? 0ff17h capture/compare register h (timer/event counter 1) 0ff18h compare register l (timer/event counter 2) cr20 cr20w ?? 0ff19h compare register h (timer/event counter 2) 0ff1ah capture/compare register l (timer/event counter 2) cr21 cr21w ?? 0ff1bh capture/compare register h (timer/event counter 2) 0ff1ch compare register l (timer 3) cr30 cr30w ?? 0ff1dh compare register h (timer 3) 0ff20h port 0 mode register pm0 ?? ffh 0ff21h port 1 mode register pm1 ?? 0ff23h port 3 mode register pm3 ?? 0ff24h port 4 mode register pm4 ?? 0ff25h port 5 mode register pm5 ?? 0ff26h port 6 mode register pm6 ?? 0ff27h port 7 mode register pm7 ?? 0ff29h port 9 mode register pm9 ?? 0ff2ah port 10 mode register pm10 ?? 0ff2eh real-time output port control register rtpc ?? 00h 0ff30h capture/compare control register 0 crc0 ? 10h note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 99 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 table 3-6. list of special function registers (sfrs) (2/5) address note special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff31h timer output control register toc r/w ?? 00h 0ff32h capture/compare control register 1 crc1 ? 0ff33h capture/compare control register 2 crc2 ? 10h 0ff36h capture register (timer/event counter 0) cr02 r ? 0000h 0ff38h capture register l (timer/event counter 1) cr12 cr12w ?? 0ff39h capture register h (timer/event counter 1) 0ff3ah capture register l (timer/event counter 2) cr22 cr22w ?? 0ff3bh capture register h (timer/event counter 2) 0ff41h port 1 mode control register pmc1 r/w ?? 00h 0ff43h port 3 mode control register pmc3 ?? 0ff4ah port 10 mode control register pmc10 ?? 0ff4eh pull-up resistor option register l puol ?? 0ff4fh pull-up resistor option register h puoh ?? 0ff50h timer counter 0 tm0 r ? 0000h 0ff51h 0ff52h timer counter 1 tm1 tm1w ?? 0ff53h 0ff54h timer counter 2 tm2 tm2w ?? 0ff55h 0ff56h timer counter 3 tm3 tm3w ?? 0ff57h 0ff5ch prescaler mode register 0 prm0 r/w ? 11h 0ff5dh timer control register 0 tmc0 ?? 00h 0ff5eh prescaler mode register 1 prm1w ? 11h 0ff5fh timer control register 1 tmc1 ?? 00h 0ff68h a/d converter mode register adm ?? 0ff6ah a/d conversion result register adcr r ? undefined 0ff6ch a/d current cut select register iead r/w ?? 00h 0ff6fh watch timer mode register wm ?? 0ff70h pwm control register pwmc ?? 05h 0ff71h pwm prescaler register pwpr ? 00h 0ff72h pwm modulo register 0 pwm0 ? undefined 0ff74h pwm modulo register 1 pwm1 ? 0ff78h rom correction control register corc ?? 00h 0ff79h rom correction address register h corah ? 0ff7ah rom correction address register l coral ? 0000h note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 100 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 table 3-6. list of special function registers (sfrs) (3/5) address note special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ff7dh one-shot pulse output control register ospc r/w ?? 00h 0ff80h clocked serial interface mode register 3 csim3 ?? 0ff82h clocked serial interface mode register csim ?? 0ff84h clocked serial interface mode register 1 csim1 ?? 0ff85h clocked serial interface mode register 2 csim2 ?? 0ff86h serial shift register sio ? undefined 0ff88h asynchronous serial interface mode register asim ?? 00h 0ff89h asynchronous serial interface mode register 2 asim2 ?? 0ff8ah asynchronous serial interface status register asis r ?? 0ff8bh asynchronous serial interface status register 2 asis2 ?? 0ff8ch serial receive buffer: uart0 rxb ? undefined serial transmit shift register: uart0 txs w ? serial shift register: ioe1 sio1 r/w ? 0ff8dh serial receive buffer: uart2 rxb2 r ? serial transmit shift register: uart2 txs2 w ? serial shift register: ioe2 sio2 r/w ? 0ff8eh serial shift register: ioe3 sio3 ? 0ff90h baud rate generator control register brgc ? 00h 0ff91h baud rate generator control register 2 brgc2 ? 0ffa0h external interrupt mode register 0 intm0 ?? 0ffa1h external interrupt mode register 1 intm1 ?? 0ffa4h sampling clock selection register scs0 ? 0ffa8h in-service priority register ispr r ?? 0ffaah interrupt mode control register imc r/w ?? 80h 0ffach interrupt mask register 0l mk0l mk0 ?? ? ffffh 0ffadh interrupt mask register 0h mk0h ?? 0ffaeh interrupt mask register 1l mk1l mk1 ?? ? 0ffafh interrupt mask register 1h mk1h ?? 0ffb0h bus control register bcr ?? 00h 0ffb2h unit address register uar ? 0000h 0ffb4h slave address register sar ? 0ffb6h partner address register par r ? 0ffb8h control data register cdr r/w ? 01h 0ffb9h telegraph length register dlr ? 0ffbah data register dr ? 00h 0ffbbh unit status register usr r ?? 0ffbch interrupt status register isr r/w ?? note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 101 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 table 3-6. list of special function registers (sfrs) (4/5) address note 1 special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0ffbdh slave status register ssr r ?? 41h 0ffbeh success count register scr ? 01h 0ffbfh communication count register ccr ? 20h 0ffc0h standby control register stbc r/w ? note 2 30h 0ffc2h watchdog timer mode register wdm ? note 2 00h 0ffc4h memory expansion mode register mm ?? 20h 0ffc5h hold mode register hldm ?? 00h 0ffc6h clock output mode register clom ?? 0ffc7h programmable wait control register 1 pwc1 ? aah 0ffc8h programmable wait control register 2 pwc2 ? aaaah 0ffcch refresh mode register rfm ?? 00h 0ffcdh refresh area specification register rfa ?? 0ffcfh oscillation stabilization time specification register osts ? 0ffd0h to external sfr area ?? 0ffdfh 0ffe0h interrupt control register (intp0) pic0 ?? 43h 0ffe1h interrupt control register (intp1) pic1 ?? 0ffe2h interrupt control register (intp2) pic2 ?? 0ffe3h interrupt control register (intp3) pic3 ?? 0ffe4h interrupt control register (intc00) cic00 ?? 0ffe5h interrupt control register (intc01) cic01 ?? 0ffe6h interrupt control register (intc10) cic10 ?? 0ffe7h interrupt control register (intc11) cic11 ?? 0ffe8h interrupt control register (intc20) cic20 ?? 0ffe9h interrupt control register (intc21) cic21 ?? 0ffeah interrupt control register (intc30) cic30 ?? 0ffebh interrupt control register (intp4) pic4 ?? 0ffech interrupt control register (intp5) pic5 ?? 0ffedh interrupt control register (intad) adic ?? 0ffeeh interrupt control register (intser) seric ?? 0ffefh interrupt control register (intsr) sric ?? interrupt control register (intcsi1) csiic1 ?? 0fff0h interrupt control register (intst) stic ?? 0fff1h interrupt control register (intcsi) csiic ?? 0fff2h interrupt control register (intser2) seric2 ?? notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 2. the write operation is possible by using the dedicated instruction mov stbc, #byte or mov wdm, #byte only. instructions other than these cannot perform the write operation. 102 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 table 3-6. list of special function registers (sfrs) (5/5) address note 1 special function register (sfr) name symbol r/w manipulable bit units after reset 1 bit 8 bits 16 bits 0fff3h interrupt control register (intsr2) sric2 r/w ?? 43h interrupt control register (intcsi2) csiic2 ?? 0fff4h interrupt control register (intst2) stic2 ?? 0fff6h interrupt control register (intie1) ieic1 ?? 0fff7h interrupt control register (intie2) ieic2 ?? 0fff8h interrupt control register (intw) wic ?? 0fff9h interrupt control register (intcsi3) csiic3 ?? 0fffch internal memory size switching register note 2 ims ? ffh notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the value shown. 2. writes to this register are only meaningful in the case of the m pd78f4938. 103 chapter 3 cpu architecture preliminary users manual u13987ej1v0um00 3.10 cautions (1) program fetches cannot be performed from the internal high-speed ram area (0fd00h to 0feffh when the location 0 instruction is executed; ffd00h to ffeffh when the location 0fh instruction is executed). (2) special function registers (sfrs) addresses onto which sfrs are not assigned should not be accessed in the area 0ff00h to 0ffffh note . if such an address is accessed by mistake, the m pd784938 may become deadlocked. a deadlock can only be released by reset input. note when the location 0 instruction is executed; fff00h to fffffh when the location 0fh instruction is executed. (3) stack pointer (sp) operation with stack addressing, the entire 1-mbyte space can be accessed, but a stack area cannot be reserved in the sfr area or internal rom area. (4) stack pointer (sp) initialization the sp is undefined after reset input, while non-maskable interrupts can be acknowledged directly after reset release. therefore, an unforeseen operation may be performed if a non-maskable interrupt request is generated while the sp is in the undefined state directly after reset release. to minimize this risk, the following program should be coded without fail after reset release. rstvct cseg at 0 dw rststrt to initseg cseg base rststrt : location 0h ; or location 0fh movg sp, #stkbgn 104 preliminary users manual u13987ej1v0um00 [memo] 105 preliminary users manual u13987ej1v0um00 chapter 4 clock generator 4.1 configuration and function the clock generator generates and controls the internal clock and internal system clock supplied to the cpu and on-chip hardware. the clock generator block diagram is shown in figure 4-1. figure 4-1. clock generator block diagram remark f xx : crystal/ceramic oscillation frequency or internal clock frequency f clk : internal system clock frequency the clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the x1 and x2 pins. when standby mode (stop) is set, oscillation stops (see chapter 25 standby function ). it is also possible to input an external clock. in this case, the clock signal is input to the x1 pin, and the inverse phase s ignal to the x2 pin. the frequency divider generates an internal system clock by 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output (f xx ) according to the setting of the standby control register (stbc). x1 internal bus f xx selosc ck1 ck0 stp clock oscillator x2 f xx /2 f clk f xx /8 selector frequency divider f xx f xx /4 osts extc osts1 osts0 reset osts2 f xx internal system clock (cpu, watchdog timer, noise elimination circuit, a/d, pwm, interrupts, local bus interface) internal clock (uart/ioe, csi, noise elimination circuit, timer/counters, oscillation stabilization timer) iebus selosc = 1 stbc hlt reset selector 1/2 divider clock supplied to watch timer when the main clock selected (wm6 = 0) 106 chapter 4 clock generator preliminary users manual u13987ej1v0um00 figure 4-2. clock oscillator external circuitry (a) crystal/ceramic oscillation v ss x2 m pd784938 x1 (b) external clock extc bit of osts = 1 extc bit of osts = 0 open x1 x2 pd74hc04, etc. m pd784938 m x1 x2 pd784938 m cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the dotted line. remark differences between crystal resonator and ceramic resonator generally speaking, the oscillation frequency of a crystal resonator is extremely stable. it is therefore ideal for performing high-precision time management (in clocks, frequency meters, etc.). a ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three advantages: a fast oscillation start-up time, small size, and low price. it is therefore suitable for general use (when high-precision time management is not required). in addition, there are products with a built-in capacitor, etc., which enable the number of parts and mounting area to be reduced. 107 chapter 4 clock generator preliminary users manual u13987ej1v0um00 4.2 control registers 4.2.1 standby control register (stbc) stbc is a register used to set the standby mode and select the internal system clock. see chapter 25 standby function for details of the standby modes. to prevent erroneous entry into standby mode due to an inadvertent program loop, the stbc register can only be written to by a dedicated instruction. this instruction is the mov stbc, #byte instruction, and has a special code configuration (4 b ytes). a write is only performed if the 3rd and 4th bytes of the op code are mutual complements. if the 3rd and 4th bytes of the op c ode are not mutual complements, a write is not performed, and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction which is the source of the error. the error source address c an thus be found from the return address saved on the stack area. an endless loop will result if restore from an operand error is simply performed with an retb instruction. because the operand error interrupt occurs only when the program hangs up (only the correct dedicated instruction is generated with the necs assembler ra78k4 when mov stbc, #byte is described), make sure that the operand error interrupt processing program initializes the system. other write instructions (mov stbc, a, and stbc, #byte, set1 stbc.7, etc.) are ignored, and no operation is performed. that is, a write is not performed on the stbc, and an interrupt such as an operand error interrupt is not generated . stbc can be read at any time with a data transfer instruction. reset input sets stbc to 30h. the format of stbc is shown in figure 4-3. 108 chapter 4 clock generator preliminary users manual u13987ej1v0um00 figure 4-3. standby control register (stbc) format selosc 0 ck1 ck0 0 stp hlt 76543210 stbc 0ffc0h address 30h after reset r/w r/w stp 0 0 1 1 operating mode normal mode halt mode stop mode idle mode hlt 0 1 0 1 ck1 0 0 1 1 internal system clock selection f xx (12.58 mhz) f xx /2 (6.29 mhz) f xx /4 (3.15 mhz) f xx /8 (1.57 khz) ck0 0 1 0 1 (f xx = 12.58 mhz) selosc 0 1 oscillation frequency control 6.29 mhz 12.58 mhz cautions 1. overwrite the selosc bit after performing the following settings. stop the iebus (set bit 7 of the bus control register (bcr) to ??. if the watch timer is operated with the main clock selected, stop the watch timer (set bit 3 of the watch timer mode register (wm) to ??. 2. if the above settings are not performed, the iebus and watch timer may perform incorrectly. 109 chapter 4 clock generator preliminary users manual u13987ej1v0um00 4.2.2 oscillation stabilization time specification register (osts) osts is a register used to select the oscillation stabilization time. osts can be written to only by an 8-bit transfer instruction. reset input clears osts to 00h. the format of osts is shown in figure 4-4. figure 4-4. oscillation stabilization time specification register (osts) format 7 0 osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 oscillation stabilization time selection (see figure 25-4 for details) address after reset r/w r/w 00h 0ffcfh caution when using the regulator (refer to chapter 5 regulator), set a value of at least 10.4 ms, taking in consideration the regulator output stabilization time. 110 chapter 4 clock generator preliminary users manual u13987ej1v0um00 4.3 clock generator operation 4.3.1 clock oscillator (1) when using crystal/ceramic oscillation the clock oscillator starts oscillating when the reset signal is input, and stops oscillation when the stop mode is set by the standby control register (stbc). oscillation is resumed when the stop mode is released. (2) when using external clock the clock oscillator supplies the clock input from the x1 pin to the internal circuitry when the reset signal is input. 4.3.2 divider the divider performs 1/1, 1/2, 1/4, or 1/8 scaling of the clock oscillator output, and supplies the resulting clock to the cpu, watchdog timer, noise elimination circuit, clocked serial interface (csi), a/d converter, pwm, interrupt control circuit, and l ocal bus interface. the division ratio is specified by the ck0 and ck1 bits of the standby control register (stbc). controlling the division ratio to match the speed required by the cpu enables the overall power consumption to be reduced. also, the operating speed can be selected to match the supply voltage. when reset is input, the lowest speed (1/8) is selected. if the division ratio of the divider circuit is changed, the maximum time shown in table 4-1 is required to change the division ratio, depending on the clock selected before change. instruction execution continues even while the division ratio is changed, and the clock is supplied with the previous division ratio until the division ratio has been completely changed. table 4-1. time required to change division ratio previous division ratio maximum time required for change none 11/f xx 1/2 12/f xx 1/4 8/f xx 1/8 8/f xx 111 chapter 4 clock generator preliminary users manual u13987ej1v0um00 4.4 cautions the following cautions apply to the clock generator. 4.4.1 when an external clock is input (1) when an external clock is input, this should be performed with a hcmos device, or a device with the equivalent drive capability. (2) a signal should not be extracted from the x1 and x2 pins. if a signal is extracted, it should be extracted from point a in figure 4-5. figure 4-5. signal extraction with external clock input x1 m pd74hc04, etc. m pd784938 x2 a (3) the wiring connecting the x1 pin to the x2 pin via an inverter, in particular, should be made as short as possible. 112 chapter 4 clock generator preliminary users manual u13987ej1v0um00 4.4.2 when crystal/ceramic oscillation is used (1) as the oscillator is a high-frequency analog circuit, considerable care is required. the following points, in particular, require attention. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. if oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably, either. also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is recommended. figure 4-6. cautions on resonator connection v ss x2 x1 m pd784938 cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed by the broken lines. 113 chapter 4 clock generator preliminary users manual u13987ej1v0um00 figure 4-7. incorrect example of resonator connection (a) wiring of connected circuits is too long (b) crossed signal lines pd784938 m x1 x2 v ss pd784938 m x1 pnm x2 v ss (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potentials at points a, b, and c fluctuate) (e) signal extracted pd784938 m x1 x2 v ss pd784938 m x1 x2 v ss high fluctuating current pd784938 m x1 x2 v ss b ac v dd pnm high current 114 chapter 4 clock generator preliminary users manual u13987ej1v0um00 (2) when the device is powered on, and when restoring from the stop mode, sufficient time must be allowed for the oscillation to stabilize. generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is used, and several hundred microseconds when a ceramic resonator is used. an adequate oscillation stabilization period should be secured by the following means: <1> when powered-on: reset input (reset period) <2> when returning from stop mode: (i) reset input (reset period) (ii) time of the oscillation stabilization timer that automatically starts at the valid edge of nmi, intp4, or intp5 signal note (set by the oscillation stabilization time specification register (osts)) note for intp4 and intp5, when masking is released and macro service is disabled. 115 preliminary users manual u13987ej1v0um00 chapter 5 regulator 5.1 outline of regulator the m pd784938 has a regulator that reduces the power consumption of the device (a circuit for low voltage operation). the operation of this regulator is controlled by the input level of the regoff pin. when the regoff pin is made high, the regulator is turned off; when it is made low, the regulator is turned on. when the regulator is turned on, it enables to reduce the power consumption. to stabilize the output voltage of the regulator, connect a capacitor for stabilizing the regulator (approximately 1 m f) to the regc pin. apply the same level as v dd to the regc pin when the regulator is stopped. figure 5-1 shows the block diagram of the peripherals of the regulator. figure 5-1. regulator peripherals block diagram ? processing of regc pin regulator on connects capacitance for regulator stabilization regulator off supplies power supply voltage caution for the oscillation stabilization time when the stop mode is released, set a value of at least 10.4 ms with the oscillation stabilization time specification register (osts), taking in consideration the regulator output oscillation stabilization time. (refer to chapter 25 standby function.) regoff v dd regc 1 f regulator low level: regulator on high level: regulator off internal supply voltage (supplied to cpu and each peripheral circuit) m 116 preliminary users manual u13987ej1v0um00 [memo] 117 preliminary users manual u13987ej1v0um00 chapter 6 port functions 6.1 digital input/output ports the m pd784938 is provided with the ports shown in figure 6-1, enabling various kinds of control to be performed. the function of each port is shown in table 6-1. for ports 0 to 6, port 9, and port 10, use of an on-chip pull-up resistor can be specified by software when used as input ports. figure 6-1. port configuration port 0 port 1 port 3 port 4 port 5 port 6 port 7 8 port 2 p00 p07 p10 p17 p30 p37 p40 p47 p50 p57 p60 p67 p70 p77 p20 to p27 port 9 port 10 p90 p97 p100 p107 chapter 6 port functions 118 preliminary users manual u13987ej1v0um00 table 6-1. port functions port name pin names functions software pull-up specification port 0 p00 to p07 ? input/output can be specified in 1-bit units. input mode pins specified at once ? can also operate as 4-bit real-time output ports (p00 to p03, p04 to p07). ? can drive a transistor. port 1 p10 to p17 ? input/output can be specified in 1-bit units. ? led drive capability. port 2 p20 to p27 ? input port 6-bit unit (p22 to p27) port 3 p30 to p37 ? input/output can be specified in 1-bit units. input mode pins specified at once ? p32/sck0 pin and p33/so0 pin can be set in n-ch open-drain mode. port 4 p40 to p47 ? input/output can be specified in 1-bit units. ? can drive an led. port 5 p50 to p57 ? input/output can be specified in 1-bit units. ? led drive capability. port 6 p60 to p67 ? input/output can be specified in 1-bit units. port 7 p70 to p77 ? input/output can be specified in 1-bit units. port 9 p90 to p97 ? input/output can be specified in 1-bit units. input mode pin specified at once port 10 p100 to p107 ? input/output can be specified in 1-bit units. ? p105/sck3 pin and p107/so3 pin can be set in n-ch open-drain mode. table 6-2. number of input/output ports input/output total input mode output mode ports software pull-up resistor direct led drive direct transistor drive input ports 8 6 input/output ports 72 64 24 0 output ports 0 0 8 total 80 70 24 8 119 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.2 port 0 port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. input/output can be spe cified in 1-bit units by means of the port 0 mode register (pm0). each pin incorporates a software programmable pull-up resistor. p00 to p03 and p04 to p07 can output the buffer register (p0l, p0h) contents at any time interval as 4-bit real-time output ports or one 8-bit real-time output port. the real-time output port control register (rtpc) is used to select whether this por t is used as a normal output port or a real-time output port. when reset is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.2.1 hardware configuration the port 0 hardware configuration is shown in figure 6-2. figure 6-2. port 0 block diagram wr puol pull-up resistor option register l puol0 wr rtpc real-time output port control register p0lm (p0hm) wr pm0 port 0 mode register rd rtpc wr p0l buffer register pm0n (pm0m) rd p0l wr out rd p0 p0ln (p0hm) p0n (p0m) p0n (p0m) n=0,1,2,3 m=4,5,6,7 trigger output latch rd pm0 v dd selector internal bus rd puol chapter 6 port functions 120 preliminary users manual u13987ej1v0um00 6.2.2 i/o mode/control mode setting the port 0 input/output mode is set by means of the port 0 mode register (pm0) as shown in figure 6-3. figure 6-3. port 0 mode register (pm0) format 7 pm07 pm0 6 pm06 5 pm05 4 pm04 3 pm03 2 pm02 1 pm01 0 pm00 address after reset r/w r/w ffh 0ff20h pm0n p0n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 when port 0 is used as a real-time output port, the p0lm and p0hm bits of the real-time output port control register (rtpc) should be set (to 1). when p0lm and p0hm are set, the respective pin output buffer is turned on and the output latch contents are output to the pin irrespective of the contents of pm0. 121 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.2.3 operating status port 0 is an input/output port. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . writes cannot be performed to the output latch of a port specified as a real-time output port. however, the output latch contents can be read even if it is set to the real-time output port mode. note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-4. port specified as output port p0n n = 0 to 7 rd out wr port internal bus output latch chapter 6 port functions 122 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an i nput port cannot be loaded into an accumulator. figure 6-5. port specified as input port output latch p0n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. 123 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.2.4 on-chip pull-up resistors port 0 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by means of the puol0 bit of the pull- up resistor option register l (puol) and the port 0 mode register (pm0). when puol0 is 1, the on-chip pull-up resistors of the pins for which input is specified by pm0 are enabled (pm0n = 1, n = 0 to 7). figure 6-6. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol0 port 0 pull-up resistor specification not used in port 0 used in port 0 1 0 remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 124 preliminary users manual u13987ej1v0um00 figure 6-7. pull-up resistor specification (port 0) p06 input buffer p07 p05 p01 p00 v dd port 0 mode register (pm0) puol0 (puol) internal bus 125 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.2.5 transistor drive in port 0, the output buffer high-level side drive capability has been increased, allowing active-high direct transistor drive. an example of the connection is shown in figure 6-8. figure 6-8. example of transistor drive p0n v dd load chapter 6 port functions 126 preliminary users manual u13987ej1v0um00 6.3 port 1 port 1 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 1 mode register (pm1). each pin incorporates a programmable pull-up resistor. this port has direct led drive capability. in addition to their input/output port function, p10 to p14 also have an alternate function as serial interface pins. the oper ation mode can be specified bit-wise by setting the port 1 mode control register (pmc1), as shown in table 6-3. the level of any pin can be read and tested at any time irrespective of the alternate-function operation. when reset is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 6-3. port 1 operation modes pin name port mode control signal i/o mode operation to operate control pin p10, p11 i/o port p12 asck2 i/o/sck2 i/o setting pmc12 bit of pmc1 to 1 p13 rxd2 input/si2 input setting pmc13 bit of pmc1 to 1 p14 txd2 output/so2 output setting pmc14 bit of pmc1 to 1 p15 to p17 127 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.3.1 hardware configuration the port 1 hardware configuration is shown in figures 6-9 to 6-12. figure 6-9. p12 (port 1) block diagram p12 wr puol v dd rd puol wr pmc1 wr p1 asck2, sck2 input rd pmc1 external sck2 wr pm1 sck2 output puol1 pmc12 p12 pm12 rd pm1 rd p1 pull-up resistor option register l port 1 mode register output latch selector internal bus port 1 mode control register chapter 6 port functions 128 preliminary users manual u13987ej1v0um00 figure 6-10. p13 (port 1) block diagram p13 v dd wr puol wr p1 si2, rxd2 input rd puol wr pm1 wr pmc1 rd pmc1 puol1 pm13 p13 pmc13 rd pm1 rd p1 pull-up resistor option register l port 1 mode register output latch internal bus port 1 mode control register 129 chapter 6 port functions preliminary users manual u13987ej1v0um00 figure 6-11. p14 (port 1) block diagram wr puol rd puol wr pmc1 wr p1 rd pmc1 txd2/so2 output puol1 pmc14 p14 pm14 wr pm1 p14 v dd rd pm1 rd p1 pull-up resistor option register l port 1 mode register output latch internal bus port 1 mode control register selector chapter 6 port functions 130 preliminary users manual u13987ej1v0um00 figure 6-12. block diagram of p10, p11, and p15 to p17 (port 1) p1n n = 0, 1, 5 to 7 wr puol puol1 v dd rd puol wr pm1 pm1n wr p1 p1n rd pm1 rd p1 pull-up resistor option register l port 1 mode register output latch internal bus 131 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.3.2 i/o mode/control mode setting the port 1 input/output mode is set for each pin by means of the port 1 mode register (pm1) as shown in figure 6-13. in addition to their input/output port function, p12 to p14 also have an alternate function as serial interface pins, and the control mode is specified by setting the port 1 mode control register (pmc1) as shown in figure 6-14. figure 6-13. port 1 mode register (pm1) format 7 pm17 pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 address after reset r/w r/w ffh 0ff21h pm1n p1n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 figure 6-14. port 1 mode control register (pmc1) format 7 0 pmc1 6 0 5 0 4 pmc14 3 pmc13 2 pmc12 1 0 0 0 address after reset r/w r/w 00h 0ff41h pmc12 p12 pin control mode specification input/output port mode asck2/sck2 input/output mode 1 0 pmc13 p13 pin control mode specification input/output port mode rxd2/si2 input mode 1 0 pmc14 p14 pin control mode specification input/output port mode txd2/so2 output mode 1 0 chapter 6 port functions 132 preliminary users manual u13987ej1v0um00 6.3.3 operating status port 1 is an input/output port. pins p12 to p14 have an alternate function as serial interface pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-15. port specified as output port internal bus output latch p1n n = 0 to 7 rd out wr port 133 chapter 6 port functions preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction, etc. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the output latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an i nput port cannot be loaded into an accumulator. figure 6-16. port specified as input port output latch p1n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port that has the i/o mode or port mode and control mode, the contents of the output latch of the pin set in the input mode or control mode become undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. chapter 6 port functions 134 preliminary users manual u13987ej1v0um00 (3) when specified as control signal input/output p12 to p14 (by setting (to 1) bits of the port 1 mode control register (pmc1)) can be used as control signal inputs or outputs bit-wise irrespective of the setting of the port 1 mode register (pm1). when a pin is used as a control signal, the control signal status can be seen by executing a port read instruction. figure 6-17. control specification p1n n = 2 to 4 pm1n = 0 pm1n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when the port 1 mode register (pm1) is set (to 1), the control signal pin level can be read by executing a port read instruction. when pm1 is reset (to 0), the m pd784938 internal control signal status can be read by executing a port read instruction. (b) when port is control signal input when the port 1 mode register (pm1) is set (to 1), control signal pin level can be read by executing a port read instruction. 135 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.3.4 on-chip pull-up resistors port 1 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by means of the puol1 bit of the pull- up resistor option register l (puol) and the port 1 mode register (pm1). when puol1 is 1, the on-chip pull-up resistors of the pins for which input is specified by pm1 are enabled (pm1n = 1, n = 0 to 7). also, the specification for use of the pull-up resistor is also valid for pins specified as control signal output pins (pull-u p resistors are also connected to pins that function as control signal output pins). therefore, if you do not want to connect th e pull- up resistors with the control signal output pin, the contents of the corresponding bits of pm1 should be set to 0 (output mode) . figure 6-18. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol1 port 1 pull-up resistor specification not used in port 1 used in port 1 1 0 remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 136 preliminary users manual u13987ej1v0um00 figure 6-19. pull-up resistor specification (port 1) p16 input buffer p17 p15 p11 p10 v dd port 1 mode register (pm1) puol1 (puol) internal bus 6.3.5 direct led drive in port 1, the output buffer low-level side drive capability has been reinforced allowing active-low direct led drive. an exam ple of such use is shown in figure 6-20. figure 6-20. example of direct led drive m pd784938 p1n (n = 0 to 7) v dd 137 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.4 port 2 port 2 is an 8-bit input-only port. p22 to p27 incorporate a software programmable pull-up resistor. as well as operating as input ports, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see table 6-4). al l 8 pins are schmitt-triggered inputs to prevent misoperation due to noise. table 6-4. port 2 operation modes port name function p20 input port/nmi input note p21 input port/intp0 input/cr11 capture trigger input/ timer/event counter 1 count clock/real-time output port trigger signal p22 input port/intp1 input/cr22 capture trigger input p23 input port/intp2 input/ci input p24 input port/intp3 input/cr02 capture trigger input/ timer/event counter 0 count clock p25 input port/intp4 input/asck input/sck1 input/output p26 input port/intp5 input/a/d converter external trigger input p27 input port/si0 input note nmi input is acknowledged regardless of whether interrupts are enabled or disabled. (a) function as port pins the pin level can always be read or tested regardless of the alternate-function operation. (b) functions as control signal input pins (i) nmi (non-maskable interrupt) the external non-maskable interrupt request input pin. rising edge detection or falling edge detection can be specified by setting the external interrupt mode register 0 (intm0). (ii) intp0 to intp5 (interrupt from peripherals) external interrupt request input pins. when the valid edge specified by the external interrupt mode registers 0, 1 (intm0/intm1) is detected an interrupt is generated (see chapter 22 edge detection function ). in addition, pins intp0 to intp3 and intp5 are also used as external trigger input pins with the various functions shown below. ? intp0 ....... timer/event counter 1 capture trigger input pin external count clock input pin real-time output port trigger input pin ? intp1 ....... timer/event counter 2 capture register (cr22) capture trigger input pin ? intp2 ....... timer/event counter 2 external count clock input pin capture/compare register (cr21) capture trigger input pin ? intp3 ....... timer/event counter 0 capture trigger input pin timer/event counter 0 external count clock input pin ? intp5 ....... a/d converter external trigger input pin chapter 6 port functions 138 preliminary users manual u13987ej1v0um00 (iii) ci (clock input) the timer/event counter 2 external clock input pin (iv) asck (asynchronous serial clock) the external baud rate clock input pin (v) sck1 (serial clock 1) the serial clock input/output pin (in 3-wire serial i/o 1 mode) (vi) si0 (serial input 0) the serial data input pin (in 3-wire serial i/o 0 mode) 139 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.4.1 hardware configuration the port 2 hardware configuration is shown in figure 6-21. figure 6-21. block diagram of p20 to p24, p26 and p27 (port 2) internal bus rd p2 rd puol wr puol si0 input various interrupt control signals v dd p27 rd p2 3-wire serial i/o mode 0 p2n n = 0 to 4, 6 puol2 edge detection circuit note pull-up resistor option register l v dd note p20 and p21 do not have the circuitry enclosed by the broken lines. chapter 6 port functions 140 preliminary users manual u13987ej1v0um00 figure 6-22. p25 (port 2) block diagram rd p2 v dd rd puol wr puol puol2 intp4 input sck1 output mode sck1 output asck/sck1 input p25/asck/sck1 internal bus edge detection circuit 141 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.4.2 input mode/control mode setting port 2 is an input-only port, and there is no register for setting the input mode. also, control signal input is always possible, and therefore the signal to be used is determined by the control registers for individual on-chip hardware items. 6.4.3 operating status port 2 is an input-only port, and pin levels can always be read or tested. figure 6-23. port specified as input port internal bus p2n n = 0 to 7 rd in 6.4.4 on-chip pull-up resistors p22 to p27 incorporate pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for all six pins, p22 to p27, together by means of the puol2 bit of the pull-up resistor option register l (puol) (bit-wise specification is not possible). p20 and p21 do not incorporate a pull-up resistor. figure 6-24. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol2 port 2 pull-up resistor specification not used in port 2 used in pins p22 to p27 1 0 remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 142 preliminary users manual u13987ej1v0um00 figure 6-25. pull-up specification (port 2) p23 v dd pull-up resistor option register l (puol) puol2 input buffer internal bus p22 p24 p25 p26 p27 caution as p22 to p26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate function (intp1 to intp5). therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine. 143 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.5 port 3 port 3 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 3 mode register (pm3). each pin incorporates a software programmable pull-up resistor. p32 and p33 can be set in the n-ch open- drain mode. in addition to its function as an input/output port, port 3 also has various alternate-function control signal pin functions. the operation mode can be specified in 1-bit units by setting the port 3 mode control register (pmc3), as shown in table 6-5. the pin level of all pins can always be read or tested regardless of the alternate-function pin operation. when reset is input, port 3 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 6-5. port 3 operation modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc3n = 0 pmc3n = 1 p30 input/output port rxd input/si1 input p31 txd output/so1 output p32 sck0 input/output p33 so0 output p34 to0 output p35 to1 output p36 to2 output p37 to3 output (a) port mode each port specified as port mode by the port 3 mode control register (pmc3) can be specified as input/output bit-wise by setting the port 3 mode register (pm3). (b) control signal input/output mode pins can be set as control pins in 1-bit units by setting the port 3 mode control register (pmc3). (i) rxd (receive data) /si1 (serial input 1) rxd is the asynchronous serial interface serial data input pin. si1 is the serial data input pin (in 3-wire serial i/o 1 mode). (ii) txd (transmit data) /so1 (serial output 1) txd is the asynchronous serial interface serial data output pin. so1 is the serial data output pin (in 3-wire serial i/o 1 mode). (iii) sck0 (serial clock 0) sck0 is the clocked serial interface serial clock input/output pin (in 3-wire serial i/o 0 mode). (iv) so0 (serial output 0) so0 is the serial data output pin (in 3-wire serial i/o 0 mode). (v) to0 to to3 (timer output) timer output pins chapter 6 port functions 144 preliminary users manual u13987ej1v0um00 6.5.1 hardware configuration the port 3 hardware configuration is shown in figures 6-26 to 6-29. figure 6-26. p30 (port 3) block diagram p30 v dd wr puol wr p3 si1, rxd input rd puol wr pm3 wr pmc3 rd pmc3 puol3 pm30 p30 pmc30 rd pm3 rd p3 pull-up resistor option register l port 3 mode register output latch internal bus port 3 mode control register 145 chapter 6 port functions preliminary users manual u13987ej1v0um00 figure 6-27. block diagram of p31 and p34 to p37 (port 3) wr puol rd puol wr pmc3 wr p3 rd pmc3 to, so1, txd output puol3 pmc3n p3n pm3n wr pm3 p3n n = 1, 4, 5, 6, 7 v dd rd pm3 rd p3 pull-up resistor option register l port 3 mode register output latch internal bus port 3 mode control register selector chapter 6 port functions 146 preliminary users manual u13987ej1v0um00 figure 6-28. p32 (port 3) block diagram wr puol rd puol wr pm3 rd pm3 wr pmc3 rd pmc3 rd p3 rd p3 puol3 pm32 pmc32 p32 sck0 output sck0 input v dd v dd p32 pull-up resistor option register l port 3 mode register output latch internal bus port 3 mode control register selector sck0 input n-ch open-drain specification (csim mod bit) 147 chapter 6 port functions preliminary users manual u13987ej1v0um00 figure 6-29. p33 (port 3) block diagram wr puol rd puol wr pm3 rd pm3 wr pmc3 rd pmc3 wr p3 rd p3 puol3 pm33 pmc33 p33 so0 output v dd v dd p33 n-ch open-drain specification (csim mod bit) pull-up resistor option register l port 3 mode register output latch internal bus port 3 mode control register selector chapter 6 port functions 148 preliminary users manual u13987ej1v0um00 6.5.2 i/o mode/control mode setting the port 3 input/output mode is set for each pin by means of the port 3 mode register (pm3) as shown in figure 6-30. in addition to their input/output port function, port 3 pins also have an alternate function as various control signal pins, an d the control mode is specified by setting the port 3 mode control register (pmc3) as shown in figure 6-31. figure 6-30. port 3 mode register (pm3) format 7 pm37 pm3 6 pm36 5 pm35 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 address after reset r/w r/w ffh 0ff23h pm3n p3n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 149 chapter 6 port functions preliminary users manual u13987ej1v0um00 figure 6-31. port 3 mode control register (pmc3) format 7 pmc37 pmc3 6 pmc36 5 pmc35 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address after reset r/w r/w 00h 0ff43h pmc30 p30 pin control mode specification input/output port mode rxd/si1 input mode 1 0 pmc31 p31 pin control mode specification input/output port mode txd/so1 output mode 1 0 pmc32 p32 pin control mode specification input/output port mode sck0 input/output mode 1 0 pmc33 p33 pin control mode specification input/output port mode so0 output mode 1 0 pmc3n p3n pin control mode specification (n = 4 to 7) input/output port mode ton output mode (n = 0 to 3) 1 0 chapter 6 port functions 150 preliminary users manual u13987ej1v0um00 6.5.3 operating status port 3 is an input/output port, with an alternate function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-32. port specified as output port internal bus output latch p3n n = 0 to 7 rd out wr port 151 chapter 6 port functions preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-33. port specified as input port output latch p3n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. chapter 6 port functions 152 preliminary users manual u13987ej1v0um00 (3) when specified as control signal input/output by setting (to 1) bits of the port 3 mode control register (pmc3), port 3 can be used as control signal input or output bit-wis e irrespective of the setting of the port 3 mode register (pm3). when a pin is used as a control signal, the control signal stat us can be seen by executing a port read instruction. figure 6-34. control specification p3n n = 0 to 7 pm3n = 0 pm3n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when the port 3 mode register (pm3) is set (to 1), the control signal pin level can be read by executing a port read instruction. when pm3 is reset (to 0), the m pd784938 internal control signal status can be read by executing a port read instruction. (b) when port is control signal input only the port 3 mode register (pm3) is set (to 1), control signal pin levels can be read by executing a port read instruction. 153 chapter 6 port functions preliminary users manual u13987ej1v0um00 6.5.4 on-chip pull-up resistors port 3 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puol3 bit of the pull- up resistor option register l (puol) and the port 3 mode register (pm3). when puol3 is 1, the on-chip pull-up resistors of the pins for which input is specified by pm3 (pm3n = 1, n = 0 to 7) are enabled. also, the specification for use of the pull-up resistor is also valid for pins specified as control mode pins (pull-up resistor s are also connected to pins that function as output pins in the control mode). therefore, if you do not want to connect the pull-up resistors in the control mode, the contents of the corresponding bits of pm3 should be set to 0 (output mode). figure 6-35. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol3 port 3 pull-up resistor specification not used in port 3 used in port 3 1 0 remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 154 preliminary users manual u13987ej1v0um00 figure 6-36. pull-up specification (port 3) p31 input buffer p30 p32 p36 p37 v dd port 3 mode register (pm3) puol3 (puol) internal bus chapter 6 port functions 155 preliminary users manual u13987ej1v0um00 6.6 port 4 port 4 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 4 mode register (pm4). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. port 4 also functions as the time division address/data bus (ad0 to ad7) by the memory expansion mode register (mm) when external memory or i/os are expanded. when reset is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.6.1 hardware configuration the port 4 hardware configuration is shown in figure 6-37. figure 6-37. port 4 block diagram rd puol wr puol puol4 v dd p4n n = 0 to 7 wr pm4 pm4n wr p4 p4n mm0 to mm3 rd pm4 rd p4 pull-up resistor option register l port 4 mode register output latch internal data bus internal address bus input/ output control circuit chapter 6 port functions 156 preliminary users manual u13987ej1v0um00 6.6.2 i/o mode/control mode setting the port 4 input/output mode is set for each pin by means of the port 4 mode register (pm4) as shown in figure 6-38. when port 4 is used as the address/data bus, it is set by means of the memory expansion mode register (mm: see figure 24-1 ) as shown in table 6-6. figure 6-38. port 4 mode register (pm4) format 7 pm47 pm4 6 pm46 5 pm45 4 pm44 3 pm43 2 pm42 1 pm41 0 pm40 address after reset r/w r/w ffh 0ff24h p4n p4n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 table 6-6. port 4 operation modes mm bits operation mode mm3 mm2 mm1 mm0 0000 port 0011 address/data bus (ad0 to ad7) 0100 0101 0110 0111 1000 1001 chapter 6 port functions 157 preliminary users manual u13987ej1v0um00 6.6.3 operating status port 4 is an input/output port, with an alternate function as the address/data bus (ad0 to ad7). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-39. port specified as output port internal bus output latch p4n n = 0 to 7 rd out wr port chapter 6 port functions 158 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a port specified as input is switched to an output port, the output latch contents are output to the port pin). also, when specified as an input port, the output latch contents cannot be loaded into an accumulator. figure 6-40. port specified as input port output latch p4n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) when used as address/data bus (ad0 to ad7) used automatically when an external access is performed. input/output instructions should not be executed on port 4. chapter 6 port functions 159 preliminary users manual u13987ej1v0um00 6.6.4 on-chip pull-up resistors port 4 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puol4 bit of the pull- up resistor option register l (puol) and the port 4 mode register (pm4). when puol4 is 1, the on-chip pull-up resistors of the pins for which input is specified by the pm4 for port 4 (pm4n = 1, n = 0 to 7) are enabled . figure 6-41. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol4 port 4 pull-up resistor specification not used in port 4 used in port 4 1 0 caution when using the port 4 of the m pd784938 as an address/data bus pin, be sure to clear puol4 to 0 to disconnect the on-chip pull-up resistor. remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 160 preliminary users manual u13987ej1v0um00 figure 6-42. pull-up specification (port 4) p41 input buffer p40 p42 p46 p47 v dd port 4 mode register (pm4) puol4 (puol) internal bus chapter 6 port functions 161 preliminary users manual u13987ej1v0um00 6.6.5 direct led drive in port 4, the output buffer low-level side drive capability has been reinforced, allowing active-low direct led drive. an example of such use is shown in figure 6-43. figure 6-43. example of direct led drive m pd784938 p4n (n = 0 to 7) v dd chapter 6 port functions 162 preliminary users manual u13987ej1v0um00 6.7 port 5 port 5 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 5 mode register (pm5). each pin incorporates a software programmable pull-up resistor. this port has direct led drive capability. in addition, p50 to p57 function as the address bus (a8 to a15) when external memory or i/os are expanded. when reset is input, port 5 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.7.1 hardware configuration the port 5 hardware configuration is shown in figure 6-44. figure 6-44. port 5 block diagram v dd p5n n = 0 to 7 mm0 to mm3 rd puol wr puol puol5 wr pm5 pm5n wr p5 p5n rd pm5 rd p5 pull-up resistor option register l port 5 mode register output latch internal data bus internal address bus input/ output control circuit chapter 6 port functions 163 preliminary users manual u13987ej1v0um00 6.7.2 i/o mode/control mode setting the port 5 input/output mode is set for each pin by setting the port 5 mode register (pm5) as shown in figure 6-45. when port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory expansion mode register (mm: see figure 24-1 ) as shown in table 6-7. figure 6-45. port 5 mode register (pm5) format 7 pm57 pm5 6 pm56 5 pm55 4 pm54 3 pm53 2 pm52 1 pm51 0 pm50 address after reset r/w r/w ffh 0ff25h pm5n p5n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 table 6-7. port 5 operation modes mm bits operation mode mm3 mm2 mm1 mm0 p50 p51 p52 p53 p54 p55 p56 p57 0 0 0 0 port (p50 to p57) 00 1 1 0 1 0 0 a8 a9 port 0 1 0 1 a8 a9 a10 a11 port 0 1 1 0 a8 a9 a10 a11 a12 a13 port 0 1 1 1 a8 a9 a10 a11 a12 a13 a14 a15 10 0 0 10 0 1 chapter 6 port functions 164 preliminary users manual u13987ej1v0um00 6.7.3 operating status port 5 is an input/output port, with an alternate function as the address bus (a8 to a15). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-46. port specified as output port internal bus output latch p5n n = 0 to 7 rd out wr port chapter 6 port functions 165 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-47. port specified as input port output latch p5n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) when used as address bus (a8 to a15) used automatically when an external address is accessed. chapter 6 port functions 166 preliminary users manual u13987ej1v0um00 6.7.4 on-chip pull-up resistors port 5 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puol5 bit of the pull- up resistor option register l (puol) and the port 5 mode register (pm5). when puol5 is 1, the on-chip pull-up resistors of the pins for which input is specified by the pm5 for port 5 (pm5n = 1, n = 0 to 7) are enabled . figure 6-48. pull-up resistor option register l (puol) format 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol5 port 5 pull-up resistor specification not used in port 5 used in port 5 1 0 caution when using the port 5 of the m pd784938 as an address bus, be sure to clear puol5 to 0 to disconnect the on-chip pull-up resistor. remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. chapter 6 port functions 167 preliminary users manual u13987ej1v0um00 figure 6-49. pull-up specification (port 5) p51 input buffer p50 p52 p56 p57 v dd port 5 mode register (pm5) puol5 (puol) internal bus chapter 6 port functions 168 preliminary users manual u13987ej1v0um00 6.7.5 direct led drive in port 5, the output buffer low-level side drive capability has been reinforced, allowing active-low direct led drive. an example of such use is shown in figure 6-50. figure 6-50. example of direct led drive m pd784938 p5n (n = 0 to 7) v dd chapter 6 port functions 169 preliminary users manual u13987ej1v0um00 6.8 port 6 port 6 is an 8-bit input/output port with an output latch. p60 to p67 incorporate a software programmable pull-up resistor. in addition to its function as a port, port 6 also has various alternate-function control signal pin functions as shown in tabl e 6-8. operations as control pins are performed by the respective function operations. when reset is input, p60 to p67 are set as input port pins (output high-impedance state), and the output latch contents are undefined. table 6-8. port 6 operation modes pin name port mode control signal input/ operation to operate as control pins output mode p60 to p63 input/output ports a16 to a19 outputs specified by bits mm3 to mm0 of the mm in 2-bit units p64 rd output p65 wr output p66 wait input specified by bits pwn1 & pwn0 (n = 0 to 7) of the pwc1 & pwc2 or setting p66 in the input mode hldrq input bus hold enabled by the hlde bit of the hldm p67 hldak output refrq output set (to 1) the rfen bit of the rfm external memory expansion mode is specified by bits mm3 to mm0 of the mm chapter 6 port functions 170 preliminary users manual u13987ej1v0um00 6.8.1 hardware configuration the port 6 hardware configuration is shown in figures 6-51 to 6-54. figure 6-51. p60 to p63 (port 6) block diagram v dd p6n n = 0 to 3 mm0 to mm3 rd puol wr puol puol6 wr pm6 pm6n wr p6 p6n rd pm6 rd p6 pull-up resistor option register l port 6 mode register output latch internal data bus internal address bus input/ output control circuit chapter 6 port functions 171 preliminary users manual u13987ej1v0um00 figure 6-52. p64 and p65 (port 6) block diagram wr puol rd puol wr p6 puol6 p64 (p65) wr pm6 p64 (p65) v dd external expansion mode pm64 (pm65) rd signal (wr signal) rd pm6 rd p6 pull-up resistor option register l port 6 mode register output latch internal bus selector chapter 6 port functions 172 preliminary users manual u13987ej1v0um00 figure 6-53. p66 (port 6) block diagram p66 wr puol puol6 v dd rd puol wr pm6 pm66 wr p6 p66 hold enabled mode external wait specification wait input hold request input rd p6 rd pm6 pull-up resistor option register l port 6 mode register output latch internal bus chapter 6 port functions 173 preliminary users manual u13987ej1v0um00 figure 6-54. p67 (port 6) block diagram pm67 wr puol rd puol wr p6 puol6 p67 wr pm6 p67 v dd rd pm6 rd p6 hold enabled mode refresh mode pull-up resistor option register l port 6 mode register output latch internal bus refresh signal hold acknowledge signal selector chapter 6 port functions 174 preliminary users manual u13987ej1v0um00 6.8.2 i/o mode/control mode setting the port 6 input/output mode is set by setting the port 6 mode register (pm6) as shown in figure 6-55. operations for operating port 6 as control pins are shown in table 6-9. table 6-9. port 6 control pin function pin name control signal i/o mode port mode operation to operate as control pins p60 a16 input/output port p61 a17 p62 a18 p63 a19 p64 rd output port p65 wr p66 wait input/output port external wait input is specified by bits pwn1 & pwn0 (n = 0 to 7) of the pwc1 & pwc2 hldrq bus hold enabled by the hlde bit of the hldm p67 hldak output port refrq set (to 1) the rfen bit of the rfm table 6-10. p60 to p65 control pin specification mm bits operation mode mm3 mm2 mm1 mm0 p60 p61 p62 p63 p64 p65 0 0 0 0 port (p60 to p65) 0011 0 1 0 0 port (p60 to p63) rd wr 0101 0110 0111 1 0 0 0 a16 a17 port 1 0 0 1 a16 a17 a18 a19 (a) port mode each port not specified as in control mode can be specified as input/output in 1-bit units by setting the port 6 mode register (pm6). (b) control signal input/output mode (i) a16 to a19 (address bus) upper address bus output pins when the external memory space is expanded (10000h to fffffh). these pins operate in accordance with the memory expansion mode register (mm). external memory expansion mode specified by bits mm3 to mm0 of the mm (see table 6-10 ) external memory expansion mode specified by bits mm3 to mm0 of the mm (see table 6-10 ) chapter 6 port functions 175 preliminary users manual u13987ej1v0um00 (ii) rd (read strobe) the strobe signal for an external memory read operation. the operation of this pin is controlled by the memory expansion mode register (mm). (iii) wr (write strobe) pin that outputs the strobe signal for an external memory write operation. the operation of this pin is controlled by the memory expansion mode register (mm). (iv) wait (wait) wait signal input pin. operates in accordance with the programmable wait control registers (pwc1, pwc2). (v) hldrq (hold request) external bus hold request signal input pin. operates in accordance with the hold mode register (hldm). (vi) hldak (hold acknowledge) bus hold acknowledge signal output pin. operates in accordance with the hold mode register (hldm). (vii) refrq (refresh request) this pin outputs refresh pulses to pseudo-static memory when this memory is connected to it externally. operates in accordance with the refresh mode register (rfm). figure 6-55. port 6 mode register (pm6) format 7 pm67 pm6 6 pm66 5 pm65 4 pm64 3 pm63 2 pm62 1 pm61 0 pm60 address after reset r/w r/w ffh 0ff26h pm6n p6n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 chapter 6 port functions 176 preliminary users manual u13987ej1v0um00 6.8.3 operating status port 6 is an input/output port, with an alternate function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-56. port specified as output port internal bus output latch p6n n = 0 to 7 rd out wr port chapter 6 port functions 177 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-57. port specified as input port output latch p6n n = 4 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in the control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. (3) when used as control pins cannot be manipulated or tested by software. chapter 6 port functions 178 preliminary users manual u13987ej1v0um00 6.8.4 on-chip pull-up resistors p60 to p67 incorporate pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puol6 bit of the pull- up resistor option register l (puol) and the port 6 mode register (pm6). when puol6 is 1, the on-chip pull-up resistors of the pins for which input is specified by the pm6 (pm6n = 1, n = 0 to 7) are enabled . figure 6-58. pull-up resistor option register l (puol) format remark when stop mode is entered, setting puol to 00h is effective for reducing the current consumption. figure 6-59. pull-up specification (port 6) p66 input buffer p67 p65 p61 p60 v dd port 6 mode register (pm6) puol6 (puol) internal bus 7 0 puol 6 puol6 5 puol5 4 puol4 3 puol3 2 puol2 1 puol1 0 puol0 address after reset r/w r/w 00h 0ff4eh puol6 port 6 pull-up resistor specification not used in port 6 used in port 6 1 0 chapter 6 port functions 179 preliminary users manual u13987ej1v0um00 6.9 port 7 port 7 is an 8-bit input/output port. in addition to operating as an input/output port, it also operates as the a/d converter analog input pins (ani0 to ani7). input/output can be specified in 1-bit units by setting the port 7 mode register (pm7). pin levels can be read or tested at any time irrespective of alternate-function operations. when reset is input, port 7 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.9.1 hardware configuration the port 7 hardware configuration is shown in figure 6-60. figure 6-60. port 7 block diagram p7n (n = 0 to 7) wr p7 p7n rd pm7 pm7n wr pm7 a/d converter rd p7 port 7 mode register output latch internal bus chapter 6 port functions 180 preliminary users manual u13987ej1v0um00 6.9.2 i/o mode/control mode setting the port 7 input/output mode is set for each pin by setting the port 7 mode register (pm7) as shown in figure 6-61. in addition to the operation of port 7 as an input/output port, analog signal input can be performed at any time. mode setting is not necessary. specification of the a/d conversion operation is performed by adm of the a/d converter (see chapter 16 a/d converter for details). figure 6-61. port 7 mode register (pm7) format 7 pm77 pm7 6 pm76 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 address after reset r/w r/w ffh 0ff27h pm7n p7n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 chapter 6 port functions 181 preliminary users manual u13987ej1v0um00 6.9.3 operating status port 7 is an input/output port, with an alternate function as the a/d converter analog input pins (ani0 to ani7). (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-62. port specified as output port internal bus output latch p7n n = 0 to 7 rd out wr port chapter 6 port functions 182 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches-irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-63. port specified as input port output latch p7n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. 6.9.4 on-chip pull-up resistors port 7 does not incorporate pull-up resistors. 6.9.5 caution a voltage outside the range av ss to av ref must not be applied to pins for which p70 to p77 are used as ani0 to an17. see 16.6 cautions in chapter 16 a/d converter for details. chapter 6 port functions 183 preliminary users manual u13987ej1v0um00 6.10 port 9 port 9 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 9 mode register (pm9). each pin incorporates a software programmable pull-up resistor. when reset is input, port 9 is set as an input port (output high-impedance state), and the output latch contents are undefined. 6.10.1 hardware configuration the port 9 hardware configuration is shown in figure 6-64. figure 6-64. port 9 block diagram wr puoh rd puoh wr p9 puoh9 p9n pm9n wr pm9 p9n n = 0 to 7 v dd rd pm9 rd p9 pull-up resistor option register h port 9 mode register output latch internal bus chapter 6 port functions 184 preliminary users manual u13987ej1v0um00 6.10.2 i/o mode/control mode setting the port 9 input/output mode is set for each pin by setting the port 9 mode register (pm9) as shown in figure 6-65. figure 6-65. port 9 mode register (pm9) format 7 pm97 pm9 6 pm96 5 pm95 4 pm94 3 pm93 2 pm92 1 pm91 0 pm90 address after reset r/w r/w ffh 0ff29h pm9n p9n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 1 0 chapter 6 port functions 185 preliminary users manual u13987ej1v0um00 6.10.3 operating status port 9 is an input/output port. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-66. port specified as output port internal bus output latch p9n n = 0 to 7 rd out wr port chapter 6 port functions 186 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high-impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-67. port specified as input port output latch p9n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output, the contents of the output latch of pins specified as inputs will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. chapter 6 port functions 187 preliminary users manual u13987ej1v0um00 6.10.4 on-chip pull-up resistors port 9 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puoh9 bit of the pull- up resistor option register h (puoh) and the port 9 mode register (pm9). when puoh9 is 1, the on-chip pull-up resistors of the pins for which input is specified by the pm9 for port 9 (pm9n = 1, n = 0 to 7) are enabled . figure 6-68. pull-up resistor option register h (puoh) format 7 0 puoh 6 0 5 0 4 0 3 0 2 puoh10 1 puoh9 0 0 address after reset r/w r/w 00h 0ff4fh puoh9 port 9 pull-up resistor specification not used in port 9 used in port 9 1 0 remark when stop mode is entered, setting puoh to 00h is effective for reducing the current consumption. figure 6-69. pull-up specification (port 9) p96 input buffer p97 p95 p91 p90 v dd port 9 mode register (pm9) puoh9 (puoh) internal bus chapter 6 port functions 188 preliminary users manual u13987ej1v0um00 6.11 port 10 port 10 is an 8-bit input/output port with an output latch. input/output can be specified in 1-bit units by setting the port 1 0 mode register (pm10). each pin incorporates a software programmable pull-up resistor. p105 and p107 can be set in the n-ch open- drain mode. in addition to its function as an input/output port, port 10 also has an alternate function as serial interface pin. the operation mode can be specified bit-wise by setting the port 10 mode control register (pmc10), as shown in table 6-11. the pin level of all pins can always be read or tested regardless of the alternate-function pin operation. when reset is input, port 10 is set as an input port (output high-impedance state), and the output latch contents are undefined. table 6-11. port 10 operation modes (n = 0 to 7) mode port mode control signal input/output mode setting condition pmc10n = 0 pmc10n = 1 p100 to p104 input/output port p105 sck3 input/output p106 si3 input p107 so3 output (a) port mode each port specified as port mode by the port 10 mode control register (pmc10) can be specified as input/output in 1- bit units by setting the port 10 mode register (pm10). (b) control signal input/output mode pins can be set as control pins in 1-bit units by setting the port 10 mode control register (pmc10). (i) sck3 (serial clock 3) sck3 is the clocked serial interface serial clock input/output pin (in 3-wire serial i/o 3 mode). (ii) si3 (serial input 3) si3 is the serial data input pin (in 3-wire serial i/o 3 mode). (iii) so3 (serial output 3) so3 is the serial data output pin (in 3-wire serial i/o 3 mode). chapter 6 port functions 189 preliminary users manual u13987ej1v0um00 6.11.1 hardware configuration the port 10 hardware configuration is shown in figures 6-70 to 6-73. figure 6-70. p100 to p104 (port 10) block diagram wr puoh rd puoh wr p10 puoh10 p10n pm10n wr pm10 p10n n = 0 to 4 v dd rd pm10 rd p10 pull-up resistor option register h port 10 mode register output latch internal bus chapter 6 port functions 190 preliminary users manual u13987ej1v0um00 figure 6-71. p105 (port 10) block diagram wr puoh rd puoh wr pm10 rd pm10 wr pmc10 rd pmc10 rd p10 rd p10 puoh10 pm105 pmc105 p105 sck3 output sck3 input v dd v dd p105 pull-up resistor option register h port 10 mode register output latch internal bus port 10 mode control register selector sck3 input n-ch open-drain specification (csim3 mod3 bit) chapter 6 port functions 191 preliminary users manual u13987ej1v0um00 figure 6-72. p106 (port 10) block diagram p106 v dd wr puoh wr p10 si3 input rd puoh wr pm10 wr pmc10 rd pmc10 puoh10 pm10n p106 pmc106 rd pm10 rd p10 pull-up resistor option register h port 10 mode register output latch internal bus port 10 mode control register chapter 6 port functions 192 preliminary users manual u13987ej1v0um00 figure 6-73. p107 (port 10) block diagram wr puoh rd puoh wr pm10 rd pm10 wr pmc10 rd pmc10 wr p10 rd p10 puoh10 pm107 pmc107 p107 so3 output v dd v dd p107 n-ch open-drain specification (scim3 mod3 bit) pull-up resistor option register h port 10 mode register output latch internal bus port 10 mode control register selector chapter 6 port functions 193 preliminary users manual u13987ej1v0um00 6.11.2 i/o mode/control mode setting the port 10 input/output mode is set for each pin by means of the port 10 mode register (pm10) as shown in figure 6-74. in addition to their input/output port function, port 10 also have an alternate function as serial interface pin, and the contr ol mode is specified by setting the port 10 mode control register (pmc10) as shown in figure 6-75. figure 6-74. port 10 mode register (pm10) format 7 pm107 pm10 6 pm106 5 pm105 4 pm104 3 pm103 2 pm102 1 pm101 0 pm100 address after reset r/w r/w ffh 0ff2ah pm10n p10n pin input/output mode specification (n = 0 to 7) output mode (output buffer on) intput mode (output buffer off) 1 0 figure 6-75. port 10 mode control register (pmc10) format 7 pmc107 pmc10 6 pmc106 5 pmc105 4 0 3 0 2 0 1 0 0 0 address after reset r/w r/w 00h 0ff4ah pmc105 p105 pin control mode specification input/output port mode sck3 input/output mode 1 0 pmc106 p106 pin control mode specification input/output port mode si3 input mode 1 0 pmc107 p107 pin control mode specification input/output port mode so3 output mode 1 0 chapter 6 port functions 194 preliminary users manual u13987ej1v0um00 6.11.3 operating status port 10 is an input/output port, with an alternate function as various control pins. (1) when set as an output port the output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions. the output latch contents can be freely set by means of logical operation instructions. once data has been written to the output latch, it is retained until data is next written to the output latch note . note including the case where another bit of the same port is manipulated by a bit manipulation instruction. figure 6-76. port specified as output port internal bus output latch p10n n = 0 to 7 rd out wr port chapter 6 port functions 195 preliminary users manual u13987ej1v0um00 (2) when set as an input port the port pin level can be loaded into an accumulator by means of a transfer instruction. in this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all outp ut latches irrespective of the port input/output specification. however, since the output buffer of a bit specified as an input p ort is high impedance, the data is not output to the port pin (when a bit specified as input is switched to an output port, the out put latch contents are output to the port pin). also, the contents of the output latch of a bit specified as an input port cannot be loaded into an accumulator. figure 6-77. port specified as input port output latch p10n n = 0 to 7 rd in wr port internal bus caution a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs and pins specified as control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. chapter 6 port functions 196 preliminary users manual u13987ej1v0um00 (3) when specified as control signal input/output by setting (to 1) bits of the port 10 mode control register (pmc10), port 10 can be used as control signal input or output in 1-bit units irrespective of the setting of the port 10 mode register (pm10). when a pin is used as a control signal, the contr ol signal status can be seen by executing a port read instruction. figure 6-78. control specification p10n n = 0 to 7 pm10n = 0 pm10n = 1 rd control (output) internal bus control (input) (a) when port is control signal output when the port 10 mode register (pm10) is set (to 1), the control signal pin level can be read by executing a port read instruction. when pm10 is reset (to 0), the m pd784938 internal control signal status can be read by executing a port read instruction. (b) when port is control signal input only the port 10 mode register (pm10) is set (to 1), control signal pin levels can be read by executing a port read instruction. chapter 6 port functions 197 preliminary users manual u13987ej1v0um00 6.11.4 on-chip pull-up resistors port 10 incorporates pull-up resistors. use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. whether or not an on-chip pull-up resistor is to be used can be specified for each pin by setting the puoh10 bit of the pull- up resistor option register h (puoh) and the port 10 mode register (pm10). when puoh10 is 1, the on-chip pull-up resistors of the pins for which input is specified by pm10 (pm10n = 1, n = 0 to 7) are enabled. also, the specification for use of the pull-up resistor is also valid for pins specified as control mode pins (pull-up resistor s are also connected to pins that function as output pins in the control mode). therefore, if you do not want to connect the pull-up resistors in the control mode, the contents of the corresponding bits of pm10 should be set to 0 (output mode). figure 6-79. pull-up resistor option register h (puoh) format 7 0 puoh 6 0 5 0 4 0 3 0 2 puoh10 1 puoh9 0 0 address after reset r/w r/w 00h 0ff4fh puoh10 port 10 pull-up resistor specification not used in port 10 used in port 10 1 0 remark when stop mode is entered, setting puoh to 00h is effective for reducing the current consumption. figure 6-80. pull-up specification (port 10) p106 input buffer p107 p105 p101 p100 v dd port 10 mode register (pm10) puoh10 (puoh) internal bus chapter 6 port functions 198 preliminary users manual u13987ej1v0um00 6.12 port output check function the m pd784938 has a function for reading and testing output port pin levels in order to improve the reliability of application systems. it is therefore possible to check the output data and the actual pin status as required. if there is a mismatch, app ropriate action can be taken, such as replacement with another system. special instructions, chkl and chkla, are provided to check the port status. these instructions perform a comparison by taking the exclusive or of the pin status and the output latch contents (in port mode), or the pin status and the internal cont rol output signal level (in control mode). example an example of a program that checks the pin status and output latch contents using the chkl instruction and chkla instruction is as follows. test : set1 p0.3 ; set bit 3 of port 0 chkl p0 ; check port 0 bne $ err1 ; branch to error processing (err1) in case of mismatch with output latch contents . . . err1 : chkla p0 ; faulty bit check bt a.7, $bit07 ; bit 7? bt a.6, $bit06 ; bit 6? . . . bt a.1, $bit01 ; bit 1? br $bit00 ; if none of the bits, bit 0 is faulty cautions 1. if each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the chkl or chkla instruction will always show a match whether the individual pins of the port are port pins or control pins. therefore, executing these instructions on a port set to input mode is actually ineffective. 2. if the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the chkl or chkla instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the chkl or chkla instruction). 3. as port 2 is an input-only port, a comparison of the pin status with the output latch contents using the chkl or chkla instruction will always show a match. therefore, executing these instructions on port 2 is actually ineffective. chapter 6 port functions 199 preliminary users manual u13987ej1v0um00 6.13 cautions (1) all port pins become high-impedance after reset signal input (on-chip pull-up resistors are disconnected from the pins). if there is a problem with pins becoming high-impedance during reset input, this should be handled with external circuitry. (2) bit 7 of the pull-up resistor option register (puo) that sets the on-chip pull-up resistor connection is fixed at 0, but if 1 is written to bit 7 of the puo in the in-circuit emulator, 1 will be read. (3) output latch contents are not initialized by reset input. when a port is used as an output port, the output latch must be initialized without fail before turning on the output buffer. if the output latch is not initialized before turning on the output buffer, unexpected data will be output to the output port. similarly, for pins used as control pins, internal peripheral hardware initialization must be performed before performing the control pin specification. (4) as p22 to p26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate-function pins (intp1 to intp5). therefore, the interrupt request flags should be cleared after specifying pull-up in the initialization routine. (5) when p40 to p47 and p50 to p57 are used as the address/data bus and address bus respectively in the m pd784938, bits puo4 and puo5 of the pull-up resistor option register (puo) must be set to 0 so that on-chip pull-up resistor connection is not performed. (6) a voltage outside the range av ss to av ref must not be applied to pins for which p70 to p77 are used as ani0 to ani7. see 16.6 cautions in chapter 16 a/d converter for details. (7) a bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins or port mode and control mode, the contents of the output latch of pins specified as inputs or pins specified as in control mode will be undefined (excluding bits manipulated with a set1 or clr1 instruction, etc.). particular care is required when there are bits which are switched between input and output. caution is also required when manipulating the port with other 8-bit arithmetic instructions. (8) if each port is set to input mode, a comparison of the pin status with the output latch contents (or control output level) using the chkl or chkla instruction will always show a match whether the individual pins of the port are port pins or control pins. therefore, executing these instructions on a port set to input mode is actually ineffective. (9) if the output levels of a port in which control outputs and port outputs are mixed in a single port are checked with the chkl or chkla instruction, the input/output mode of control output pins should be set to input mode before executing these instructions (as the output levels of control outputs vary asynchronously, the output level cannot be checked with the chkl or chkla instruction). (10) as port 2 is an input-only port, a comparison of the pin status with the output latch contents using the chkl or chkla instruction will always show a match. therefore, executing these instructions on port 2 is actually ineffective. 200 preliminary users manual u13987ej1v0um00 [memo] 201 preliminary users manual u13987ej1v0um00 chapter 7 real-time output function 7.1 configuration and function the real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (p0h, p0l) , shown in figure 7-1. the real-time output function refers to the transfer to the output latch by hardware of data prepared in the p0h and p0l beforehand, simultaneously with the generation of an interrupt from timer/event counter 1 or external interrupt, and its output off-chip. the pins that output the data off-chip are called real-time output ports. the following two kinds of real-time output data are handled: ? 4 bits 2 channels ? 8 bits 1 channel by combining the real-time output function with the macro service function described later, the functions of a pattern generato r with programmable timing are implemented without software intermediation. this is ideally suited to stepping motor control, for example. figure 7-1 shows the block diagram of the real-time output port. 202 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 figure 7-1. real-time output port block diagram internal bus selector rtpc byte p0mh extr p0ml intc11 intp0 intc10 extr trgp0 trgp0 p0ml p0mh byte 4-bit real-time output (p0h) 4-bit real-time output (p0l) 8-bit real-time output (p0) 4 4 output latch p0 p0h p0l port 0 buffer registers p07 p05 p06 p04 p03 p02 p01 p00 8 44 selector 203 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 7.2 real-time output port control register (rtpc) rtpc is an 8-bit register that specifies the function of port 0. rtpc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. figure 7-2 shows the format of rtpc. reset input clears rtpc to 00h. figure 7-2. real-time output port control register (rtpc) format caution when p0ml and p0mh bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (pm0). the output latch contents should therefore be initialized before making a real-time output port specification. 7 byte rtpc 6 0 5 0 4 p0mh 3 extr 2 0 1 trgp0 0 p0ml address after reset r/w r/w 00h 0ff2eh p0ml p00 to p03 function specification port mode real-time output port mode 1 0 extr trgp0 enabling of data transfer to output latch from p0h, p0l by intp0 not enabled (data transfer by intc10 only) transfer by either intp0 or intc10 transfer by intp0 only setting prohibited enabled ?byte = 0: p0l only transferred ?byte = 1: p0l/p0h transferred 1 1 0 0 1 01 0 p0mh p04 to p07 function specification port mode real-time output port mode 1 0 byte real-time output port operating mode 4-bit separate real-time output port 8-bit real-time output port 1 0 204 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 7.3 real-time output port accesses the port 0 buffer registers (p0h, p0l) are mapped onto mutually independent addresses in the sfr area as shown in figure 7-3. when the 4-bit 2-channel real-time output function is specified, data can be set in the p0h, p0l independently of each other. when the 8-bit 1-channel real-time output function is specified, data can be set in p0h and p0l by writing 8-bit data to either one of the p0h or p0l. table 7-1 shows the operations when port 0, the p0h and p0l are manipulated. figure 7-3. port 0 buffer register (p0h, p0l) configuration high-order 4 bits p0h low-order 4 bits p0l 0ff0eh 0ff0fh table 7-1. operations when port 0 and port 0 buffer registers (p0h, p0l) are manipulated operation mode register read operation write operation high-order 4 bits low-order 4 bits high-order 4 bits low-order 4 bits 8-bit port mode p0 output latch output latch p0l buffer register note buffer register p0h buffer register note buffer register 8-bit real-time output p0 output latch port mode p0l buffer register buffer register p0h buffer register buffer register 4-bit separate real-time p0 output latch output port mode p0l buffer register note buffer register p0h buffer register note buffer register p00 to p03: ports p0 output latch output latch p04 to p07: real-time p0l buffer register note buffer register output port mode p0h buffer register note buffer register p00 to p03: real-time p0 output latch output latch output port mode p0l buffer register note buffer register p04 to p07: ports p0h buffer register note buffer register note the contents of p0h are read from the high-order 4 bits, and the contents of p0l from the low-order 4 bits. remark : the output latch and port 0 buffer registers are not affected. 205 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 206 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 7.4 operation when the port 0 function is specified as the real-time output port, the port 0 buffer register (p0h, p0l) contents are fetched into the output latch and output to the port 0 pins in synchronization with the generation of one of the trigger conditions sho wn in table 7-2. for example, the timer/event counter 1 timer counter 1 (tm1) and compare register (cr10, cr11) match signal (intc10, intc11) can be selected as the output trigger generation source. in this case, the port 0 pin output data can be changed to th e p0h and p0l values using the value set in the cr10, cr11 beforehand as the timing interval. combining this real-time output port function with the macro service function enables the port 0 output pin output data to be changed sequentially at any inter val time (see 23.8 macro service function ). if the intp0 external interrupt pin is selected as the output trigger source, port 0 output can be obtained in synchronization with an external event. table 7-2. real-time output port output triggers (when p0mh = p0ml = 1) rtpc output mode p0h p0l byte extr trgp0 0 0 0 4-bit real-time output intc11 intc10 0 1 0 intc11 intc10 or intp0 0 1 1 intc11 intp0 1 0 0 8-bit real-time output intc10 1 1 0 intc10 or intp0 1 1 1 intp0 207 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 figure 7-4. real-time output port operation timing intc11 interrupt request cpu operation timer/event counter 1 0h ffh output latches p07 to p04 timer start port 0 buffer register p0h d01 cr11 cr11 cr11 cr11 d01 d02 d00 port 0 buffer register and compare register overwrite by software servicing or macro service (see 23.8 macro service function ) d03 d04 d02 d03 208 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 figure 7-5. real-time output port operation timing (2-channel independent control example) intc11 interrupt request cpu operation timer/event counter 1 0h ffh timer start output latches p07 to p04 d00 port 0 buffer register p0h d01 cr11 cr11 cr11 cr11 cr10 cr10 cr10 intc10 interrupt request p0l d11 p03 to p00 d02 d03 d04 d14 d12 d13 d01 d02 d13 d11 d12 d10 d03 port 0 buffer register and compare register overwrite by software servicing or macro service (see 23.8 macro service function ) 209 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 7.5 example of use the case in which p00 to p03 are used as a 4-bit real-time output port is shown here. each time the contents of timer/event counter 1 timer counter 1 (tm1) and compare register (cr10) match, the contents of port 0 buffer register (p0l) are output to p00 to p03. at this time, the next data to be output and the timing at which the ou tput is to be changed next are set in the service routine for the simultaneously generated interrupt (see figure 7-6 ). see chapter 10 timer/event counter 1 for the method of using timer/event counter 1. the control register settings are shown in figure 7-7, the setting procedure in figure 7-8, and the processing in the interrupt service routine in figure 7-9. figure 7-6. real-time output port operation timing intc10 interrupt request timer/event counter 1 0h ffh output pins p00 to p03 d01 d02 port 0 buffer register p0l d02 d03 cr10 cr10 cr10 cr10 output latches p00 to p03 d01 d02 d03 d04 d03 d01 d00 d00 p0l and cr10 overwritten by intc10 interrput p0l contents transferred to output latch on match of tm1 and cr10 timer start output buffer turned on next data to be output is set in p0l initial output data is set in output latches p00 to p03 hi-z 210 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 figure 7-7. real-time output function control register settings 7 0 rtpc 6 0 5 0 4 0 3 0 2 0 1 0 0 0 p00 to p03 used as real-time output port p04 to p07 used as normal output port 4-bit separate real-time output ports selected data transfer to output latch from p0l by intp0 disabled figure 7-8. real-time output function setting procedure real-time output port set initial value in p0 output latch set next value to be output in p0l set real-time output port control register (rtpc) set timer/event counter 1 intc10 interrupt timer start 211 chapter 7 real-time output function preliminary users manual u13987ej1v0um00 figure 7-9. interrupt request servicing when real-time output function is used timer interrupt interval time setting set next value to be output in p0l return 7.6 cautions (1) when p0ml and p0mh bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (pm0). the output latch contents should therefore be initialized before making a real-time output port specification. (2) when the port is specified as a real-time output port, values cannot be directly written to the output latch by software. therefore, the initial value of the output latch must be set by software before specifying use as a real-time output port. also, if the need arises to forcibly set the output data to a fixed value while the port is being used as a real-time output port, you should change the port to a normal output port by manipulating the real-time output port control register (rtpc), then write the value to be output to the output latch. 212 preliminary users manual u13987ej1v0um00 [memo] 213 preliminary users manual u13987ej1v0um00 chapter 8 outline of timer the m pd784938 incorporates three timer/event counter units and one timer unit. these timer/event counter and timer units can be used as seven units of timer/event counters because the m pd784938 supports seven interrupt requests. table 8-1. operations of timer name timer/event timer/event timer/event timer 3 item counter 0 counter 1 counter 2 count 8 bits ??? width 16 bits ?? ? ? operation interval timer 2 ch 2 ch 2 ch 1 ch mode external event counter ?? ? one-shot timer ? function timer output 2 ch 2 ch toggle output ? ? pwm/ppg output ? ? one-shot pulse output note ? real-time output ? pulse width measurement 1 input 1 input 2 inputs number of interrupt requests 2 2 2 1 note in the one-shot pulse output function, the pulse output level activated by software and inactivated by hardware (an interrupt request signal). this function is different in nature from the one-shot timer function of timer/event counter 2. 214 chapter 8 outline of timer preliminary users manual u13987ej1v0um00 figure 8-1. timer block diagram timer/event counter 0 timer/event counter 2 clear control intc00 compare register (cr00) pulse output control ovf intc01 to0 to1 timer counter 0 (tm0) prescaler edge detection selector match match intp3 f xx /4 intp3 software trigger compare register (cr01) capture register (cr02) timer/event counter 1 edge detection intp0 intp0 clear control compare register (cr10/cr10w) capture/compare register (cr11/cr11w) capture register (cr12/cr12w) ovf timer counter 1 (tm1/tm1w) prescaler selector match f xx /4 event input to real-time output port intc11 intc10 match clear control intc20 compare register (cr20/cr20w) capture/compare register (cr21/cr21w) capture register (cr22/cr22w) pulse output control ovf intc21 to2 to3 timer counter 2 (tm2/tm2w) prescaler edge detection selector match match intp1 f xx /4 intp2/ci intp1 intp2 edge detection timer 3 remark ovf: overflow flag compare register (cr30/cr30w) timer counter 3 (tm3/tm3w) prescaler match f xx /4 match uart, csi intc30 215 preliminary users manual u13987ej1v0um00 chapter 9 timer/event counter 0 9.1 functions timer/event counter 0 is a 16-bit timer/event counter. in addition to its basic functions of interval timer, programmable square-wave output, pulse width measurement and event counter, timer/event counter 0 can be used for the following functions. ? pwm output ? cycle measurement ? soft triggered one-shot pulse output (1) interval timer generates internal interrupts at preset intervals. table 9-1. timer/event counter 0 interval time minimum interval time maximum interval time resolution 4/f xx 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.20 m s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz 216 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (2) programmable square-wave output outputs square waves independently to the timer output pins (to0, to1). table 9-2. timer/event counter 0 programmable square-wave output setting range minimum pulse width maximum pulse width 4/f xx 2 16 4/f xx (0.32 m s) (20.8 ms) 8/f xx 2 16 8/f xx (0.64 m s) (41.7 ms) 16/f xx 2 16 16/f xx (1.27 m s) (83.4 ms) 32/f xx 2 16 32/f xx (2.54 m s) (167 ms) 64/f xx 2 16 64/f xx (5.09 m s) (333 ms) 128/f xx 2 16 128/f xx (10.17 m s) (667 ms) 256/f xx 2 16 256/f xx (20.35 m s) (1.33 s) 512/f xx 2 16 512/f xx (40.70 m s) (2.67 s) 1,024/f xx 2 16 1,024/f xx (81.40 m s) (5.33 s) ( ): when f xx = 12.58 mhz 217 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (3) pulse width measurement detects the pulse width of the signal input to the external interrupt request input pin (intp3). table 9-3. timer/event counter 0 pulse width measurement range measurable pulse width note resolution 4/f xx to 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx to 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx to 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx to 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx to 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx to 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx to 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx to 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz note the minimum pulse width that can be measured differs depending on the selected value of f clk . the minimum pulse width that can be measured is the value of 3/f clk or the value in the above table, whichever is greater. (4) software triggered one-shot pulse output this is a one-shot pulse output function in which the pulse output level is activated by software and inactivated by hardware (an interrupt request signal). control can be performed for the timer output pins (to0, to1) independently. caution the software triggered one-shot pulse output function is different in nature from the one-shot timer function of timer/event counter 2. 218 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (5) external event counter counts the clock pulses input from the external interrupt request input pin (intp3). the clocks that can be input to timer/event counter 0 are shown in table 9-4. table 9-4. timer/event counter 0 pulse width measurement time when counting one edge when counting both edges maximum frequency f clk /6 (2.10 mhz) f clk /6 (2.10 mhz) minimum pulse width 3/f clk (0.24 m s) 3/f clk (0.24 m s) (high and low levels) ( ): when f clk = 12.58 mhz 9.2 configuration timer/event counter 0 consists of the following registers: ? timer counter (tm0) 1 ? compare register (cr00, cr01) 2 ? capture register (cr02) 1 the block diagram of timer/event counter 0 is shown in figure 9-1. 219 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-1. timer/event counter 0 block diagram internal bus 1/8 8/16 8 1/8 external interrupt mode register 1 (intm1) es31 es30 p24/intp3 edge detection circuit compare register (cr00) 16 16 16 mod1 mod0 clr01 pwm/ppg output control capture/compare control register 0 (crc0) ent01 alv1 ent00 alv0 timer output control register (toc) match p34/to0 intc00 p35/to1 intc01 reset clear overflow compare register (cr01) 16 16 16 16 16 16 8 selector prescaler f xx /1,024 f xx /512 f xx /256 f xx /128 f xx /64 f xx f xx /32 f xx /16 f xx /8 f xx /4 prescaler mode register 0 (prm0) prs03 prs02 prs01 prs00 capture register (cr02) timer counter 0 (tm0) timer control register 0 (tmc0) ovf0 ce0 st1 rt1 os1 st0 rt0 os0 one-shot pulse control register (ospc) 1/8 1/8 internal bus capture trigger output control circuit output control circuit 220 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (1) timer counter 0 (tm0) tm0 is a timer counter that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 0 (prm0). the count operation is stopped or enabled by means of timer control register 0 (tmc0). tm0 can be read only with a 16-bit manipulation instruction. when reset is input, tm0 is cleared to 0000h and the count is stopped. (2) compare registers (cr00/cr01) cr00 and cr01 are 16-bit registers that hold the values that determine the interval timer frequency. if the cr00/cr01 contents match the contents of tm0, an interrupt request (intc00/intc01) and timer output control signal are generated. also, the count value can be cleared by a content match (cr01). cr00 and cr01 can be read or written with a 16-bit manipulation instruction. the contents of these registers are undefined after reset input. (3) capture register (cr02) cr02 is a 16-bit register that captures the contents of tm0. the capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp3). the contents of the cr02 are retained until the next capture trigger is generated. cr02 can be read only with a 16-bit manipulation instruction. the contents of this register are undefined after reset input. (4) edge detection circuit the edge detection circuit detects an external input valid edge. when the valid edge set by external interrupt mode register 1 (intm1) is detected in the intp3 pin input, the external interrupt request (intp3), a capture trigger, and a external event count clock are generated (see figure 22-2 for details of the intm1). (5) output control circuit it is possible to invert the timer output when the compare register (cr00, cr01) register contents and the contents of the timer counter (tm0) match. a square wave can be output from the timer output pins (to0/to1) in accordance with the setting of the low-order 4 bits of the timer output control register (toc). at this time, pwm output or ppg output can be performed according to the specification of capture/compare control register 0 (crc0). in addition, one-shot pulse output can also be performed by means of a software trigger. timer output can be disabled/enabled by means of the toc. when timer output is disabled, a fixed level is output to the to0 and to1 pins (the output level is set by the toc). (6) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer counter 0 (tm0) to perform count operations. (7) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 0 (tm0). 221 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.3 timer/event counter 0 control registers (1) timer control register 0 (tmc0) the timer/event counter 0 tm0 count operation is controlled by the low-order 4 bits in the tmc0 (the high-order 4 bits control the count operation of the tm3/tm3w of the timer 3). tmc0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of tmc0 is shown in figure 9-2. reset input clears tmc0 to 00h. figure 9-2. timer control register 0 (tmc0) format 7 ce3 tmc0 6 0 5 0 4 bw3 3 ce0 2 ovf0 1 0 0 0 address after reset r/w r/w 00h 0ff5dh ovf0 tm0 overflow flag no overflow overflow (count up from ffffh to 0000h) 1 0 ce0 tm0 count operation control count operation stopped with count cleared count operation enabled 1 0 countrols count operation of the tm3/tm3w of the timer 3 (see figure 12-2 ). remark the ovf0 bit is reset by software only. 222 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (2) prescaler mode register 0 (prm0) the count clock of the timer/event counter 0 tm0 is specified by the low-order 4 bits of prm0 (the high-order 4 bits specify the count clock of the timer 3, tm3/tm3w). prm0 can be read/written with an 8-bit manipulation instruction. the format of prm0 is shown in figure 9-3. reset input sets prm0 to 11h. figure 9-3. prescaler mode register 0 (prm0) format prs3 prs2 prs1 prs0 prs03 prs02 prs01 prs00 76543210 prm0 0ff5ch address 11h after reset r/w r/w prs03 0 0 0 0 0 0 0 0 1 1 1 specifies count clock of the tm3/tm3w of the timer 3 (see figure 12-3 ). prs02 0 0 0 0 1 1 1 1 0 0 1 prs01 0 0 1 1 0 0 1 1 0 0 1 prs00 0 1 0 1 0 1 0 1 0 1 1 timer/event counter 0 tm0 count clock specification count clock [hz] specification setting prohibited f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock (intp3) setting prohibited 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 (f xx = 12.58 mhz) other than the above resolution [ s] m remark f xx : x1 input frequency or oscillation frequency 223 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (3) capture/compare control register 0 (crc0) crc0 specifies the enabling conditions for the tm0 clear operation by a match signal between the contents of the compare register (cr01) and the timer counter 0 (tm0) counter value, and the timer outputs (to0/to1) mode. crc0 can be read/written with an 8-bit manipulation instruction. the format of crc0 is shown in figure 9-4. reset input sets crc0 to 10h. figure 9-4. capture/compare control register 0 (crc0) format 7 mod1 crc0 6 mod0 5 0 4 1 3 clr01 2 0 1 0 0 0 address after reset r/w r/w 10h 0ff30h mod1 mod0 clr01 timer output mode specification tm0 clear opration when tm0 = cr01 toggle output toggle output pwm output toggle output toggle output toggle output pwm output pwm output disabled to0 to1 setting prohibited setting prohibited setting prohibited disabled enabled disabled 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ppg output toggle output enabled 224 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (4) timer output control register (toc) toc is an 8-bit register that controls the active level of timer output and output enabling/disabling. the operation of the timer output pins (to0/to1) by the timer/event counter 0 is controlled by the low-order 4 bits (the high- order 4 bits control the operation of the timer output pins (to2/to3) by the timer/event counter 2). toc can be written to or read with an 8-bit manipulation instruction or bit manipulation instruction. the format of toc is shown in figure 9-5. reset input clears toc to 00h. figure 9-5. timer output control register (toc) format 7 ento3 toc 6 alv3 5 ento2 4 alv2 3 ento1 2 alv1 1 ento0 0 alv0 address after reset r/w r/w 00h 0ff31h alv0 to0 pin active level toggle output specifica- tion or one-shot pulse output specificaton pwm/ppg output specification low level high level high level low level 1 0 ento0 to0 pin operation specification alv0 output pulse output enabled 1 0 ento1 to1 pin operation specification alv1 output pulse output enabled 1 0 countrol timer output pins (to2/to3) by timer/ event counter 2 (see figure 11-5 ). alv1 to1 pin active level toggle output specifica- tion or one-shot pulse output specificaton pwm/ppg output specification low level high level high level low level 1 0 225 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (5) one-shot pulse output control register (ospc) ospc is an 8-bit register that specifies enabling/disabling of one-shot pulse output by a software trigger and the output level, etc. ospc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of ospc is shown in figure 9-6. reset input clears ospc to 00h. figure 9-6. one-shot pulse output control register (ospc) format remarks 1. the rt0, st0, rt1, and st1 bits are write-only, and show a value of 0 if read. 2. pin pulse output disabling/enabling and active level setting are performed by means of the timer output control register (toc). 7 st1 ospc 6 rt1 5 0 4 os1 3 st0 2 rt0 1 0 0 os0 address after reset r/w r/w 00h 0ff7dh os0 to0 pulse output type selection toggle output/pwm output/ppg output selectable software triggerd one-shot pulse selectable 1 0 st0 to0 output control output not changed inactive level output to to0 0 0 rt0 1 0 active level output to to0 setting prohibited 1 1 1 0 os1 to1 pulse output type selection toggle output/pwm output/ppg output selectable software triggerd one-shot pulse output 1 0 st1 to1 output control output not changed inactive level output to to1 0 0 rt1 1 0 active level output to to1 setting prohibited 1 1 1 0 226 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.4 timer counter 0 (tm0) operation 9.4.1 basic operation in the timer/event counter 0 count operation, an count-up is performed using the count clock specified by the low-order 4 bits of prescaler mode register 0 (prm0). count operation enabling/disabling is controlled by bit 3 (ce0) of timer control register 0 (tmc0). when the ce0 bit is set (to 1) by software, the contents of tm0 are cleared to 0000h on the first count clock, and then the count-up operation is perfo rmed. when the ce0 bit is cleared (to 0), tm0 becomes 0000h immediately, and capture operations and match signal generation are stopped. if the ce0 bit is set (to 1) again when it is already set (1), tm0 continues the count operation without being cleared. if the count clock is input when tm0 is ffffh, tm0 becomes 0000h. in this case, ovf0 bit is set (to 1) and an overflow signal is sent to the output control circuit. ovf0 bit is cleared by software only. the count operation is continued. when reset is input, tm0 is cleared to 0000h, and the count operation is stopped. 227 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-7. basic operation of timer counter 0 (tm0) (a) count started ? count stopped ? count started (b) when 1 is written to the ce0 bit again after the count starts (c) operation when tm0 = ffffh tm0 ce0 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce0 ? 1 count stopped ce0 ? 0 count started ce0 ? 1 count clock f clk /8 tm0 ce0 0h 0h 1h 2h 3h 4h 5h 6h count started ce0 ? 1 rewrite ce0 ? 1 count clock f clk /8 tm0 ovf0 fffeh ffffh 0h cleared by software ovf0 ? 0 count clock f clk /8 1h 228 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.4.2 clear operation (1) clear operation after a match with the compare register the timer counter 0 (tm0) can be cleared automatically after a match with the compare register (cr01). when a clearance source arises, tm0 is cleared to 0000h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 9-8. tm0 clearance by match with compare register (cr01) (2) clear operation by the ce0 bit of the timer control register 0 (tmc0) the timer counter 0 (tm0) is also cleared when the ce0 bit of tmc0 is cleared (to 0) by software. the clear operation is performed immediately after clearance (to 0) of the ce0 bit. tm0 compare register (cr01) n cleared here count clock 0 1 n-1 n tm0 and cr01 match 229 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-9. clear operation when ce0 bit is cleared (0) (a) basic operation (b) restart before count clock input after clearance (c) restart after count clock input after clearance tm0 ce0 n count clock n-1 0 tm0 ce0 n 0 count clock n-1 0 1 2 if the ce0 bit is set (to 1) before this count clock, the count starts from 0 on the count clock. tm0 ce0 n count clock n-1 0 0 0 1 if the ce0 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce0 bit is set (to 1). 230 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.5 external event counter function the timer/event counter 0 can count clock pulses input from the external interrupt request input pin (intp3). no special selection method is needed for the external event counter operation mode. when the timer counter 0 (tm0) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 0 (prm0), tm0 oper ates as an external event counter. the maximum frequency of external clock pulses that can be counted by tm0 as the external event counter is 2.10 mhz (f clk = 12.58 mhz) irrespective of whether only one edge or both edges are counted on intp3 input. the pulse width of the intp3 input must be at least 3 system clocks (0.24 m s: f clk = 12.58 mhz) for both the high level and low level. if the pulse width is shorter than this, the pulse may not be counted. the timer/event counter 0 external event counter timing is shown in figure 9-10. figure 9-10. timer/event counter 0 external event count timing (1) counting one edge (maximum frequency = f clk /6) remark ici: intp3 input signal after passing through edge detection circuit (2) counting both edges (maximum frequency = f clk /6) remark ici: intp3 input signal after passing through edge detection circuit ici tm0 intp3 dn 3/f clk (min.) 3/f clk (min.) 6/f clk (min.) dn+1 dn+2 dn+3 2-3/f clk ici tm0 intp3 dn+1 dn dn+2 dn+3 dn+4 dn+5 3/f clk (min.) 3/f clk (min.) 6/f clk (min.) 2-3/f clk 231 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 the tm0 count operation is controlled by the ce0 bit of the timer control register 0 (tmc0) in the same way as with basic operation. when the ce0 bit is set (to 1) by software, the contents of tm0 are set to 0000h and the count-up is started on the initial cou nt clock. when the ce0 bit is cleared (to 0) by software during a tm0 count operation, the contents of tm0 are set to 0000h immediately and the stopped state is entered. the tm0 count operation is not affected if the ce0 bit is set (to 1) by software again when it is already set (to 1). caution when timer/event counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 0 (tm0) alone (see figure 9-11), since the contents of tm0 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. an example is shown in figure 9-12. figure 9-11. example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input tm0 0 intp3 1 2 0 count start no distinction made 232 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-12. to distinguish whether one or no valid edge has been input with external event counter (a) processing when count is started clear intp3 interrupt request flag pif3 ? 0 ; clear pif3 to 0 end start count start count ce0 ? 1 ; set ce0 to 1 (b) processing when count value is read read tm0 contents ax ? tm0 ax ? ax+1 ; check pif3 contents if 1, there is a valid edge ; number of input valid edges is set in ax register ; check tm0 value if 0, check interrupt request flag end pif3 = 1? yes yes no no count value read ax = 0? 233 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.6 compare register and capture register operation 9.6.1 compare operations timer/event counter 0 performs compare operations in which the value set in compare registers (cr00, cr01) are compared with the timer counter 0 (tm0) count value. if the count value of tm0 matches the preset cr0n (n = 0, 1) value as the result of the count operation, a match signal is sent to the output control circuit, and at the same time an interrupt request (intc00/intc01) is generated. after a match with the cr01 value, the tm0 count value can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr01. figure 9-13. compare operation intc00 interrupt request tm0 count value 0h ffffh count start ce0 ? 1 cr00 value cr01 value ffffh cr00 value cr01 value intc01 interrupt request ovf0 match match match match cleared by software remark clr01 = 0 234 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-14. tm0 clearance after match detection remark clr01 = 0 intc00 interrupt request tm0 count value 0h cr01 count start ce0 ? 1 intc01 interrupt request cr00 clear clear cr01 cr00 235 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.6.2 capture operations timer/event counter 0 performs capture operations in which the timer counter 0 (tm0) count value is fetched into the capture register in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pin (intp3) is used as the external trigger (capt ure trigger). the count value of tm0 in the process of being counted is fetched into the capture register (cr02) in synchronizatio n with the capture trigger, and is retained there. the contents of the cr02 are retained until the next capture trigger is gener ated. the capture trigger valid edge is set by means of external interrupt mode register 1 (intm1). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured. also, if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 22-2 for details of the intm1. figure 9-15. capture operation remark dn: tm0 count value (n = 0, 1, 2, ...) clr01 = 0 intp3 pin input intp3 interrupt request tm0 count value 0h ffffh ovf0 d0 d1 d2 count start ce0 ? 1 d0 d1 d2 capture register (cr02) 236 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.7 basic operation of output control circuit the output control circuit controls the timer output pin (to0/to1) levels by means of overflow signals or match signals from the compare registers (cr00, cr01). the operation of the output control circuit is determined by the timer output control regi ster (toc), capture/compare control register 0 (crc0), and the one-shot pulse output control register (ospc) (see table 9-5 ). when to0, to1 signals are output to a pin, the relevant pin must be in control mode in the port 3 mode register (pmc3). 237 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 table 9-5. timer output (to0/to1) operations toc ospc crc0 to1 to0 ento1 alv1 ento0 alv0 os1 os0 mod1 mod0 clr01 0 0/1 0 0/1 high/low level fixed high/low level fixed 0 0/1 1 0/1 000 high/low level fixed toggle output (active-low/high) 0 0/1 1 0/1 0010 high/low level fixed pwm output (active-high/low) 0 0/1 1 0/1 0100 high/low level fixed pwm output (active-high/low) 0 0/1 1 0/1 0111 high/low level fixed ppg output (active-high/low) 0 0/1 1 0/1 1 high/low level fixed one-shot pulse output (active-low/high) 1 0/1 0 0/1 0 0 toggle output (active-low/high) high/low level fixed 1 0/1 0 0/1 0 1 0 0 pwm output (active-high/low) high/low level fixed 1 0/1 0 0/1 0 11 toggle output (active-low/high) high/low level fixed 1 0/1 0 0/1 1 one-shot pulse output (active-low/high) high/low level fixed 10/110/10000 toggle output (active-low/high) toggle output (active-low/high) 10/110/100010 toggle output (active-low/high) pwm output (active-high/low) 10/110/100100 pwm output (active-high/low) pwm output (active-high/low) 10/110/100111 toggle output (active-low/high) ppg output (active-high/low) 1 0/1 1 0/1 0 1 0 toggle output (active-low/high) one-shot pulse output (active-low/high) 10/110/101100 pwm output (active-high/low) one-shot pulse output (active-low/high) 10/110/101111 toggle output (active-low/high) one-shot pulse output (active-low/high) 10/110/11000 one-shot pulse output (active-low/high) toggle output (active-low/high) 10/110/110010 one-shot pulse output (active-low/high) pwm output (active-high/low) 10/110/110100 one-shot pulse output (active-low/high) pwm output (active-high/low) 10/110/110111 one-shot pulse output (active-low/high) ppg output (active-high/low) 1 0/1 1 0/1 1 1 one-shot pulse output (active-low/high) one-shot pulse output (active-low/high) remarks 1. in the alvn (n = 0, 1) columns, the figures on the left and right of the slash (/) correspond to the items on the left and ri ght of the slash in the ton (n = 0, 1) columns. 2. the mark indicates that the operation is the same for either 0 or 1, but some prohibited combinations are included (see figure 9-4 ). 3. use with combinations not shown in this table is prohibited. 238 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.7.1 basic operation setting (to 1) the enton (n = 0, 1) bit of the timer output control register (toc) enables timer output (ton: n = 0, 1) to be varied at a timing in accordance with the settings of mod0, mod1, and clr01 bits of capture/compare control register 0 (crc0) and the one-shot pulse output control register (ospc). clearing (to 0) enton sets the ton to a fixed level. the fixed level is determined by the alvn (n = 0, 1) bit of the toc. the level is high when alvn is 0, and low when 1. 9.7.2 toggle output toggle output is an operation mode in which the output level is inverted each time the compare register (cr00/cr01) value coincides with the timer counter 0 (tm0) value. the output level of timer output (to0) is inverted by a match between cr00 and tm0, and the output level of to1 is inverted by a match between cr01 and tm0. when timer/event counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0), the inactive level (alvn: n = 0, 1) is output. figure 9-16. toggle output operation ento0 tm0 count value 0h ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh cr00 value cr01 value ffffh to0 output (alv0 = 1) ento1 instruction execution instruction execution instruction execution instruction execution to1 output (alv1 = 0) 239 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 table 9-6. to0, to1 toggle output (f xx = 12.58 mhz) count clock minimum pulse width maximum interval time f xx /4 0.32 m s 0.02 s f xx /8 0.64 m s 0.04 s f xx /16 1.27 m s 0.08 s f xx /32 2.54 m s 0.17 s f xx /64 5.09 m s 0.33 s f xx /128 10.17 m s 0.67 s f xx /256 20.35 m s 1.33 s f xx /512 40.70 m s 2.67 s f xx /1,024 81.40 m s 5.33 s 240 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.7.3 pwm output (1) basic operation of pwm output in this mode, a pwm signal with the period in which timer counter 0 (tm0) reaches a full count used as one cycle is output. the timer output (to0) pulse width is determined by the value of compare register (cr00), and the timer output (to1) pulse width is determined by the value of compare register (cr01). when this function is used, the clr01 bit of capture/compare control register 0 (crc0) must be set to 0. the pulse cycle and pulse width are as shown below. ? pwm cycle = 65,536 x/f xx ? pwm pulse width = cr0n x/f xx note ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 note 0 cannot be set in the cr0n. ? duty = pwm pulse width = cr0n pwm cycle 65,536 remark n = 0, 1 figure 9-17. pwm pulse output remark alv0 = 0 table 9-7. to0, to1 pwm cycle (f xx = 12.58 mhz) count clock minimum pulse width [ m s] pwm cycle [s] pwm frequency [hz] f xx /4 0.32 0.02 47.6 f xx /8 0.64 0.04 23.8 f xx /16 1.27 0.08 12.0 f xx /32 2.54 0.17 6.0 f xx /64 5.09 0.33 3.0 f xx /128 10.17 0.67 1.5 f xx /256 20.35 1.33 0.7 f xx /512 40.70 2.67 0.4 f xx /1,024 81.40 5.33 0.2 cr00 interrupt timer count 0h ffffh count start cr00 ffffh ffffh pulse width pulse cycle to0 cr00 pulse width pulse cycle 241 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-18 shows an example of 2-channel pwm output, and figure 9-19 shows the operation of the case where ffffh is set in the cr00. figure 9-18. example of pwm output using tm0 remark alv0 = 0, alv1 = 0 figure 9-19. example of pwm output when cr00 = ffffh remarks 1. alv0 = 0 2. t = x/f xx (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) tm0 count value 0h cr00 ffffh intc00 cr01 cr00 ffffh cr01 cr00 ffffh intc01 to0 to1 tm0 count value ffffh intc00 0 1 2 fffeh ffffh 0 1 2 fffeh count clock cycle t ffffh 0 pulse width t duty = 100 = 99.998 (%) . . 65,535 65,536 pulse cycle = 65,536t to0 ovf flag 242 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (2) rewriting compare registers (cr00, cr01) the output level of the timer output (ton: n = 0, 1) does not change even if the cr0n (n = 0, 1) value matches the timer counter 0 (tm0) value more than once during one pwm output cycle. figure 9-20. example of compare register (cr00) rewrite cr00 to0 tm0 count value 0h t1 t2 t1 t2 t1 t2 cr00 and tm0 values match, but to0 does not change here. cr00 rewrite ffffh t1 ffffh 243 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 if a value smaller than that of the tm0 is set as the cr0n value, a 100% duty pwm signal will be output. cr0n rewriting should be performed by the interrupt due to a match between tm0 and the cr0n on which the rewrite is performed. figure 9-21. example of 100% duty with pwm output remark alv0 = 0 cr00 to0 tm0 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm0 value n3 is written to cr00, the duty of this period will be 100%. ffffh ffffh ffffh ffffh n2 n2 n2 n1 244 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (3) stopping pwm output if timer/event counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0) during pwm signal output, the active level is output. figure 9-22. when timer/event counter 0 is stopped during pwm signal output remark alv0 = 1 caution the output level of the ton (n = 0, 1) pin when timer output is disabled (enton = 0: n = 0, 1) is the inverse of the value set in alvn (n = 0, 1) bit. caution is therefore required as the active level is output when timer output is disabled when the pwm output function has been selected. to0 tm0 count value 0h cr00 ffffh ffffh cr00 245 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.7.4 ppg output (1) basic operation of ppg output this function outputs a square-wave with the time determined by compare register cr01 value as one cycle, and the time determined by compare register cr00 value as the pulse width. the pwm cycle output by the pwm is made variable. this signal can only be output from the timer output (to0). when this function is used, the clr01 bit of capture/compare control register 0 (crc0) must be set to 1. the pulse cycle and pulse width are as shown below. ? ppg cycle = (cr01 + 1) x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 ? ppg pulse width = cr00 x/f xx where 1 cr00 cr01 ? duty = ppg pulse width = cr00 ppg cycle cr01 + 1 figure 9-23 shows an example of ppg output using timer counter 0 (tm0), figure 9-24 shows an example of the case where cr00 = cr01. figure 9-23. example of ppg output using tm0 remark alv0 = 0, alv1 = 0 intc01 tm0 count value 0h cr00 cr00 cr00 cr01 cr01 cr01 intc00 to0 (ppg output) pulse width count start pulse cycle to1 (timer output) 246 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 table 9-8. to0 ppg output (f xx = 12.58 mhz) count clock minimum pulse width [ m s] ppg cycle ppg frequency f xx /4 0.32 0.64 m s to 20.84 ms 1572 khz to 48.0 hz f xx /8 0.64 1.27 m s to 41.68 ms 786 khz to 24.0 hz f xx /16 1.27 2.54 m s to 83.35 ms 393 khz to 12.0 hz f xx /32 2.54 5.09 m s to 166.71 ms 197 khz to 6.0 hz f xx /64 5.09 10.17 m s to 333.41 ms 98.3 khz to 3.0 hz f xx /128 10.17 20.35 m s to 666.82 ms 49.1 khz to 1.5 hz f xx /256 20.35 40.70 m s to 1.33 s 24.6 khz to 0.7 hz f xx /512 40.70 81.40 m s to 2.67 s 12.3 khz to 0.4 hz f xx /1,024 81.40 162.80 m s to 5.33 s 6.1 khz to 0.2 hz figure 9-24. example of ppg output when cr00 = cr01 remark alv0 = 0 t = x/f xx (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) tm0 count value n intc00 0 1 2 n-1 n 0 1 2 n-1 count cycle t n 0 pulse width = nt pulse cycle = (n+1) t intc01 to0 247 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (2) rewriting compare register (cr00) the output level of the timer output (to0) does not change even if the cr00 value matches the timer counter 0 (tm0) value more than once during one ppg output cycle. figure 9-25. example of compare register (cr00) rewrite remark alv0 = 1 cr00 to0 tm0 count value 0h t1 t2 t1 t2 cr00 and tm0 values match, but to0 does not change here. cr00 rewrite cr01 t1 cr01 t1 t2 248 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 if a value equal to or less than the tm0 value is written to cr00 before the compare register (cr00) and timer counter 0 (tm0) match, the duty of the ppg cycle will be 100%. cr00 rewriting should be performed by the interrupt due to a match between tm0 and cr00. figure 9-26. example of 100% duty with ppg output remark alv0 = 0 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr00 cannot be rewritten by interrupt processing that is performed on coincidence between tm0 and cr00. use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cr00 to0 tm0 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm0 value n3 is written to cr00 here, the duty of this period will be 100%. cr01 cr01 cr01 cr01 n2 n2 n2 n1 249 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (3) rewriting compare register (cr01) if the current value of the cr01 is changed to a smaller value, and the cr01 value is made smaller than the timer counter 0 (tm0) value, the ppg cycle at that time will be extended to the time equivalent to a full-count by tm0. if cr01 is rewritten after the compare register (cr00) and tm0 match, the output level at this time will be the inactive level until tm0 overflows and becomes 0, and will then return to normal ppg output. if cr01 is rewritten before cr00 and tm0 match, the active level will be output until cr00 and tm0 match. if cr00 and tm0 match before tm0 overflows and becomes 0, the inactive level is output at that point. when tm0 overflows and becomes 0, the active level will be output, and normal ppg output will be restored. cr01 rewriting should be performed by the interrupt due to a match between tm0 and cr01, etc. figure 9-27. example of extended ppg output cycle remark alv0 = 1 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr01 cannot be rewritten by interrupt processing that is performed on coincidence between the timer counter 0 (tm0) and compare register (cr01). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cr00 to0 tm0 count value 0h n3 n4 n2 if cr00 and tm0 match, to0 enters the inactive level. otherwise, it remains at the active level. full count value n4 n2 n3 n1 n2 cr01 n5 n3 n1 n1 n1 when value n2 which is smaller than the tm0 value n5 is written to cr01 here, the ppg cycle is extended. 250 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (4) stopping ppg output if timer/event counter 0 is stopped by clearing (to 0) the ce0 bit of the timer control register 0 (tmc0) during ppg signal output, the active level is output irrespective of the output level at the time it was stopped. figure 9-28. when timer/event counter 0 is stopped during ppg signal output caution the output level of the ton (n = 0, 1) pin when timer output is disabled (enton = 0: n = 0, 1) is the inverse of the value set in alvn (n = 0, 1) bit. caution is therefore required as the active level is output when timer output is disabled when the ppg output function has been selected. to0 tm0 count value 0h cr00 cr01 cr01 cr00 251 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.7.5 software triggered one-shot pulse output in the software triggered one-shot pulse output mode, a one-shot pulse is output by software. when the stn (n = 0, 1) bit of the one-shot pulse output control register (ospc) is set (1), timer output pin (ton: n = 0, 1) is set to the active level. ton then remains at the active level until the timer counter 0 (tm0) value and the compare registe r (cr0n: n = 0, 1) value match, at which point ton changes to the inactive level. ton then remains at the inactive level until the stn bit is set again. ton can also be set to the inactive level by setting (to 1) the rtn bit (n = 0, 1), and in the same way, ton remains at the inactive level until the stn bit is set again. to0 and to1 can be controlled independently. an example of software triggered one-shot pulse output is shown in figure 9-29. when timer/event counter 0 is stopped by clearing (to 0) the ce0 bit of the tmc0, the level at the time was stopped is retained . figure 9-29. example of software triggered one-shot pulse output caution 1 should not be written to stn and rtn simultaneously. 0h ffffh count start software trigger st0 intc00 alv0 to0 active period ? inactive level output 252 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8 examples of use 9.8.1 operation as interval timer (1) when timer counter 0 (tm0) is made free-running and a fixed value is added to the compare register (cr0n: n = 0, 1) in the interrupt service routine, tm0 operates as an interval timer with the added fixed value as the cycle (see figure 9-30 ). this interval timer can count within the range shown in table 9-1 (internal system clock f xx = 32 mhz). since tm0 has two compare registers, two interval timers with different cycles can be constructed. the control register settings are shown in figure 9-31, the setting procedure in figure 9-32, and the processing in the interru pt service routine in figure 9-33. figure 9-30. interval timer operation (1) timing remark interval = n 4/f xx , 1 n ffffh mod (2n) intc00 interrupt request tm0 count value 0h ffffh compare register (cr00) n timer start mod (3n) mod (4n) ffffh n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program 253 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-31. control register settings for interval timer operation (1) capture/compare control register 0 (crc0) figure 9-32. interval timer operation (1) setting procedure figure 9-33. interval timer operation (1) interrupt request servicing 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs interval timer (1) set count value in cr00 cr00 ? n intc00 interrupt ; set 1 in bit 3 of tmc0 set crc0 crc0 ? 10h start count ce0 ? 1 intc00 interrupt calculate timer value that will generate next interrupt cr00 ? cr00+n other interrupt service program reti 254 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8.2 operation as interval timer (2) tm0 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 9-34 ). this interval timer can count within the range shown in table 9-1 (internal system clock f xx = 32 mhz). the control register settings are shown in figure 9-35, and the setting procedure in figure 9-36. figure 9-34. interval timer operation (2) timing remark interval = (n + 1) 4/f xx , 0 n ffffh n compare register (cr01) intc01 interrupt request tm0 count value 0h n n count start clear clear interrupt acknowledged interrupt acknowledged interval interval 255 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-35. control register settings for interval timer operation (2) capture/compare control register 0 (crc0) figure 9-36. interval timer operation (2) setting procedure 7 0 crc0 6 0 5 0 4 1 3 1 2 0 1 0 0 0 tm0 cleared by match of cr01 & tm0 contents to0 & to1 both toggle outputs interval timer (2) set count value in cr01 cr01 ? n intc01 interrupt ; set 1 in bit 3 of tmc0 set crc0 crc0 ? 18h start count ce0 ? 1 256 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp3) is measured. both the high-level and low-level widths of pulses input to the intp3 pin must be at least 3 system clocks (0.24 m s: f clk = 12.58 mhz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. this pulse width measurement can be performed within the range shown in table 9-3 (f clk = 12.58 mhz). as shown in figure 9-37, the timer counter 0 (tm0) value being counted is fetched into the capture register (cr02) in synchronization with a valid edge (specified as both rising and falling edges) in the intp3 pin input, and held there. the pul se width is obtained from the product of the difference between the tm0 count value (dn) fetched into and held in the cr02 on detection of the nth valid edge and the count value (d n-1 ) fetched and held on detection of valid edge n-1, and the number of count clocks (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). the control register settings are shown in figure 9-38, and the setting procedure in figure 9-39. figure 9-37. pulse width measurement timing remark dn: tm0 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 d1 intp3 external input signal intp3 interrupt request tm0 count value 0h ffffh capture register (cr02) ovf0 d0 d0 d1 count start ffffh d2 d2 d3 capture capture capture capture (d1-d0) 8/f xx (10000h-d1+ d2) 8/f xx (d3-d2) 8/f xx d3 - cleared by software 257 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-38. control register settings for pulse width measurement (a) capture/compare control register 0 (crc0) (b) external interrupt mode register 1 (intm1) figure 9-39. pulse width measurement setting procedure 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs pulse width measurement set crc0 crc0 ? 10h set intm1, set mk0l initialize capture value buffer memory x 0 ? 0 start count ce0 ? 1 enable interrupt ; specify both edges as intp3 input valid edges, release interrupt masking intp3 interrupt ; set 1 in bit 3 of tmc0 7 0 intm1 6 0 5 4 3 2 : don? care 1 1 0 1 both rising & falling edges specified as intp3 input valid edges 258 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-40. interrupt request servicing that calculates pulse width intp3 interrupt calculate pulse width y n = cr02 ?x n store capture value in memory x n+1 ? cr02 reti 259 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8.4 operation as pwm output in pwm output, pulses with the duty ratio determined by the value set in the compare register (cr0n: n = 0, 1) are output (see figure 9-41 ). this pwm output duty ratio can be varied in the range 1/65,536 to 65,535/65,536 in 1/65,536 units. since timer counter 0 (tm0) has two compare registers, two different pwm signals can be output. the control register settings are shown in figure 9-42, the setting procedure in figure 9-43, and the procedure for varying the duty in figure 9-44. figure 9-41. example of timer/event counter 0 pwm signal output figure 9-42. control register settings for pwm output operation (a) capture/compare control register 0 (crc0) (b) timer output control register (toc) (c) port 3 mode control register (pmc3) to0 (when active-low) tm0 count value 0h timer start ffffh cr00 ffffh cr00 ffffh cr00 7 1 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both pwm outputs 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-low pwm signal output to0 pwm output enabled 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output 260 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-43. pwm output setting procedure pwm output set crc0 crc0 ? 90h set toc set p34 pin to control mode pmc3.4 ? 1 set initial value in cr00, cr01 ; set bit 3 of tmc0 start count ce0 ? 1 261 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-44. changing pwm output duty duty change processing set duty value in cr00 disable intc00 interrupts cmk00 ? 1 reti ; set bit 4 of mk0l duty change preprocessing clear intc00 interrupt request flag cif00 ? 0 enable intc00 interrupts cmk00 ? 0 intc00 interrupt ; clear bit 4 of if0l ; clear bit 4 of mk0l 262 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8.5 operation as ppg output in ppg output, pulses with the cycle and duty ratio determined by the values set in the compare registers (cr0n: n = 0, 1) are output (see figure 9-45 ). the control register settings are shown in figure 9-46, the setting procedure in figure 9-47, and the procedure for varying the duty in figure 9-48. figure 9-45. example of timer/event counter 0 ppg signal output figure 9-46. control register settings for ppg output operation (a) capture/compare control register 0 (crc0) (b) timer output control register (toc) (c) port 3 mode control register (pmc3) to0 (when active-low) tm0 count value 0h timer start cr01 cr00 cr01 cr00 cr01 cr00 7 1 crc0 6 1 5 0 4 1 3 1 2 0 1 0 0 0 tm0 cleared by match of tm0 & cr01 to0 = ppg output 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-low ppg signal output to0 ppg output enabled 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output 263 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-47. ppg output setting procedure ppg output set crc0 crc0 ? d8h set toc set p34 pin to control mode pmc3.4 ? 1 set cycle in cr01 set duty in cr00 ; set bit 3 of tmc0 start count ce0 ? 1 264 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-48. changing ppg output duty duty change preprocessing clear intc00 interrupt request flag cif00 ? 0 duty change processing set duty value in cr00 disable intc00 interrupts cmk00 ? 1 reti intc00 interrupt ; clear bit 4 of if0l ; clear bit 4 of mk0l ; set bit 4 of mk0l enable intc00 interrupts cmk00 ? 0 265 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.8.6 example of software triggered one-shot pulse output in the software triggered one-shot pulse output mode, a one-shot pulse is output in response to a trigger activated by software (see figure 9-49 ). the control register settings are shown in figure 9-50, and the setting procedure in figure 9-51. figure 9-49. example of timer/event counter 0 one-shot pulse output to0 tm0 count value 0h ffffh count start cr00 ffffh set trigger 266 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-50. control register settings for one-shot pulse output (a) one-shot pulse output control register (ospc) (b) capture/compare control register 0 (crc0) (c) timer output control register (toc) (d) port 3 mode control register (pmc3) 7 0 ospc 6 0 5 0 4 3 0 2 0 1 0 0 1 to0 = one-shot pulse output 7 0 crc0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm0 clearing disabled to0 & to1 both toggle outputs 7 toc 6 5 4 3 2 1 1 0 1 to0 = active-high one-shot pulse signal output to0 one-shot pulse output enabled 7 pmc3 6 5 4 1 3 2 1 0 p34 pin set as to0 output 267 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-51. one-shot pulse output setting procedure one-shot pulse output set ospc os0 ? 1 ; set bit 3 of tmc0 ; set to one-shot pulse output mode set crc0 crc0 ? 10h set p34 pin to control mode pmc 3.4 ? 1 start count ce0 ? 1 one-shot pulse output st0 ? 1 set pulse width in cr00 268 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 9.9 cautions (1) while timer/event counter 0 is operating (while the ce0 bit of the timer control register 0 (tmc0) is set), malfunctioning m ay occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contention the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following register s. ? prescaler mode register 0 (prm0) ? capture/compare control register 0 (crc0) ? timer output control register (toc) (2) if the contents of the compare register (cr0n: n = 0, 1) coincide with those of tm0 operation when an instruction that stops timer counter 0 (tm0) operation is executed, the counting operation of tm0 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm0, mask the interrupt in advance by using the interrupt mask register before stopping tm0. example program that may generate interrupt request program that does not generate interrupt request clr1 ce0 or mk0l, #30h or mk0l, #30h clr1 ce0 clr1 cif00 clr1 cif01 (3) up to 1 count clock is required after an operation to start timer/event counter 0 (ce0 ? 1) has been performed before timer/ event counter 0 actually starts (refer to figure 9-52 ). for example, when using timer/event counter 0 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 9-52. operation when counting is started ? interrupt request from timer/event counter 0 occurs between these instructions ? disables interrupt from timer/event counter 0 ? clears interrupt request flag for timer/event counter 0 count clock tm0 ce0 timing to start actual counting count start command (ce0 ? 1) by software 0 0 123 269 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 (4) while an instruction that writes data to the compare register (cr0n: n = 0, 1) is executed, coincidence between cr0n, to which the data is to be written, and timer counter 0 (tm0) is not detected. for example, if the contents of cr0n do not change before and after the writing, the interrupt request is not generated even if the value of tm0 coincides with the value of cr0n, nor does the timer output (ton: n = 0, 1) change. write data to cr0n when timer/event counter 0 is executing counting operation, in the timing that the contents of tm0 do not coincide with the value of cr0n before and after writing (e.g., immediately after an interrupt request has been generated because tm0 and cr0n have coincided). (5) coincidence between tm0 and compare register (cr0n: n = 0, 1) is detected only when tm0 is incremented. therefore, the interrupt request is not generated even if the same value as tm0 is written to cr0n, and the timer output (ton: n = 0, 1) does not change. (6) if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the cr0n cannot be rewritten by interrupt processing that is performed on coincidence between tm0 and the compare register (cr0n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (7) the output level of the ton (n = 0, 1) when the timer output is disabled (enton = 0: n = 0, 1) is the reverse value of the value set to the alvn (n = 0, 1) bit. note, therefore, that an active level is output when the timer output is disabled with t he pwm output function or ppg output function selected. (8) when timer/event counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 0 (tm0) alone (refer to figure 9-53 ), since the contents of tm0 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. to make a distinction, use the interrupt request flag of intp3, as shown in figure 9-54. figure 9-53. example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input intp3 tm0 0 1 2 0 cannot be distinguished count start 270 chapter 9 timer/event counter 0 preliminary users manual u13987ej1v0um00 figure 9-54. to distinguish whether one or no valid edge has been input with external event counter (a) processing on starting counting (b) processing on reading count value ; set ce3 to 1 ; clear pif3 to 0 clear intp3 interrupt request flag pif3 ? 0 start count ce3 ? 1 start count end number of input valid edges is set to ax register count value read read tm0 contents ax ? tm0 ax ? ax+1 end ax = 0? pif3 = 1? ; ; check tm0 value. if 0, check interrupt request flag. check pif3 contents. if 1, valid edge is input. yes no yes no 271 preliminary users manual u13987ej1v0um00 chapter 10 timer/event counter 1 10.1 functions timer/event counter 1 is 16-bit or 8-bit timer/event counter. in addition to its basic functions of interval timer, pulse width measurement, and event counter, timer/event counter 1 can be used as a real-time output port output trigger generation timer. (1) interval timer generates internal interrupts at preset intervals. table 10-1. timer/event counter 1 intervals minimum interval maximum interval resolution 4/f xx 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz 272 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (2) pulse width measurement detects the pulse width of the signal input to the external interrupt request input pin intp0. table 10-2. timer/event counter 1 pulse width measurement range measurable pulse width note resolution 4/f xx to 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx to 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx to 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx to 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx to 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx to 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx to 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx to 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz note the minimum pulse width that can be measured changes depending on the sampling clock selected by the sampling clock select register (scs0). the minimum pulse width that can be measured is the value in the table below or above, whichever is greater. at f xx = 12.58 mhz operation sampling clock minimum pulse width f clk f clk = f xx 3/f clk = 3/f xx (0.24 m s) f clk = f xx /2 3/f clk = 6/f xx (0.48 m s) f clk = f xx /4 3/f clk = 12/f xx (0.95 m s) f clk = f xx /8 3/f clk = 24/f xx (1.19 m s) f xx /32 96/f xx (7.63 m s) f xx /64 192/f xx (15.26 m s) f xx /128 384/f xx (30.52 m s) 273 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (3) external event counter counts the clock pulses input from the external interrupt request input pin (intp0). the clocks that can be input to timer/event counter 1 are shown in table 10-3. table 10-3. timer/event counter 1 pulse width measurement time ( ): when f clk = 12.58 mhz and f xx = 12.58 mhz sampling clock note when counting one edge when counting both edges f clk maximum frequency f clk /6 (2.10 mhz) f clk /6 (2.10 mhz) minimum pulse width 3/f clk (0.24 m s) 3/f clk (0.24 m s) (high and low levels) f xx /32 maximum frequency f xx /192 (65.52 khz) f xx /192 (65.52 khz) minimum pulse width 96/f xx (7.63 m s) 96/f xx (7.63 m s) (high and low levels) f xx /64 maximum frequency f xx /384 (32.76 khz) f xx /384 (32.76 khz) minimum pulse width 192/f xx (15.26 m s) 192/f xx (15.26 m s) (high and low levels) f xx /128 maximum frequency f xx /768 (16.38 khz) f xx /768 (16.38 khz) minimum pulse width 384/f xx (30.52 m s) 384/f xx (30.52 m s) (high and low levels) note selected by means of the sampling clock selection register (scs0) 10.2 configuration timer/event counter 1 consists of the following registers: ? timer counter (tm1/tm1w) 1 ? compare register (cr10/cr10w) 1 ? capture/compare register (cr11/cr11w) 1 ? capture register (cr12/cr12w) 1 the block diagram of timer/event counter 1 is shown in figure 10-1. 274 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-1. timer/event counter 1 block diagram internal bus 1/8 8/16 8 external interrupt mode register 0 (intm0) es31 es30 p21/intp0 edge detection circuit 16 16 8/16 capture/compare register (cr11/cr11w) 16 8/16 16 16 16 8/16 8 selector prescaler f xx /1,024 f xx /512 f xx /256 f xx /128 f xx f xx /64 f xx /32 f xx /16 f xx /8 prescaler mode register 1 (prm1) prs23 prs22 prs21 prs20 capture register (cr12/cr12w) timer counter 1 (tm1/tm1w) timer control register 1 (tmc1) ovf1 ce1 1/8 internal bus bw1 overflow cm selector 8 8 8 8 intp0 match match match match reset clr11 cm clr10 capture/compare control register 1 (crc1) intc10 real-time output port intc11 compare register (cr10/cr10w) selector capture trigger capture trigger clear f xx /4 275 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (1) timer counter 1 (tm1/tm1w) tm1/tm1w is a timer counter that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 1 (prm1). the count operation can be specified to stop or enable, and an 8-bit operation mode (tm1)/16-bit operation mode (tm1w) can be selected, by means of timer control register 1 (tmc1). tm1/tm1w can be read only with an 8/16-bit manipulation instruction. when reset is input, tm1/tm1w is cleared to 00h and the count is stopped. (2) compare register (cr10/cr10w) cr10/cr10w is an 8/16-bit register that holds the value that determines the interval timer operation cycle. if the contents of the cr10/cr10w match the values of tm1/tm1w, an interrupt request (intc10) is generated. this match signal is also a real-time output port trigger signal. also, the count value can be cleared by a match. this compare register operates as cr10 in the 8-bit operation mode, and cr10w in the 16-bit operation mode. cr10/cr10w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (3) capture/compare register (cr11/cr11w) cr11/cr11w is an 8/16-bit register that can be specified as a compare register for detecting a match with the tm1/tm1w count value or a capture register for capturing the tm1/tm1w count value according to the setting of capture/compare control register 1 (crc1). this capture/compare register operates as cr11 in the 8-bit operation mode, and cr11w in the 16-bit operation mode. cr11/cr11w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (a) when specified as compare register cr11/cr11w functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. an interrupt request (intc11) is generated by a match between the contents of cr11/cr11w and the contents of tm1/tm1w. also, the count value can be cleared by a match. this match signal is also a real-time output port trigger signal. (b) when specified as capture register cr11/cr11w functions as an 8/16-bit register that captures the contents of tm1/tm1w in synchronization with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp0). the contents of the cr11/cr11w are retained until the next capture trigger is generated. tm1/tm1w can be cleared after a capture operation. (4) capture register (cr12/cr12w) cr12/cr12w is an 8/16-bit register that captures the contents of tm1/tm1w. the capture operation is synchronized with the input of a valid edge (capture trigger) on the external interrupt request input pin (intp0). the contents of the cr12/cr12w are retained until the next capture trigger is generated. this capture/compare register operates as cr12 in the 8-bit operation mode, and cr12w in the 16-bit operation mode. cr12/cr12w can be read only with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. 276 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (5) edge detection circuit the edge detection circuit detects an external input valid edge. when the valid edge set by external interrupt mode register 0 (intm0) is detected in the intp0 pin input, the external interrupt request (intp0), a capture trigger and a count clock of the external event are generated (see figure 22-1 for details of the intm0). (6) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by this prescaler is selected by the selector, and is used as the count clock by the timer counter 1 (tm1/tm1w) to perform count operations. (7) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 1 (tm1/tm1w). 277 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.3 timer/event counter 1 control registers (1) timer control register 1 (tmc1) tmc1 controls the timer/event counter 1, tm1/tm1w, count operation by the low-order 4 bits (the high-order 4 bits control the count operation of timer/event counter 2 tm2/tm2w). tmc1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of tmc1 is shown in figure 10-2. reset input clears tmc1 to 00h. figure 10-2. timer control register 1 (tmc1) format remark the ovf1 bit is reset by software only. 7 ce2 tmc1 6 ovf2 5 cmd2 4 bw2 3 ce1 2 ovf1 1 0 0 bw1 address after reset r/w r/w 00h 0ff5fh bw1 timer/event counter 1 bit length specification 8-bit operating mode 16-bit operating mode 1 0 ovf1 tm1/tm1w overflow flag no overflow overflow note 1 0 ce1 tm1/tm1w count operation control count operation stopped with count cleared count operation enabled 1 0 countrols count operation of timer/event counter 2 (tm2/tm2w) (see figure 11-2 ). note in 8-bit operating mode: count up from ffh to 00h in 16-b it operating mode: count up from ffffh to 0000h 278 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (2) prescaler mode register 1 (prm1) in prm1, the count clock to timer/event counter 1 tm1/tm1w is specified by the low-order 4 bits (the high-order 4 bits specify the count clock to timer/event counter 2 tm2/tm2w). prm1 can be read or written to with an 8-bit manipulation instruction. the format of prm1 is shown in figure 10-3. reset input sets prm1 to 11h. figure 10-3. prescaler mode register 1 (prm1) format remark f xx : x1 input frequency or oscillation frequency prs23 prs22 prs21 prs20 prs13 prs12 prs11 prs10 76543210 prm1 0ff5eh address 11h after reset r/w r/w prs13 0 0 0 0 0 0 0 0 1 1 1 specifies count clock to tm2/tm2w of timer/event counter 2 (see figure 11-3 ). prs12 0 0 0 0 1 1 1 1 0 0 1 prs11 0 0 1 1 0 0 1 1 0 0 1 prs10 0 1 0 1 0 1 0 1 0 1 1 timer/event counter 1 (tm1/ tm1w) count clock specification count clock [hz] specification setting prohibited f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock (intp0) setting prohibited 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 162.80 other than the above (f xx = 12.58 mhz) resolution [ s] m 279 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (3) capture/compare control register 1 (crc1) crc1 specifies the operation of the capture/compare register (cr11/cr11w) and the enabling condition for a timer counter 1 (tm1/tm1w) clear operation. crc1 can be read or written to with an 8-bit manipulation instruction. the format of crc1 is shown in figure 10-4. reset input clears crc1 to 00h. figure 10-4. capture/compare control register 1 (crc1) format 7 0 crc1 6 0 5 0 4 0 3 clr11 2 cm 1 clr10 0 0 address after reset r/w r/w 00h 0ff32h clr10 tm1 clear operation when tm1 = cr10 tm1w clear operation when tm1w = cr10w disabled enabled 1 0 clr11 cm compare operation cr11/cr11w operation specificaton tm1/tm1w clearance operation disabled enabled (when tm1 & cr11 or tm1w & cr11w contents match) 1 0 0 0 capture operation disabled enabled (when tm1 contents are captured in cr11 or when tm1w contents are captured in cr11w) 1 0 1 1 280 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.4 timer counter 1 (tm1) operation 10.4.1 basic operation 8-bit operation mode/16-bit operation mode control can be performed for timer/event counter 1 by means of bit 0 (bw1) of timer control register 1 (tmc1) note . in the timer/event counter 1 count operation, the count-up is performed using the count clock specified by the low-order 4 bits of prescaler mode register 1 (prm1). count operation enabling/disabling is controlled by bit 3 (ce1) of tmc1 (timer/event counter 1 operation control is performed by the low-order 4 bits of the tmc1). when the ce1 bit is set (to 1) by software, the contents of tm1 are cleared to 0h on the first count clock, and then the count-up operation is performed. when the ce1 bit is cleared (to 0), tm1 becomes 0h immediately, and capture operations and match signal generation are stopped. if the ce1 bit is set (to 1) again when it is already set (to 1), tm1 continues the count operation without being cleared. if the count clock is input when tm1 is ffh in 8-bit operation mode and when tm1w is ffffh in 16-bit operation mode, tm1/ tm1w becomes 0h. in this case, ovf1 bit is set. ovf1 bit is cleared by software only. the count operation is continued. when reset is input, tm1 is cleared to 0h, and the count operation is stopped. note unless otherwise specified, the functions of timer counter 1 in the 8-bit operation mode are described hereafter. in the 16-bit operation mode, tm1, cr10, and cr11 operate as tm1w, cr10w, and cr11w respectively. 281 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-5. basic operation in 8-bit operation mode (bw1 = 0) (a) count started ? count disabled ? count started (b) when 1 is written to the ce1 bit again after the count starts (c) operation when tm1 = ffh tm1 ce1 0h 0h 1h 2h 0fh 10h 11h 0h 1h 0h count started ce1 ? 1 count stopped ce1 ? 0 count started ce1 ? 1 count clock tm1 ce1 count started ce1 ? 1 rewrite ce1 ? 1 count clock 0h 0h 1h 2h 3h 4h 5h 6h tm1 ovf1 feh ffh 0h cleared by software ovf1 ? 0 count clock 1h 282 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-6. basic operation in 16-bit operation mode (bw1 = 1) (a) count started ? count disabled ? count started (b) when 1 is written to the ce1 bit again after the count starts (c) operation when tm1w = ffffh tm1w ce1 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce1 ? 1 count stopped ce1 ? 0 count started ce1 ? 1 count clock tm1w ce1 count started ce1 ? 1 rewrite ce1 ? 1 count clock 0h 0h 1h 2h 3h 4h 5h 6h tm1w ovf1 fffeh ffffh 0h cleared by software ovf1 ? 0 count clock 1h 283 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.4.2 clear operation (1) clear operation after match with compare register and after capture operation timer counter 1 (tm1) can be cleared automatically after a match with the compare register (cr1n: n = 0, 1) and a capture operation. when a clearance source arises, tm1 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 10-7. tm1 clearance by match with compare register (cr10, cr11) figure 10-8. tm1 clearance after capture operation (2) clear operation by ce1 bit of timer control register 1 (tmc1) timer counter 1 (tm1) is also cleared when the ce1 bit of tmc1 is cleared (to 0) by software. the clear operation is performed immediately after the clearance (to 0) of the ce1 bit. tm1 compare register (cr1n) cleared here count clock n tm1 and cr1n match n01 n-1 tm1 intp0 tm1 is captured in cr11 here cleared here count clock n01 2 n-1 284 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-9. clear operation when ce1 bit is cleared (to 0) (a) basic operation (b) restart before count clock is input after clearance (c) restart after count clock is input after clearance tm1 ce1 n count clock n-1 0 tm1 ce1 n count clock n-1 0 0 1 2 if the ce1 bit is set (to 1) before this count clock, this count clock starts counting from 0. tm1 ce1 n0 count clock n-1 0 0 1 if the ce1 bit is set (to 1) from this count clock onward, the count clock starts counting from 0 after the ce1 bit is set (to 1). 285 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.5 external event counter function timer/event counter 1 can count clock pulses input from the external interrupt request input pin (intp0) pin. no special selection method is needed for the external event counter operation mode. when the timer counter 1 (tm1) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 1 (prm1), tm1 oper ates as an external event counter. the maximum frequency of the external clock pulse that can be counted by the external event counter is determined by the sampling clock select register (scs0) as shown in table 10-4. the maximum frequency is the same when both the edges of the intp0 input are counted and when only one edge is counted. the pulse width of the intp0 input must be three or more sampling clocks selected by scs0, regardless of whether the level is high or low. if the width is shorter than this, the pulse may not be counted. figure 10-10 shows the timing of the external event count by timer/event counter 1. table 10-4. maximum input frequency and minimum input pulse width that can be counted as events ( ): f xx = 12.58 mhz, f clk = 12.58 mhz sampling clock selected by scs0 maximum input frequency minimum pulse width f clk f clk /6 (2.10 mhz) 3/f clk (0.24 m s) f xx /32 f xx /192 (65.52 khz) 96/f xx (7.63 m s) f xx /64 f xx /384 (32.76 khz) 192/f xx (15.26 m s) f xx /128 f xx /768 (16.38 khz) 384/f xx (30.52 m s) figure 10-10. timer/event counter 1 external event count timing (1/2) (1) counting one edge (maximum frequency = f clk /6) remarks 1. ici: intp0 input signal after passing through edge detection circuit 2. f smp is selected by the sampling clock selection register (scs0). ici tm1 intp0 dn dn+1 dn+2 dn+3 3/f smp (min.) 3/f smp (min.) 6/f smp (min.) 2-3/f smp 286 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-10. timer/event counter 1 external event count timing (2/2) (2) counting both edges (maximum frequency = f clk /6) remarks 1. ici: intp0 input signal after passing through edge detection circuit 2. f smp is selected by the sampling clock selection register (scs0). the tm1 count operation is controlled by the ce1 bit of the timer control register 1 (tmc1) in the same way as with the basic operation. when the ce1 bit is set (to 1) by software, the contents of tm1 are set to 0h and the count-up operation is started on the initial count clock. when the ce1 bit is cleared (to 0) by software during a tm1 count operation, the contents of tm1 are set to 0h immediately and the stopped state is entered. the tm1 count operation is not affected if the ce1 bit is set (to 1) by software again when it is already set (to 1). caution when timer/event counter 1 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using the timer counter 1 (tm1) alone (see figure 10-11), since the contents of tm1 are 0 in both cases. if it is necessary to make this distinction, the intp0 interrupt request flag should be used. an example is shown in figure 10-12. figure 10-11. example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input ici tm1 intp0 dn+1 dn dn+2 dn+3 dn+4 dn+5 3/f smp (min.) 3/f smp (min.) 6/f smp (min.) 2-3/f smp tm1 0 intp0 1 2 0 count start no distinction made 287 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-12. to distinguish whether one or no valid edge has been input with external event counter (a) processing when count is started (b) processing when count value is read clear intp0 interrupt request flag pif0 ? 0 ; clear pif0 to 0 end start count ; set ce1 to 1 start count ce1 ? 1 read tm1 contents a ? tm1 ; check pif0 contents if 1, there is a valid edge ; number of input valid edges is set in a register ; check tm1 value if 0, check interrupt request flag end pif0 = 1? yes yes no no count value read a = 0? a ? a+1 288 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.6 compare register and capture/compare register operation 10.6.1 compare operations timer/event counter 1 performs compare operations in which the value set in a compare register (cr10), capture/compare register (cr11), specified for compare operation is compared with the timer counter 1 (tm1) count value. if the count value of tm1 matches the preset value of the cr10, or the cr11 as the result of the count operation, an interrupt request signal (intc10 or intc11) is generated. after a match with the cr10 or cr11 value, the tm1 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr10 or cr11. figure 10-13. compare operation in 8-bit operation mode remark clr10 = 0, clr11 = 0, cm = 0, bw1 = 0 intc10 interrupt request tm1 count value 0h count start ce1 ? 1 cr10 value ovf1 intc11 interrupt request ffh cr11 value match match 289 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-14. compare operation in 16-bit operation mode remark clr10 = 0, clr11 = 0, bw1 = 1 figure 10-15. tm1 clearance after match detection intc10 interrupt request tm1w count value 0h ffffh count start ce1 ? 1 cr10w value cr11w value ffffh cr10w value cr11w value intc11 interrupt request ovf1 cleared by software match match match match intc10 interrupt request tm1 count value 0h cr11 count start ce ? 1 clr10 ? 0 clr11 ? 1 ce1 ? 0 clr10 ? 1 clr11 ? 0 intc11 interrupt request cr10 cr10 cr10 count disabled ce1 ? 0 count start clear clear clear 290 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.6.2 capture operations timer/event counter 1 performs capture operations in which the timer counter 1 (tm1) count value is fetched into the capture register in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pin (intp0) is used as the external trigger (captu re trigger). the count value of tm1 in the process of being counted is fetched into the capture register (cr12), or the capture/ compare register (cr11) when a capture operation is specified, in synchronization with the capture trigger, and is retained the re. the contents of the cr11 and cr12 are retained until the next capture trigger is generated. the capture trigger valid edge is set by means of external interrupt mode register 0 (intm0). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 22-1 for details of the intm0 format. when cr11 is used as a capture register, tm1 can be cleared as soon as the contents of tm1 have been captured to cr11 by capture trigger. figure 10-16. capture operation in 8-bit operation mode remark dn: tm1 count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 0, cm = 1, bw1 = 0 intp0 pin input intp0 interrupt request tm1 count value 0h ffh capture/compare register (cr11) ovf1 count start d0 d1 d2 d0 d1 d2 291 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-17. capture operation in 16-bit operation mode remark dn: tm1w count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 0, cm = 1, bw1 = 1 intp0 pin input intp0 interrupt request tm1w count value 0h ffffh capture register (cr12w) ovf1 count start ce1 ? 1 d0 d1 d2 d0 d1 d2 292 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-18. tm1 clearance after capture operation remark ni: tm1 count value (n = 0, 1, 2, ...) clr10 = 0, clr11 = 1, cm = 1 intp0 pin input intp0 interrupt request tm1 count value 0h capture/compare register (cr11) n1 capture capture capture capture capture n2 n3 n4 n5 n3 n2 n4 n1 293 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.7 examples of use 10.7.1 operation as interval timer (1) when timer counter 1 (tm1) is made free-running and a fixed value is added to the compare register (cr1n: n = 0, 1) in the interrupt service routine, tm1 operates as an interval timer with the added fixed value as the cycle (see figure 10-19 ). since tm1 has two compare registers, two interval timers with different intervals can be constructed. the control register settings are shown in figure 10-20, the setting procedure in figure 10-21, and the processing in the interrupt service routine in figure 10-22. figure 10-19. interval timer operation (1) timing remark interval = n x/f xx , 1 n ffh x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 mod (2n) intc10 interrupt request tm1 count value 0h ffh compare register (cr10) n timer start mod (3n) mod (4n) ffh n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program 294 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-20. control register settings for interval timer operation (1) (a) prescaler mode register 1 (prm1) (b) capture/compare control register 1 (crc1) 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) 7 0 crc1 6 0 5 0 4 0 3 0 2 0 1 0 0 0 tm1 clearing by match of cr10 & tm1 contents disabled cr11 specified as compare register tm1 clearing by match of cr11 & tm1 contents disabled 295 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-21. interval timer operation (1) setting procedure figure 10-22. interval timer operation (1) interrupt request servicing interval timer (1) set count value in cr10 cr10 ? n start count ce1 ? 1 intc10 interrupt ; set 1 in bit 3 of tmc1 set prm1 set crc1 crc1 ? 00h intc10 interrupt calculate timer value that will generate next interrupt cr10 ? cr10+n other interrupt service program reti 296 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.7.2 operation as interval timer (2) tm1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 10-23 ). the control register settings are shown in figure 10-24, and the setting procedure in figure 10-25. figure 10-23. interval timer operation (2) timing (when cr11 is used as compare register) remark interval = (n+1) x/f xx 0 n ffh x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 compare register (cr11) intc11 interrupt request tm1 count value 0h n n n count start clear clear interval match match interrupt acknowledge interrupt acknowledge interval 297 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-24. control register settings for interval timer operation (2) (a) prescaler mode register 1 (prm1) (b) capture/compare control register 1 (crc1) figure 10-25. interval timer operation (2) setting procedure 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) 7 0 crc1 6 0 5 0 4 0 3 1 2 0 1 0 0 0 tm1 clearing by match of cr10 & tm1 contents disabled cr11 specified as compare operation tm1 clearing by match of cr11 & tm1 contents enabled interval timer (2) set count value in cr11 cr11 ? n intc11 interrupt ; set 1 in bit 3 of tmc1 set prm1 set crc1 crc1 ? 08h start count ce1 ? 1 298 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.7.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp0) is measured. both the high-level and low-level widths of pulses input to the intp0 pin must be at least 3 sampling clocks selected by scs0; if shorter than this, the valid edge will not be detected and a capture operation will not be performed. as shown in figure 10-26, the timer counter 1 (tm1) value being counted is fetched into the capture/compare register (cr11) set as a capture register in synchronization with a valid edge (set as both rising and falling edges) in the intp0 pin input, a nd held there. the pulse width is obtained from the product of the difference between the tm1 count value (d n ) fetched into and held in the cr11 on detection of the nth valid edge and the count value (d n-1 ) fetched and held on detection of valid edge n-1, and the number of count clocks (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). the control register settings are shown in figure 10-27, and the setting procedure in figure 10-28. figure 10-26. pulse width measurement timing (when cr11 is used as capture register) remark dn: tm1 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 intp0 external input signal intp0 interrupt request tm1 count value 0h ffh capture/compare register (cr11) ovf1 d0 d1 count start ce1 ? 1 ffh d2 d3 (d1-d0) x/f xx (d3-d2) x/f xx cleard by software d1 d0 d2 d3 (100h-d1+ d2) x/f xx capture capture capture capture 299 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-27. control register settings for pulse width measurement (a) prescaler mode register 1 (prm1) (b) capture/compare control register 1 (crc1) 7 prm1 6 5 4 3 prs13 2 prs12 1 prs11 0 prs10 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) (c) external interrupt mode register 0 (intm0) 7 0 crc1 6 0 5 0 4 0 3 0 2 1 1 0 0 0 tm1 clearing by match of tm1 & cr10 contents disabled cr11 specified as capture operation tm1 clearing upon capture of cr11 in tm1 disabled 7 intm0 6 5 4 3 1 2 1 1 0 0 both rising & falling edges specified as intp0 input valid edges 300 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-28. pulse width measurement setting procedure figure 10-29. interrupt request servicing that calculates pulse width pulse width measurement initialize capture value buffer memory x 0 ? 0 intp0 interrupt ; set 1 in bit 3 of tmc1 set prm1 set intm0 set mk0l set crc1 crc1 ? 04h enable interrupts start count ce1 ? 1 ; specify both edges as intp0 input valid edges, release interrupt masking intp0 interrupt calculate pulse width y n = cr11 ?x n store capture value in memory x n+1 ? cr11 reti 301 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 10.8 cautions (1) while timer/event counter 1 is operating (while the ce1 bit of the timer control register 1 (tmc1) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following register s. ? prescaler mode register 1 (prm1) ? capture/compare control register 1 (crc1) ? cmd2 bit of timer control register 1 (tmc1) (2) if the contents of the compare register (cr1n: n = 0 or 1) coincide with those of tm1 when an instruction that stops timer counter 1 (tm1) operation is executed, the counting operation of tm1 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm1, mask the interrupt in advance by using the interrupt mask register before stopping tm1. example program that may generate interrupt request program that does not generate interrupt request clr1 ce1 or mk0l, #c0h or mk0l, #c0h clr1 ce1 clr1 cif10 clr1 cif11 (3) up to 1 count clock is required after an operation to start timer/event counter 1 (ce1 ? 1) has been performed before timer/ event counter 1 actually starts (refer to figure 10-30 ). for example, when using timer/event counter 1 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 10-30. operation when counting is started . . . . . . ? disables interrupt from timer/ event counter 1 ? clears interrupt request flag from timer/event counter 1 ? interrupt request from timer/event counter 1 occurs between these instructions count clock tm1 ce1 timing to start actual counting count start command (ce1 ? 1) by software 0 0 123 302 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 (4) while an instruction that writes data to the compare register (cr1n: n = 0, 1) is executed, coincidence between cr1n, to which the data is to be written, and timer counter 1 (tm1) is not detected. write data to cr1n when timer/event counter 1 is executing counting operation in the timing that the contents of tm1 do not coincide with the value of cr1n before and after writing (e.g., immediately after an interrupt request has been generated because tm1 and cr1n have coincided). (5) coincidence between tm1 and compare register (cr1n: n = 0, 1) is detected only when tm1 is incremented. therefore, the interrupt request is not generated even if the same value as tm1 is written to cr1n. (6) when timer/event counter 1 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer counter 1 (tm1) alone (refer to figure 10-31 ), since the contents of tm1 are 0 in both cases. if it is necessary to make this distinction, the intp3 interrupt request flag should be used. to make a distinction, use the interrupt request flag of intp0, as shown in figure 10-32. figure 10-31. example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input intp0 tm1 0 1 2 0 cannot be distinguished count start 303 chapter 10 timer/event counter 1 preliminary users manual u13987ej1v0um00 figure 10-32. to distinguish whether one or no valid edge has been input with external event counter (a) processing when count is started (b) processing when count value is read ; set ce1 to 1 ; clear pif0 to 0 clear intp0 interrupt request flag pif0 ? 0 start count ce1 ? 1 start count end ; number of input valid edges is set to a register count value read read tm1 contents a ? tm1 a ? a+1 end a = 0? pif0 = 1? ; check tm1 value. if 0, check interrupt request flag. ; check pif0 contents. if 1, valid edge is input. yes no yes no 304 preliminary users manual u13987ej1v0um00 [memo] 305 preliminary users manual u13987ej1v0um00 chapter 11 timer/event counter 2 11.1 functions timer/event counter 2 is 16-bit or 8-bit timer/event counter, and has the following function which the other three timer/ counters do not have: ? one-shot timer note note the one-shot timer function is a count operation of timer/event counter 2 (tm2/tm2w), and is thus different in nature from the one-shot pulse output function of timer/event counter 0. in this section, the following four basic functions are described in order: ? interval timer ? programmable square-wave output ? pulse width measurement ? external event counter (1) interval timer generates internal interrupts at preset intervals. table 11-1. timer/event counter 2 intervals minimum interval maximum interval resolution 4/f xx 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz 306 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (2) programmable square-wave output outputs square waves independently to the timer output pins (to2 and to3). table 11-2. timer/event counter 2 programmable square-wave output setting range minimum pulse width maximum pulse width 4/f xx 2 16 4/f xx (0.32 m s) (20.8 ms) 8/f xx 2 16 8/f xx (0.64 m s) (41.7 ms) 16/f xx 2 16 16/f xx (1.27 m s) (83.4 ms) 32/f xx 2 16 32/f xx (2.54 m s) (167 ms) 64/f xx 2 16 64/f xx (5.09 m s) (333 ms) 128/f xx 2 16 128/f xx (10.17 m s) (667 ms) 256/f xx 2 16 256/f xx (20.35 m s) (1.33 s) 512/f xx 2 16 512/f xx (40.70 m s) (2.67 s) 1,024/f xx 2 16 1,024/f xx (81.40 m s) (5.33 s) ( ): when f xx = 12.58 mhz caution the above table is applicable to use of an internal clock. 307 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (3) pulse width measurement detects the pulse width of the signal input to an external interrupt request input pins (intp1 and intp2). table 11-3. timer/event counter 2 pulse width measurement range measurable pulse width note resolution 4/f xx to 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx to 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx to 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx to 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx to 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx to 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx to 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx to 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx to 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz note the minimum pulse width that can be measured differs depending on the selected value of f clk . the minimum pulse width that can be measured is the value of 3/f clk or the value in the above table, whichever greater. (4) external event counter counts the clock pulses input from the external interrupt request input pin (intp2) (ci pin input pulses). the clocks that can be input to timer/event counter 2 are shown in table 11-4. table 11-4. clocks enabled to be input to timer/event counter 2 when counting one edge when counting both edges maximum frequency f clk /6 (2.10 mhz) f clk /6 (2.10 mhz) minimum pulse width 3/f clk (0.24 m s) 3/f clk (0.24 m s) (high and low levels) ( ): when f clk = 12.58 mhz and f xx = 12.58 mhz 308 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.2 configuration timer/event counter 2 consists of the following registers. ? timer counter (tm2/tm2w) 1 ? compare register (cr20/cr20w) 1 ? capture/compare register (cr21/cr21w) 1 ? capture register (cr22/cr22w) 1 the block diagram of timer/event counter 2 is shown in figure 11-1. 309 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-1. timer/event counter 2 block diagram internal bus 1/8 8/16 8 external interrupt mode register 0 (intm0) es21 es11 compare register (cr20/cr20w) 16 16 8/16 capture/compare register (cr21/cr21w) 16 8/16 16 16 16 8/16 8 selector f xx /512 f xx /256 f xx /128 f xx /64 f xx f xx /32 f xx /16 f xx /8 f xx /4 prescaler mode register 1 (prm1) prs23 prs22 prs21 prs20 capture register (cr22/cr22w) timer counter 2 (tm2/tm2w) timer control register 1 (tmc1) ovf2 ce2 1/8 internal bus p22/intp1 edge detection circuit edge detection circuit cmd2 overflow selector 8 8 8 8 intp2 match match match match reset capture/compare control register 2 (crc2) p23/intp2/ci intp1 p36/to2 es20 es10 f xx /1,024 prescaler capture trigger capture trigger mod1 mod0 clr22 clr21 cm21 ent03 alv3 ent02 alv2 timer output control register (toc) output control circuit output control circuit intc20 p37/to3 intc21 bw2 intp2 8 pwm/ppg output control selector selector 310 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (1) timer counter 2 (tm2/tm2w) tm2/tm2w is a timer counter that counts up the count clock specified by the high-order 4 bits of prescaler mode register 1 (prm1). an internal clock or external clock can be selected as the count clock. the count operation can be stopped or enabled by means of timer control register 1 (tmc1). the timer counter can select to operate in an 8-bit (tm2) or 16-bit (tm2w) mode. tm2/tm2w can be read only with an 8/16-bit manipulation instruction. when reset is input, tm2/tm2w is cleared to 00h and the count is stopped. (2) compare register (cr20/cr20w) cr20/cr20w is an 8/16-bit register that holds the value that determines the interval timer operation cycle. if the contents of the cr20/cr20w register match the contents of tm2/tm2w, an interrupt request (intc20) and a timer output control signal are generated. this compare register operates as cr20 in the 8-bit mode, and cr20w in the 16-bit mode. cr20/cr20w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (3) capture/compare register (cr21/cr21w) cr21/cr21w is an 8/16-bit register that can be specified as a compare register for detecting a match with the tm2/ tm2w count value or a capture register for capturing the tm2/tm2w count value according to the setting of the capture/ compare control register 2 (crc2). this capture/compare register operates as cr21 in the 8-bit mode, and cr21w in the 16-bit mode. cr21/cr21w can be read or written to with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. (a) when specified as compare register cr21/cr21w functions as an 8/16-bit register that holds the value that determines the interval timer operation cycle. an interrupt request (intc21) and a timer output control signal are generated by a match between the contents of the cr21/cr21w register and the contents of tm2/tm2w. also, the count value can be cleared by a match of the contents. (b) when specified as capture register cr21/cr21w functions as an 8/16-bit register that captures the contents of tm2/tm2w in synchronization with the input of a valid edge on the external interrupt input pin (intp2) (capture trigger). the contents of the cr21/cr21w register are retained until the next capture trigger is generated. (4) capture register (cr22/cr22w) cr22/cr22w is an 8/16-bit register that captures the contents of tm2/tm2w. the capture operation is synchronized with the input of a valid edge to the external interrupt request input pin (intp1) (capture trigger). the contents of the cr22/cr22w register are retained until the next capture trigger is generated. also, tm2/tm2w can be cleared after a capture operation. this capture register operates as cr22 in the 8-bit mode, and cr22w in the 16-bit mode. cr22/cr22w can be read only with an 8/16-bit manipulation instruction. the contents of this register are undefined after reset input. 311 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (5) edge detection circuit the edge detection circuit detects an external input valid edge. this circuit generates an external interrupt request (intp1) and capture trigger by detecting the valid edge of the intp1 pin input specified by the external interrupt mode register 0 (intm0). it also generates a capture trigger, the count clock of an external event, and external interrupt request (intp2) by detecting the valid edge from an external interrupt request input pin (intp2). (6) output control circuit it is possible to invert the timer output when the cr20/cr21 register contents and the contents of tm2 match or the cr20w/cr21w contents and the contents of tm2w match. a square wave can be output from the timer output pins (to2/to3) in accordance with the setting of the high-order 4 bits of the timer output control register (toc). at this time, pwm output or ppg output can be performed according to the specification of the capture/compare control register 2 (crc2). timer output can be disabled/enabled by means of the toc register. when timer output is disabled, a fixed level is output to the to2 and to3 pins (the output level is set by the toc register). (7) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by the prescaler is selected by the selector, and is used as the count clock by the timer counter 2 (tm2/tm2w) to perform count operations. (8) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of timer counter 2 (tm2/tm2w). 312 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.3 timer/event counter 2 control registers (1) timer control register 1 (tmc1) in tmc1 the timer/event counter 2 tm2/tm2w count operation is controlled by the high-order 4 bits (the low-order 4 bits control the count operation of timer/event counter 1, tm1/tm1w). tmc1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of tmc1 is shown in figure 11-2. reset input clears tmc1 to 00h. figure 11-2. timer control register 1 (tmc1) format remark the ovf2 bit is reset by software only. 7 ce2 tmc1 6 ovf2 5 cmd2 4 bw2 3 ce1 2 ovf1 1 0 0 bw1 address after reset r/w r/w 00h 0ff5fh bw2 timer/event counter 2 bit length specification 8-bit operation mode 16-bit operation mode 1 0 cmd2 tm2/tm2w operation mode specificaton normal mode one-shot mode 1 0 ovf2 tm2/tm2w overflow flag no overflow overflow note 1 0 ce2 tm2/tm2w count operation control count operation stopped with count cleared count operation enabled 1 0 controls count operation of timer/event counter 1 tm1/tm1w (see figure 10-2 ). note 8-bit operating mode: count up from ffh to 00h in 16-bit operating mode: count up from ffffh to 0000h 313 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (2) prescaler mode register 1 (prm1) in prm1, the count clock to timer/event counter 2 tm2/tm2w is specified by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/event counter 1 tm1/tm1w). prm1 can be read or written with an 8-bit manipulation instruction. the format of prm1 is shown in figure 11-3. reset input sets prm1 to 11h. figure 11-3. prescaler mode register 1 (prm1) format remark f xx : x1 input frequency or oscillation frequency prs23 prs22 prs21 prs20 prs13 prs12 prs11 prs10 76543210 prm1 0ff5eh address 11h after reset r/w r/w prs23 0 0 0 0 0 0 0 0 1 1 1 specifies count clock to timer/event counter 1 (tm1/tm1w) (see figure 10-3 ). prs22 0 0 0 0 1 1 1 1 0 0 1 prs21 0 0 1 1 0 0 1 1 0 0 1 prs20 0 1 0 1 0 1 0 1 0 1 1 timer/event counter 2 tm2/ tm2w count clock specification count clock [hz] specification resolution [ s] setting prohibited f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock (ci/intp2) setting prohibited 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 other than the above (f xx = 12.58 mhz) m 314 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (3) capture/compare control register 2 (crc2) crc2 specifies the enabling condition for a timer counter 2 (tm2/tm2w) clear operation by the capture/compare register (cr21/cr21w) or the capture register (cr22/cr22w) and the timer output (to2/to3) mode. crc2 can be read or written with an 8-bit manipulation instruction. the format of crc2 is shown in figure 11-4. reset input sets crc2 to 10h. figure 11-4. capture/compare control register 2 (crc2) format remark the register names in the 8-bit operation mode are shown in this figure. in the 16-bit operation mode, the register names tm2, cr20, cr21, and cr22 are tm2w, cr20w, cr21w, and cr22w, respectively. 7 mod1 crc2 6 mod0 5 clr22 4 1 3 clr21 2 cm21 1 0 0 0 address after reset r/w r/w 10h 0ff33h mod1 mod0 clr22 clr21 timer output mode specification compare operations capture operations cr21 operation specification tm2 clear operation toggle output toggle output toggle output toggle output toggle output to2 to3 setting prohibited other than the above not cleared pwm output toggle output not cleared pwm output ppg output pwm output toggle output not cleared not cleared pwm output not cleared 0000 cm21 0 00010 toggle output toggle output toggle output 00100 toggle output toggle output 00110 01000 10000 11010 00001 00011 01001 cleared if tm2 and cr21 match cleared if tm2 and cr21 match cleared after tm2 contents are captured in cr22 by intp1 cleared after tm2 contents are captured in cr21 by intp2 cleared by match of tm2 and cr21 or after tm2 contents are captured in cr22 by intp1 315 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (4) timer output control register (toc) toc is an 8-bit register that controls output enabling/disabling of the active level of timer output. the operation of the timer output pins (to2/to3) by timer/event counter 2 is controlled by the high-order 4 bits (the low-order 4 bits control the operation of the timer output pins (to0/to1) by timer/event counter 0). toc can be read or written with an 8-bit manipulation instruction or bit manipulation instruction. the format of toc is shown in figure 11-5. reset input clears toc to 00h. figure 11-5. timer output control register (toc) format 7 ento3 toc 6 alv3 5 ento2 4 alv2 3 ento1 2 alv1 1 ento0 0 alv0 address after reset r/w r/w 0000h 0ff31h ento2 to2 pin operation specification alv2 output pulse output enabled 1 0 control operation of timer output pins (to0 & to1) by timer/event counter 0 (see figure 9-5 ). alv2 to2 pin active level toggle output specification pwm/ppg output specification low level high level high level low level 1 0 ento3 to3 pin operation specification alv3 output pulse output enabled 1 0 alv3 to3 pin active level toggle output specification pwm/ppg output specification low level high level high level low level 1 0 316 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.4 timer counter 2 (tm2) operation 11.4.1 basic operation 8-bit operation mode/16-bit operation mode control can be performed for timer/event counter 2 by means of bit 0 (bw2) of timer control register 2 (tmc2) note . in the timer/event counter 2 count operation, a count-up is performed using the count clock specified by the high-order 4 bits of prescaler mode register 1 (prm1). count operation enabling/disabling is controlled by bit 3 (ce2) of tmc2 (timer/event counter 2 operation control is performed by the high-order 4 bits of the timer control register 1 (tmc1). when the ce2 bit is set (to 1) by software, the contents of tm2 are cleared to 0h on the first count clock, and then the count-up operation is performed. when the ce2 bit is cleared (to 0) by software, tm2 becomes 0h immediately, and capture operations and match signal generation are stopped. if the ce2 bit is set (to 1) again when it is already set (to 1), the tm2 count operation is not affected (see figure 11- 6 (b) ). tm2/tm2w is cleared to 0h when the count clock is input while the value of tm2 is ffh in the 8-bit operation mode or while the value of tm2w is ffffh in the 16-bit operation mode. at this time, ovf2 bit is set and the overflow signal is sent to the output control circuit. ovf2 bit is cleared by software only. the count operation is continued. when reset is input, tm2 is cleared to 0h, and the count operation is stopped. note unless otherwise specified, the functions of timer counter 2 in the 8-bit operation mode are described hereafter. in the 16-bit operation mode, tm2, cr20, cr21, and cr22 operate as tm2w, cr20w, cr21w, and cr22w, respectively. 317 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-6. basic operation in 8-bit operation mode (bw2 = 0) (a) count started ? count disabled ? count started (b) when 1 is written to the ce2 bit again after the count starts tm2 ovf2 feh ffh 0h cleared by software ovf2 ? 0 count clock f clk /8 1h tm2 ce2 0h 0h 1h 2h 3h 4h 5h 6h count started ce2 ? 1 rewrite ce2 ? 1 count clock (c) operation when tm2 = ffh tm2 ce2 0h 0h 1h 2h 0fh 10h 11h 0h 1h 0h count started ce2 ? 1 count stopped ce2 ? 0 count started ce2 ? 1 count clock 318 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-7. basic operation in 16-bit operation mode (bw2 = 1) (a) count started ? count disabled ? count started (b) when 1 is written to the ce2 bit again after the count starts (c) operation when tm2w = ffffh tm2w ce2 0h 0h 1h 2h ffh 100h 101h 0h 1h 0h count started ce2 ? 1 count started ce2 ? 1 count stopped ce2 ? 0 count clock tm2w ce2 0h 0h 1h 2h 3h 4h 5h 6h count started ce2 ? 1 rewrite ce2 ? 1 count clock tm2w ovf2 fffeh ffffh 0h cleared by software ovf2 ? 0 count clock f clk /8 1h 319 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.4.2 clear operation (1) clear operation after match with compare register and capture operation timer counter 2 (tm2) can be cleared automatically after a match with the compare register (cr2n: n = 0, 1) and a capture operation. when a clearance source arises, tm2 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 11-8. tm2 clearance by match with compare register (cr20/cr21) figure 11-9. tm2 clearance after capture operation (2) clear operation by ce2 bit of timer control register 1 (tmc1) tm2 is also cleared when the ce2 bit of the tmc1 is cleared (to 0) by software. the clear operation is performed immediately after clearance (to 0) of the ce2 bit. tm2 compare register (cr2n) n cleared here count clock 0 1 n-1 n tm2 and cr2n match tm2 intp1 n tm2 is captured in cr22 here cleared here count clock 0 1 2 n-1 320 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-10. clear operation when ce2 bit is cleared (0) (a) basic operation (b) restart before count clock is input after clearance (c) restart after count clock is input after clearance tm2 ce2 n count clock n-1 0 tm2 ce2 n 0 count clock n-1 0 1 2 if the ce2 bit is set (to 1) before this count clock, this count clock starts counting from 0. tm2 ce2 n 0 count clock n-1 0 0 1 if the ce2 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce2 bit is set (to 1). 321 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.5 external event counter function timer/event counter 2 can count clock pulses input from external interrupt request input pin (intp2/ci). no special selection method is needed for the external event counter operation mode. when the timer counter 2 (tm2) count clock is specified as external clock input by the setting of the high-order 4 bits of prescaler mode register 1 (prm1), tm2 operates as an external event counter. the maximum frequency of external clock pulses that can be counted by tm2 as the external event counter is 2.10 mhz (f clk = 12.58 mhz) irrespective of whether only one edge or both edges are counted on intp2/ci input. the pulse width of intp2/ci input must be at least 3 system clocks (0.24 m s: f clk = 12.58 mhz) for both the high level and low level. if the pulse width is shorter than this, the pulse may not be counted. the timer/event counter 2 external event count timing is shown in figure 11-11. figure 11-11. timer/event counter 2 external event count timing (1) counting one edge (maximum frequency = f clk /6) remark ici: ci input signal after passing through edge detection circuit ici tm2 ci 3/f clk (min.) 3/f clk (min.) 6/f clk (min.) dn+1 dn dn+2 dn+3 2-3/f clk remark ici: ci input signal after passing through edge detection circuit (2) counting both edges (maximum frequency = f clk /6) ici tm2 ci 3/f clk (min.) 3/f clk (min.) 6/f clk (min.) dn+1 dn dn+2 dn+3 dn+4 dn+5 2-3/f clk 322 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 the tm2 count operation is controlled by the ce2 bit of the timer control register 1 (tmc1) in the same way as with the basic operation. when the ce2 bit is set (to 1) by software, the contents of tm2 are set to 0h and the count-up operation is started on the initial count clock. when the ce2 bit is cleared (to 0) by software during a tm2 count operation, the contents of tm2 are set to 0h immediately and the stopped state is entered. the tm2 count operation is not affected if the ce2 bit is set (to 1) by software again when it is already set (to 1). caution when timer/event counter 2 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input using timer counter 2 (tm2) alone (see figure 11-12), since the contents of tm2 are 0 in both cases. if it is necessary to make this distinction, the intp2 interrupt request flag should be used (the intp2 pin and ci pin have a dual function, and both functions can be used at the same time). an example is shown in figure 11-13. figure 11-12. example of the case where the external event counter does not distinguish between one valid edge input and no valid edge input tm2 0 intp2/ci 1 2 0 count start no distinction made 323 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-13. to distinguish whether one or no valid edge has been input with external event counter (a) processing when count is started (b) processing when count value is read clear intp2 interrupt request flag pif2 ? 0 ; clear pif2 to 0 end start count start count ce2 ? 1 ; set ce2 to 1 read tm2 contents a ? tm2 a ? a+1 ; check pif2 contents if 1, there is a valid edge ; number of input valid edges is set in a register ; check tm2 value if 0, check interrupt request flag end pif2 = 1? yes yes no no count value read a = 0? 324 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.6 one-shot timer function timer/event counter 2 has an operation mode in which it stops automatically when a full count value is reached (ffh/ ffffh) as a result of counting by timer counter 2 (tm2/tm2w). figure 11-14. one-shot timer operation as shown in figure 11-14, the respective one-shot interrupt is generated when the value (0h to ffh/ffffh) set beforehand in the cr20, cr21/cr21w, or cr21w and tm2/tm2w value match. the one-shot timer operation mode is specified by setting (to 1) bit 5 (cmd2) of timer control register 1 (tmc1) by software. the tm2/tm2w count operation is controlled by the ce2 bit of the tmc1 as with the basic operation. when the ce2 bit is set (to 1) by software, the contents of tm2/tm2w are set to 0h and the count-up operation is started on the initial count clock. when the contents of tm2/tm2w reach ffh/ffffh (full count) as a result of the count-up operation, bit 6 (ovf2) of the tmc1 are set (to 1), and tm2/tm2w stops with the count at ffh/ffffh. the one-shot timer operation is started again from the count-stopped state by clearing (to 0) the ovf2 bit by software. when the ovf2 bit is cleared (to 0), the contents of tm2/tm2w become 0h and the count-up operation is restarted on the next count clock. if the ce2 bit is cleared (to 0) by software during a tm2/tm2w count operation, the contents of tm2/tm2w are set to 0h immediately and the stopped state is entered. the tm2/tm2w count operation is not affected if the ce2 bit is set (to 1) by software again when it is already set (to 1). intc21 interrupt request tm2/tm2w count value 0h ffh or ffffh count start ce2 ? 1 cr21/cr21w value ovf2 clear ovf2 ? 0 325 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.7 compare register, capture/compare register, and capture register operation 11.7.1 compare operations timer/event counter 2 performs compare operations in which the value set in the compare register (cr20) and the capture/compare register (cr21) specified for compare operation is compared with the timer counter 2 (tm2) count value. if the count value of tm2 matches the preset value of the cr20, and cr21 when a compare operation is performed, as the result of the count operation, a match signal is sent to the output control circuit, and an interrupt request signal (intc20/intc21) is generated at the same time. after a match with the cr20 or cr21 value, the tm2 contents can be cleared, and the timer functions as an interval timer that repeatedly counts up to the value set in the cr20 or cr21. figure 11-15. compare operation in 8-bit operation mode remark clr21 = 0, clr22 = 0, bw2 = 0 intc20 interrupt request tm2 count value 0h ffh count start ce2 ? 1 cr20 value cr21 value ffh cr20 value cr21 value intc21 interrupt request to2 pin output ento2 = 1 alv2 = 1 ovf2 match match match match to3 pin output ento2 = 1 alv3 = 0 cleared by software inactive level inactive level 326 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-16. compare operation in 16-bit operation mode remark clr21 = 0, clr22 = 0, bw2 = 1 intc20 interrupt request tm2w count value 0h ffffh count start ce2 ? 1 cr20w value cr21w value ffffh cr20w value cr21w value intc21 interrupt request to2 pin output ento2 = 1 alv2 = 1 ovf2 match match match match to3 pin output ento2 = 1 alv3 = 0 cleared by software inactive level inactive level 327 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-17. tm2 clearance after match detection remark clr22 = 0 11.7.2 capture operations timer/event counter 2 performs capture operations in which the timer counter 2 (tm2) count value is fetched into the capture register in synchronization with an external trigger, and retained there. a valid edge detected from the input of the external interrupt request input pins (intp1/intp2) is used as the external trigger (capture trigger). the count value of tm2 in the process of being counted in synchronization with the capture trigger is fetched into the capture register (cr22) in synchronization with intp1, or into the capture/compare register (cr21) when a capture operation is specified in synchronization with intp2, and is retained there. the contents of cr21 and cr22 are retained until the next capture triggers corresponding to cr21 and cr22 are generated. the capture trigger valid edge is set by means of external interrupt mode register 0 (intm0). if both rising and falling edges are set as capture triggers, the width of pulses input from off-chip can be measured, and if a capture trigger is generated by a single edge, the input pulse cycle can be measured. see figure 22-1 for details of the intm0 format. when cr21 is used as a capture register, tm2 can be cleared as soon as the contents of tm2 have been captured by capture trigger to cr21 or cr22. intc20 interrupt request tm2 count value 0h ffh count start ce2 ? 1 clr21 ? 0 intc21 interrupt request to2 pin output ento2 ? 1 alv2 ? 1 ovf2 to3 pin output ento3 ? 1 alv3 ? 1 cleared by software cr20 cr21 cr21 cr21 inactive level inactive level count start ce2 ? 1 clr21 ? 1 count disabled ce2 ? 0 clear clear 328 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-18. capture operation in 8-bit operation mode remark dn: tm2 count value (n = 0, 1, 2, ...) cm21 = 1, clr21 = 0, clr22 = 0, bw2 = 0 tm2 count value count start ce ? 1 0h intp2 pin input intp2 interrupt request capture register (cr21) intp1 pin input intp1 interrupt request capture register (cr22) ovf2 d0 d3 d6 d1 d2 d4 d5 d7 d0 d1 d2 d3 d4 d6 d7 d5 ffh 329 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-19. capture operation in 16-bit operation mode remark dn: tm2w count value (n = 0, 1, 2, ...) cm21 = 1, clr21 = 0, clr22 = 0, bw2 = 0 tm2w count value count start ce ? 1 0h intp2 pin input intp2 interrupt request capture register (cr21w) intp1 pin input intp1 interrupt request capture register (cr22w) ovf2 d0 d3 d6 d1 d2 d4 d5 d7 d0 d1 d2 d3 d4 d6 d7 d5 ffffh 330 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-20. tm2 clearance after capture operation remark clr21 = 0, clr22 = 1 11.8 basic operation of output control circuit the output control circuit controls the timer output pins (to2/to3) level by means of match signals from the compare register (cr22). the operation of the output control circuit is determined by the timer output control register (toc) and capture/compare control register 2 (crc2) (see table 11-5 ). when to2/to3 signal is output to a pin, the relevant pin must be in control mode in the port 3 mode register (pmc3). n3 intp1 pin input intp1 interrupt request tm2 count value 0h capture/compare register (cr22) n2 n1 n4 capture capture capture capture capture n1 n2 n3 n4 n5 331 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 table 11-5. timer output (to2/to3) operations toc crc2 tmc1 to3 to2 ento3 alv3 ento2 alv2 mod1 mod0 clr22 clr21 cmd2 0 0/1 0 0/1 high/low level fixed high/low level fixed 0 0/1 1 0/1 0 0 note high/low level fixed toggle output (active-low/high) 1 0/1 0 0/1 0 0 note toggle output (active-low/high) high/low level fixed 1 0/1 1 0/1 0 0 note toggle output (active-low/high) toggle output (active-low/high) 00/110/101000 high/low level fixed pwm output (active-high/low) 10/100/101000 toggle output (active-low/high) high/low level fixed 10/110/101000 toggle output (active-low/high) pwm output (active-high/low) 00/110/110000 high/low level fixed pwm output (active-high/low) 10/100/110000 pwm output (active-high/low) high/low level fixed 10/110/110000 pwm output (active-high/low) pwm output (active-high/low) 00/110/111010 high/low level fixed ppg output (active-high/low) 10/100/111010 toggle output (active-low/high) high/low level fixed 10/110/111010 toggle output (active-low/high) ppg output (active-high/low) note clr22 is normally set to 0 in this case. remarks 1. 0/1 in the alvn (n = 2, 3) columns correspond to the items on the left and right of the slash (/) in the ton (n = 2, 3) colum ns respectively. 2. indicates 0 or 1. 3. combinations not shown in this table are prohibited to use in that combination. 332 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.8.1 basic operation setting (to 1) the enton (n = 2, 3) bit of the timer output control register (toc) enables timer output (ton: n = 2, 3) to be varied at a timing in accordance with the settings of mod0, mod1, and clr21 bits of capture/compare control register 2 (crc2). clearing (to 0) enton sets the ton to a fixed level. the fixed level is determined by the alvn (n = 2, 3) bit of the toc. the level is high when alvn is 0, and low when 1. 11.8.2 toggle output toggle output is an operation mode in which the output level is inverted each time the compare register (cr20/cr21) value coincides with the timer counter 2 (tm2) value. the output level of timer output (to2) is inverted by a match between cr20 and tm2, and the output level of timer output (to3) is inverted by a match between cr21 and tm2. when timer/event counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1), the inactive level (alvn: n = 0, 1) is output. figure 11-21. toggle output operation ento0 tm2 count value 0h ffh instruction execution cr20 value cr21 value ffh cr20 value cr21 value ffh cr20 value cr21 value ffh cr20 value cr21 value ffh to2 output (alv2 = 1) ento3 to3 output (alv3 = 0) instruction execution instruction execution instruction execution 333 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 table 11-6. to2/to3 toggle output (f xx = 12.58 mhz) count clock minimum pulse width maximum pulse width f xx /4 4/f xx 2 16 4/f xx (0.32 m s) (0.32 m s) (20.8 ms) f xx /8 8/f xx 2 16 8/f xx (0.64 m s) (0.64 m s) (41.7 ms) f xx /16 16/f xx 2 16 16/f xx (1.27 m s) (1.27 m s) (83.4 ms) f xx /32 32/f xx 2 16 32/f xx (2.54 m s) (2.54 m s) (167 ms) f xx /64 64/f xx 2 16 64/f xx (5.09 m s) (5.09 m s) (333 ms) f xx /128 128/f xx 2 16 128/f xx (10.17 m s) (10.17 m s) (667 ms) f xx /256 256/f xx 2 16 256/f xx (20.35 m s) (20.35 m s) (1.33 s) f xx /512 512/f xx 2 16 512/f xx (40.70 m s) (40.70 m s) (2.67 s) f xx /1,024 1,024/f xx 2 16 1,024/f xx (81.40 m s) (81.40 m s) (5.33 s) 334 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.8.3 pwm output (1) basic operation of pwm output in this mode, a pwm signal with the period in which timer counter 2 (tm2) reaches a full count used as one cycle is output. the timer output (to2) pulse width is determined by the value of compare register (cr20), and the timer output (to3) pulse width is determined by the value of compare register (cr21). when this function is used, the clr21 bit and clr22 bit of capture/compare control register 2 (crc2) and the cmd2 bit of timer control register 1 (tmc1) must be set to 0. the pulse cycle and pulse width are as shown below. (a) bw2 = 0 ? pwm cycle = 256 x/f xx ? pwm pulse width = cr2n x/f xx note ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 note 0 cannot be set in the cr2n. ? duty = pwm pulse width = cr2n pwm 256 (b) bw2 = 1 ? pwm cycle = 65,536 x/f xx ? pwm pulse width = cr2n x/f xx note ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 note 0 cannot be set in the cr2n. ? duty = pwm pulse width = cr2n pwm cycle 65,536 335 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-22. pwm pulse output (bw2 = 0) remark alv2 = 0 table 11-7. to2/to3 pwm cycle (f xx = 12.58 mhz, bw2 = 0) count clock minimum pulse width [ m s] pwm cycle [ms] pwm frequency [hz] f xx /4 0.32 0.08 12,286 f xx /8 0.64 0.16 6,143 f xx /16 1.27 0.33 3,071 f xx /32 2.54 0.65 1,536 f xx /64 5.09 1.30 768 f xx /128 10.17 2.60 384 f xx /256 20.35 5.21 192 f xx /512 40.70 10.42 96 f xx /1,024 81.40 20.84 48 cr20 interrupt tm2 count value 0h ffh count start cr20 ffh ffh pulse width pulse cycle pulse width to2 cr20 pulse cycle 336 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-23. pwm pulse output (bw2 = 1) remark alv2 = 0 table 11-8. to2/to3 pwm cycle (f xx = 12.58 mhz, bw2 = 1) count clock minimum pulse width [ m s] pwm cycle [s] pwm frequency [hz] f xx /4 0.32 0.02 47.6 f xx /8 0.64 0.04 23.8 f xx /16 1.27 0.08 12.0 f xx /32 2.54 0.17 6.0 f xx /64 5.09 0.33 3.0 f xx /128 10.17 0.67 1.5 f xx /256 20.35 1.33 0.7 f xx /512 40.70 2.67 0.4 f xx /1,024 81.40 5.33 0.2 cr20 interrupt tm2 count value 0h ffffh count start cr20 ffffh ffffh pulse width pulse cycle to2 cr20 pulse width pulse cycle 337 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-24 shows an example of 2-channel pwm output, and figure 11-25 shows the case where ffffh is set in the cr20w. figure 11-24. example of pwm output using tm2w remark alv2 = 0, alv3 = 0 figure 11-25. example of pwm output when cr20w = ffffh remarks 1. alv2 = 0 2. t = x/f xx (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) tm2w count value 0h cr20w ffffh intc20 cr21w cr20w ffffh cr21w cr20w ffffh intc21 to2 to3 tm2w count value ffffh intc20 0 1 2 fffeh ffffh 0 1 2 fffeh count clock cycle t ffffh 0 pulse width t duty = 100 = 99.6 (%) . . 255 256 pulse cycle = 256t ovf2 to2 338 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (2) rewriting compare registers (cr20, cr21) the output level of the timer output (ton + 2: n + 2 = 2, 3) is not inverted even if the cr2n (n = 0, 1) value matches the timer counter 2 (tm2) value more than once during one pwm output cycle. figure 11-26. example of compare register (cr20w) rewrite remark alv2 = 1 if a value smaller than that of the tm2 is set as the cr2n value, a 100% duty pwm signal will be output. cr2n rewriting should be performed by the interrupt due to a match between tm2 and the cr2n on which the rewrite is performed. figure 11-27. example of 100% duty with pwm output cr20w to2 tm2w count value 0h t1 t1 t2 t1 t2 ffffh cr20w and tm2w values match, but to2 does not change here. cr20w rewrite ffffh t2 remark alv2 = 0 cr20 to2 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cr20 here, the duty of this period will be 100%. ffh ffh ffh ffh n2 n2 n2 n1 339 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (3) stopping pwm output if timer/event counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1) during pwm signal output, the active level is output. figure 11-28. when timer/event counter 2 is stopped during pwm signal output remark alv2 = 1 caution the output level of the ton (n = 2, 3) pin when timer output is disabled (enton = 0: n = 2, 3) is the inverse of the value set in alvn (n = 2, 3) bits. caution is therefore required as the active level is output when timer output is disabled when the pwm output function has been selected. to2 tm2w count value 0h cr20w cr20w ffffh ffffh 340 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.8.4 ppg output (1) basic operation of ppg output this function outputs a square-wave with the time determined by compare register cr21 value as one cycle, and the time determined by compare register cr20 value as the pulse width. the pwm output pwm cycle is made variable. this signal can only be output from timer output (to2). when this function is used, it is necessary to set the clr21 bit of capture/compare control register 2 (crc2) to 1 and the clr22 bit to 0, and to set the cmd2 bit of timer control register 1 (tmc1) to 0. the pulse cycle and pulse width are as shown below. ? ppg cycle = (cr21 + 1) x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 ? ppg pulse width = cr20 x/f xx where 1 cr20 cr21 ? duty = ppg pluse width ppg cycle = cr cr 20 21 1 + figure 11-29 shows an example of ppg output using timer counter 2 (tm2), figure 11-30 shows an example of the case where cr20 = cr21. 341 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-29. example of ppg output using tm2 remark alv2 = 0, alv3 = 0 table 11-9. to2 ppg output (f xx = 12.58 mhz) count clock minimum pulse width [ m s] ppg cycle [s] ppg frequency [hz] f xx /4 0.32 0.64 m s to 20.84 ms 1,572 khz to 48.0 hz f xx /8 0.64 1.27 m s to 41.68 ms 786 khz to 24.0 hz f xx /16 1.27 2.54 m s to 83.35 ms 393 khz to 12.0 hz f xx /32 2.54 5.09 m s to 166.71 ms 197 khz to 6.0 hz f xx /64 5.09 10.17 m s to 333.41 ms 98.3 khz to 3.0 hz f xx /128 10.17 20.35 m s to 666.82 ms 49.1 khz to 1.5 hz f xx /256 20.35 40.70 m s to 1.33 s 24.6 khz to 0.7 hz f xx /512 40.70 81.40 m s to 2.67 s 12.3 khz to 0.4 hz f xx /1,024 81.40 162.80 m s to 5.38 s 6.1 khz to 0.2 hz intc21 tm2 count value 0h cr20 pulse cycle cr20 cr20 cr21 cr21 cr21 intc20 to2 (ppg output) to3 (timer output) pulse width count start 342 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-30. example of ppg output when cr20 = cr21 remark alv2 = 0 t = x/f xx (x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) tm2 count value n intc20 0 1 2 n-1 n 0 1 2 n-1 count cycle t n 0 pulse width = nt pulse cycle = (n+1) t intc21 to2 343 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (2) rewriting compare register (cr20) the output level of the timer output (to2) is not changed even if the cr20 value matches the timer counter 2 (tm2) value more than once during one ppg output cycle. figure 11-31. example of compare register rewrite remark alv2 = 1 cr20 to2 tm2 count value 0h t1 t2 t1 t2 t1 t2 cr20 and tm2 values match, but to2 does not change here. cr20 rewrite cr21 cr21 t1 cr21 cr21 344 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 if a value equal to or less than the tm2 value is written to cr20 before the cr20 and tm2 match, the duty of that ppg cycle will be 100%. cr20 rewriting should be performed by the interrupt due to a match between tm2 and cr20. figure 11-32. example of 100% duty with ppg output remark alv2 = 0 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr20 cannot be rewritten by interrupt processing that is performed on match between tm2 and cr20. use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cr20 to2 tm2 count value 0h n1 n2 n3 n1 when value n2 which is smaller than the tm2 value n3 is written to cr20 here, the duty of this period will be 100%. cr21 cr21 cr21 cr21 n2 n2 n2 n1 345 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (3) rewriting compare register (cr21) if the current value of the cr21 is changed to a smaller value, and the cr21 value is made smaller than the timer counter 2 (tm2) value, the ppg cycle at that time will be extended to the time equivalent to a full-count by tm2. if cr21 is rewritten after the compare register (cr20) and tm2 match, the output level at this time will be the inactive level until tm2 overflows and becomes 0, and will then return to normal ppg output. if cr21 is rewritten before cr20 and tm2 match, the active level will be output until cr20 and tm2 match. if cr20 and tm2 match before tm2 overflows and becomes 0, the inactive level is output at that point. when tm2 overflows and becomes 0, the active level will be output, and normal ppg output will be restored. cr21 rewriting should be performed by the interrupt due to a match between tm2 and cr21, etc. figure 11-33. example of extended ppg output cycle remark alv2 = 1 caution if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of cr2n cannot be rewritten by interrupt processing that is performed on match between timer counter 2 (tm2) and compare register (cr2n: n = 0, 1). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). cr20 to2 tm2 count value 0h n3 n4 n2 to2 becomes inactive level when cr20 and tm2 match, otherwise it remains at the active level. full count value n4 n2 n3 n1 n2 cr21 n5 n3 n1 n1 n1 when value n2 smaller than the tm2 value n5 is written to cr21 here, the ppg cycle is extended. 346 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (4) stopping ppg output if timer/event counter 2 is stopped by clearing (to 0) the ce2 bit of the timer control register 1 (tmc1) during ppg signal output, the active level is output irrespective of the output level at the time timer/event counter 2 was stopped. figure 11-34. when timer/event counter 2 is stopped during ppg signal output caution the output level of the ton (n = 2, 3) pin when timer output is disabled (enton = 0: n = 2, 3) is the inverse value of the value set in alvn (n = 2, 3) bits. caution is therefore required as the active level is output when timer output is disabled when the ppg output function has been selected. to2 tm2 count value 0h cr20 cr21 cr21 cr20 347 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9 examples of use 11.9.1 operation as interval timer (1) when timer counter 2 (tm2) is made free-running and a fixed value is added to the compare register (cr2n: n = 0, 1) in the interrupt service routine, tm2 operates as an interval timer with the added fixed value as the cycle (see figure 11-35 ). the control register settings are shown in figure 11-36, the setting procedure in figure 11-37, and the processing in the interrupt service routine in figure 11-38. figure 11-35. interval timer operation (1) timing remark interval = n x/f xx 1 n ffh, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 mod (2n) intc20 interrupt request tm2 count value 0h ffh ffh compare register (cr20) n timer start mod (3n) mod (4n) n mod (2n) mod (3n) interval interval interval rewritten by interrupt program rewritten by interrupt program rewritten by interrupt program 348 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-36. control register settings for interval timer operation (1) (a) prescaler mode register 1 (prm1) (b) capture/compare control register 2 (crc2) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock) (c) timer control register 1 (tmc1) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled to2 & to3 both toggle outputs 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled 349 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-37. interval timer operation (1) setting procedure figure 11-38. interval timer operation (1) interrupt request servicing interval timer (1) intc20 interrupt ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) set prm1 set count value in cr20 cr20 ? n set crc2 crc2 ? 10h set tmc1 ce2 ? 1 cmd2 ? 0 intc20 interrupt calculate timer value that will generate next interrupt cr20 ? cr20+n other interrupt service program reti 350 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.2 operation as interval timer (2) tm2 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 11-39 ). the control register settings are shown in figure 11-40, and the setting procedure in figure 11-41. figure 11-39. interval timer operation (2) timing remark interval = (n+1) x/f xx 0 n ffh, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 compare register (cr21) intc21 interrupt request tm2 count value 0h n n n count start clear clear interval interrupt acknowledged interrupt acknowledged interval 351 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-40. control register settings for interval timer operation (2) (a) prescaler mode register 1 (prm1) (b) capture/compare control register 2 (crc2) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock) (c) timer control register 1 (tmc1) 7 0 crc2 6 0 5 0 4 1 3 1 2 0 1 0 0 0 tm2 clearing by match of cr21 & tm2 contents enabled tm2 clearing by capture operation disabled to2 & to3 both toggle outputs 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled 352 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-41. interval timer operation (2) setting procedure interval timer set count value in cr21 cr21 ? n intc21 interrupt ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) set prm1 set crc2 crc2 ? 18h set tmc1 ce2 ? 1 cmd2 ? 0 353 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.3 pulse width measurement operation in pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (intp1) are measured. both the high-level and low-level widths of pulses input to the intp1 pin must be at least 3 system clocks (0.24 m s: f clk = 12.58 mhz); if shorter than this, the valid edge will not be detected and a capture operation will not be performed. as shown in figure 11-42, the timer counter 2 (tm2) value being counted is fetched into the capture register (cr22) in synchronization with a valid edge (specified as both rising and falling edges) in the intp1 pin input, and held there. the pulse width is obtained from the product of the difference value between the tm2 count value (d n ) fetched into and held in the cr22 on detection of the nth valid edge and the count value (d n-1 ) fetched and held on detection of n-1th valid edge, and the number of n-1th count clocks (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024). the control register settings are shown in figure 11-43, and the setting procedure in figure 11-44. figure 11-42. pulse width measurement timing remark dn: tm2 count value (n = 0, 1, 2, ...) x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 intp1 external input signal intp1 interrupt request tm2 count value 0h ffh ffh capture register (cr22) ovf2 d0 d1 count start d2 d3 capture (d1-d0) x/f xx (100h-d1+ d2) x/f xx (d3-d2) x/f xx cleared by software d1 d0 d2 d3 capture capture capture 354 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-43. control register settings for pulse width measurement (a) prescaler mode register 1 (prm1) (b) capture/compare control register 2 (crc2) 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock) (c) timer control register 1 (tmc1) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled (d) external interrupt mode register 0 (intm0) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled 7 intm0 6 5 1 4 1 3 2 1 0 0 both rising and falling edges specified as intp1 input valid edges 355 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-44. pulse width measurement setting procedure enable interrupts pulse width measurement ; specify both edges as intp1 input valid edges, release interrupt masking set crc2 crc2 ? 10h set tmc1 ce2 ? 1 cmd2 ? 0 initialize capture value buffer memory x0 ? 0 ; set 1 in bit 7 of tmc1 set normal mode (cmd2 = 0) intp1 interrupt set intm0 set mk0l figure 11-45. interrupt request servicing that calculates pulse width intp1 interrupt store capture value in memory x n+1 ? cr22 calculate pulse width yn = x n+1 ?xn reti 356 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.4 operation as pwm output in pwm output, pulses with the duty ratio determined by the value set in the compare register (cr2n: n = 0, 1) are output (see figure 11-46 ). this pwm output duty ratio can be varied in the range 1/256 to 255/256 in 1/256 units. the control register settings are shown in figure 11-47, the setting procedure in figure 11-48, and the procedure for varying the duty in figure 11-49. figure 11-46. example of timer/event counter 2 pwm signal output ffh or ffffh ffh or ffffh ffh or ffffh tm2 count value 0h to3 (when active-high) timer start 357 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-47. control register settings for pwm output operation (a) timer control register 1 (tmc1) (b) prescaler mode register 1 (prm1) (c) capture/compare control register 2 (crc2) (d) timer output control register (toc) (e) port 3 mode control register (pmc3) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag tm2 count enabled 7 1 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled to2 & to3 both pwm outputs 7 1 toc 6 0 5 4 3 2 1 0 to3 = active-high pmw signal output to3 pmw output enabled 7 1 pmc3 6 5 4 3 2 1 0 p37 pin set as to3 output 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) 358 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-48. pwm output setting procedure pwm output set crc2 crc2 ? 90h set toc set p34 pin to control mode pmc3.4 ? 1 start count ce2 ? 1 ; set bit 7 of tmc1 set count clock in prm1 set initial value in cr20 359 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-49. changing pwm output duty duty change preprocessing clear intc21 interrupt request flag cif21 ? 0 enable intc21 interrupts cmk21 ? 0 ; clear bit 0 of if0h ; clear bit 0 of mk0h intc21 interrupt duty change processing set duty value in cr21 disable intc21 interrupts cmk21 ? 1 ; set bit 0 of mk0h reti 360 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.5 operation as ppg output in ppg output, pulses with the cycle and duty ratio determined by the value set in the compare register (cr2n: n = 0, 1) are output (see figure 11-50 ). the control register settings are shown in figure 11-51, the setting procedure in figure 11-52, and the procedure for varying the duty in figure 11-53. figure 11-50. example of timer/event counter 2 ppg signal output cr21 cr20 cr21 cr20 cr21 cr20 tm2 count value 0h to2 (when active-high) timer start 361 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-51. control register settings for ppg output operation (a) timer control register 1 (tmc1) (b) prescaler mode register 1 (prm1) (c) capture/compare control register 2 (crc2) (d) timer output control register (toc) (e) port 3 mode control register (pmc3) 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag tm2 count enabled 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) 7 1 crc2 6 1 5 0 4 1 3 1 2 0 1 0 0 0 cleared by match of tm2 & cr21 clearing when tm2 is captured in cr22 disabled to2 = ppg output 7 toc 6 5 1 4 0 3 2 1 0 to2 = active-high ppg signal output to2 ppg output enabled 7 pmc3 6 1 5 4 3 2 1 0 p36 pin set as to2 output 362 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-52. ppg output setting procedure ppg output set crc2 crc2 ? d8h set p34 pin to control mode pmc3.6 ? 1 start count ce2 ? 1 set toc ; set bit 7 of tmc1 set count clock in prm1 set cycle in cr21 set duty in cr21 363 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-53. changing ppg output duty duty change preprocessing clear intc20 interrupt request flag cif20 ? 0 ; clear bit 3 of if0h enable intc20 interrupts cmk20 ? 0 ; clear bit 3 of mk0h intc20 interrupt duty change processing set duty value in cr20 disable intc20 interrupts cmk20 ? 1 ; set bit 3 of mk0h reti 364 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.6 operation as external event counter an external event counter counts clock pulses (ci pin input pulses) input from off-chip. as shown in figure 11-54, the value of timer counter 2 (tm2) is incremented in synchronization with a ci pin input valid edge (specified as rising edge only). figure 11-54. external event counter operation (single edge) ci pin input tm2 n+1 n+2 n remark the tm2 value is one less than the number of input clock pulses. the control register settings when tm2 operates as an external event counter are shown in figure 11-55, and the setting procedure in figure 11-56. 365 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-55. control register settings for external event counter operation (a) prescaler mode register 1 (prm1) (b) external interrupt mode register 0 (intm0) (c) timer control register 1 (tmc1) figure 11-56. external event counter operation setting procedure event counter ; set 1 in bit 7 of tmc1 set prm1 prm1 ? 0f h start count ce2 ? 1 specify ci pin input valid edge 7 1 prm1 6 1 5 1 4 1 3 0 2 1 0 external clock input (c1) specified 7 0 intm0 6 1 5 4 3 2 1 0 rising edge specified as ci input valid edge 7 1 tmc1 6 0 5 0 4 0 3 2 1 00 0 normal mode overflow flag count operation enabled 366 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.9.7 operation as one-shot timer after timer counter 2 (tm2) is started, it operates as a one-shot pulse that generates a single interrupt after the preset count time (see figure 11-57 ). the second and subsequent one-shot timer operations can be started by clearing the ovf2 bit of timer control register 1 (tmc1). the control register settings are shown in figure 11-58, the setting procedure in figure 11-59, and the procedure for starting the one-shot timer from the second time onward in figure 11-60. figure 11-57. one-shot timer operation ffh or ffffh cr21 value count start ce2 ? 1 clear ovf2 ? 0 tm2 count value 0h intc21 ovf2 367 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-58. control register settings for one-shot timer operation (a) timer control register 1 (tmc1) (b) prescaler mode register 1 (prm1) (c) capture/compare control register 2 (crc2) 7 ce2 tmc1 6 ovf2 5 1 4 0 3 2 1 0 one-shot timer mode 7 prs23 prm1 6 prs22 5 prs21 4 prs20 3 0 2 1 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024, or external clock) 7 0 crc2 6 0 5 0 4 1 3 0 2 0 1 0 0 0 tm2 clearing disabled 368 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-59. one-shot timer operation setting procedure one-shot timer set one-shot timer mode cmd2 ? 1 ; set 1 in bit 7 of tmc1 set prm1 set count value in cr21 cr21 ? n set crc2 crc2 ? 10h start count ce2 ? 1 intc21 interrupt ; set 1 in bit 5 of tmc1 figure 11-60. one-shot timer operation start procedure from second time onward one-shot timer restart set count value in cr21 cr21 ? n restart count ovf2 ? 0 intc21 interrupt ; clear bit 6 of tmc1 369 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 11.10 cautions (1) while timer/event counter 2 is operating (while the ce2 bit of the timer control register 1 (tmc1) is set), malfunctioning may occur if the contents of the following registers are rewritten. this is because it is undefined which takes precedence, change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting. therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following registers. ? prescaler mode register 1 (prm1) ? capture/compare control register 2 (crc2) ? timer output control register (toc) ? cmd2 bit of timer control register 1 (tmc1) (2) if the contents of the compare register (cr2n: n = 0, 1) match with those of tm2 when an instruction that stops timer counter 2 (tm2) operation is executed, the counting operation of tm2 stops, but an interrupt request is generated. in order not to generate the interrupt when stopping the operation of tm2, mask the interrupt in advance by using the interrupt mask register before stopping tm2. example program that may generate interrupt request program that does not generate interrupt request clr1 ce2 or mk0h, #03h or mk0h, #03h clr1 ce2 clr1 cif20 clr1 cif21 (3) up to 1 count clock is required after an operation to start timer/event counter 2 (ce2 ? 1) has been performed before timer/event counter 2 actually starts (refer to figure 11-61 ). for example, when using timer/event counter 2 as an interval timer, the first interval time is delayed by up to 1 clock. the second and those that follow are at the specified interval. figure 11-61. operation when counting is started count clock tm2 ce2 timing to start actual counting count start command (ce2 ? 1) by software 0 0 123 ? disables interrupt from timer/event counter 2 ? clears interrupt request flag for timer/ event counter 2 ? interrupt request from timer/event counter 2 occurs between these instructions ? ? ? ? 370 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 (4) while an instruction that writes data to the compare register (cr2n: n = 0, 1) is executed, coincidence between cr2n, to which the data is to be written, and timer counter 2 (tm2) is not detected. for example, if the contents of cr2n do not change before and after the writing, the interrupt request is not generated even if the value of tm2 coincides with the value of cr2n, nor does the timer output (ton + 2: n + 2 = 2, 3) change. write data to cr2n when timer/event counter 2 is executing count operation in the manner that the contents of tm2 do not match the value of cr2n before and after writing (e.g., immediately after an interrupt request has been generated because tm2 and cr2n have matched). (5) match between tm2 and compare register (cr2n: n = 0, 1) is detected only when tm2 is incremented. therefore, the interrupt request is not generated and timer output (ton + 2 : n + 2 = 2, 3) does not change even if the same value as tm2 is written to cr2n. (6) during ppg output, if the ppg cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the compare register (cr2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on match between timer counter 2 (tm2) and compare register (cr2n). use another method (for example, to poll the interrupt request flags by software with all the interrupts masked). (7) the output level of the ton (n = 2, 3) when the timer output is disabled (enton = 0: n = 2, 3) is the inverse value of the value set to the alvn (n = 2, 3) bits. note, therefore, that an active level is output when the timer output is disable d with the pwm output function or ppg output function selected. (8) when using timer/event counter 2 as an external event counter, the status where no valid edge is input cannot be distinguished from the status where only one valid edge has been input, by using tm2 alone (refer to figure 11-62 ), because the contents of tm2 are 0 in both the cases. to make a distinction, use the interrupt request flag of intp2, as shown in figure 11-63 (the intp2 pin is multiplexed with the ci pin and both the functions can be used at the same time). figure 11-62. example of the case where external event counter does not distinguish between one valid edge input and no valid edge input ci tm2 0 1 2 0 cannot be distinguished count start 371 chapter 11 timer/event counter 2 preliminary users manual u13987ej1v0um00 figure 11-63. to distinguish whether one or no valid edge has been input with external event counter (a) processing when count is started ; set ce2 to 1 ; clear pif2 to 0 clear intp2 interrupt request flag pif2 ? 0 start count ce2 ? 1 start count end (b) processing when count value is read ; number of input valid edges is set to a register count value read read tm2 contents a ? tm2 a ? a+1 end a = 0? pif2 = 1? ; check tm2 value. if 0, check interrupt request flag. ; check pif2 contents. if 1, valid edge is input. yes no yes no 372 preliminary users manual u13987ej1v0um00 [memo] 373 preliminary users manual u13987ej1v0um00 chapter 12 timer 3 12.1 function timer 3 is a 16- or 8-bit timer. in addition to its function as an interval timer, it can be used as a counter for clocked serial interface (csi) clock generati on. the interval timer generates internal interrupts at preset intervals. the interval setting range is shown in table 12-1. table 12-1. timer 3 intervals minimum interval maximum interval resolution 4/f xx 2 16 4/f xx 4/f xx (0.32 m s) (20.8 ms) (0.32 m s) 8/f xx 2 16 8/f xx 8/f xx (0.64 m s) (41.7 ms) (0.64 m s) 16/f xx 2 16 16/f xx 16/f xx (1.27 m s) (83.4 ms) (1.27 m s) 32/f xx 2 16 32/f xx 32/f xx (2.54 m s) (167 ms) (2.54 m s) 64/f xx 2 16 64/f xx 64/f xx (5.09 m s) (333 ms) (5.09 m s) 128/f xx 2 16 128/f xx 128/f xx (10.17 m s) (667 ms) (10.17 m s) 256/f xx 2 16 256/f xx 256/f xx (20.35 m s) (1.33 s) (20.35 m s) 512/f xx 2 16 512/f xx 512/f xx (40.70 m s) (2.67 s) (40.70 m s) 1,024/f xx 2 16 1,024/f xx 1,024/f xx (81.40 m s) (5.33 s) (81.40 m s) ( ): when f xx = 12.58 mhz chapter 12 timer 3 374 preliminary users manual u13987ej1v0um00 12.2 configuration timer 3 consists of the following registers: ? timer counter (tm3/tm3w) 1 ? compare register (cr30/cr30w) 1 the block diagram of timer 3 is shown in figure 12-1. figure 12-1. timer 3 block diagram f xx /1,024 f xx /512 f xx /256 f xx /128 f xx /64 f xx /32 f xx /16 f xx /8 f xx /4 f xx prs3 prs2 prs1 prs0 ce3 1/8 bw3 8 timer control register 0 (tmc0) internal bus internal bus compare register (cr30/cr30w) 16 16 timer counter 3 (tm3/tm3w) prescaler selector 8/16 8/16 reset match clear intc30 serial interface prescaler mode register 0 (prm0) 375 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 (1) timer counter 3 (tm3/tm3w) tm3/tm3w is a timer counter that count up using the count clock specified by the high-order 4 bits of prescaler mode register 0 (prm0). the count operation is stopped or enabled by the timer control register 0 (tmc0). in addition, an 8-bit mode (tm3) or 16-bit mode (tm3w) can be selected. tm3 can be read only with an 8/16-bit manipulation instruction. when reset is input, tm3 is cleared to 00h and the count is stopped. (2) compare register (cr30/cr30w) cr30/cr30w is an 8/16-bit register that hold the value that determines the interval timer frequency. if the cr30/cr30w contents match the contents of tm3/tm3w, the contents of tm3/tm3w is cleared automatically and an interrupt request (intc30) is generated. this compare register operates as cr30 in the 8-bit mode and cr30w in the 16-bit mode. cr30 can be read or written to with an 8/16-bit manipulation instruction. the contents of cr30 are undefined after reset input. (3) prescaler the prescaler generates the count clock from the internal system clock. the clock generated by the prescaler is selected by the selector, and is used as the count clock by tm3/tn3w to perform count operations. (4) selector the selector selects a signal resulting from dividing the internal clock or the edge detected by the edge detection circuit as the count clock of tm3/tm3w. chapter 12 timer 3 376 preliminary users manual u13987ej1v0um00 12.3 timer 3 control registers (1) timer control register 0 (tmc0) tmc0 controls the timer 3 timer counter 3 (tm3/tm3w) count operation by the high-order 4 bits (the low-order 4 bits control the count operation of timer/event counter 0 tm0). tmc0 can be read or written to with an 8-bit manipulation instruction. the format of tmc0 is shown in figure 12-2. reset input clears tmc0 to 00h. figure 12-2. timer control register 0 (tmc0) format 7 ce3 tmc0 6 0 5 0 4 bw3 3 ce0 2 ovf0 1 0 0 0 ce3 tm3/tm3w count operation control count operation stopped with count cleared count operation enabled 1 0 bw3 timer 3 bit length specification 8-bit operating mode 16-bit operating mode 1 0 countrols count operation of timer/event counter 0 tm0 (see figure 9-2 ). address after reset r/w r/w 00h 0ff5dh 377 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 (2) prescaler mode register 0 (prm0) prm0 specifies the count clock to timer 3 timer counter 3 (tm3/tm3w) by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/event counter 0 tm0). prm0 can be read and written with an 8-bit manipulation instruction. the format of the prm0 is shown in figure 12-3. reset input sets prm0 to 11h. figure 12-3. prescaler mode register 0 (prm0) format prs3 prs2 prs1 prs0 prs03 prs02 prs01 prs00 76543210 prm0 0ff5ch address 11h after reset r/w r/w prs3 0 0 0 0 0 0 0 0 1 1 specifies count clock to timer/event counter 0 tm0 (see figure 9-3 ). prs2 0 0 0 0 1 1 1 1 0 0 prs1 0 0 1 1 0 0 1 1 0 0 prs0 0 1 0 1 0 1 0 1 0 1 timer 3 tm3/tm3w count clock specification count clock [hz] specification resolution [ s] setting prohibited f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 setting prohibited 0.32 0.64 1.27 2.54 5.09 10.17 20.35 40.70 81.40 (f xx = 12.58 mhz) other than the above m chapter 12 timer 3 378 preliminary users manual u13987ej1v0um00 12.4 timer counter 3 (tm3) operation 12.4.1 basic operation timer 3 can operate in an 8-bit or 16-bit mode. these operation modes are selected by bit 4 (bw3) of timer control register 0 (tmc0) note . in the timer 3 count operation, the count-up is performed using the count clock specified by the high-order 4 bits of prescaler mode register 0 (prm0). when reset is input, timer counter 3 (tm3) is cleared to 0000h, and the count operation is stopped. count operation enabling/disabling is controlled by bit 7 (ce3) of timer control register 0 (tmc0) (the high-order 4 bits of tmc0 control timer 3 operation). when the ce3 bit is set (to 1) by software, the contents of tm3 are immediately cleared on the first count clock, and then the count-up operation is performed. when the ce3 bit is cleared (to 0), tm3 becomes 0h immediately, and match signal generation is stopped. if the ce3 bit is set (to 1) again when it is already set (to 1), tm3 continues the count operation without being cleared. note unless there functional differences are found, the register names in the 8-bit mode are used. in the 16-bit mode, the register names tm3 and cr30 are tm3w and cr30w, respectively. figure 12-4. basic operation in 8-bit operation mode (bw3 = 0) (a) count started ? count stopped ? count started 0h 0h 1h 2h 0fh 10h 11h 0h 0h 1h count started ce3 ? 1 count clock count started ce3 ? 1 tm3 ce3 count stopped ce3 ? 0 (b) when ??is written to the ce3 bit again after the count starts count started ce3 ? 1 rewrite ce3 ? 1 count clock tm3 ce3 0h 0h 1h 2h 3h 4h 5h 6h 379 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 figure 12-5. basic operation in 16-bit operation mode (bw3 = 1) (a) count started ? count stopped ? count started 0h 0h 1h 2h ffh 100h 101h 0h 0h 1h count started ce3 ? 1 count clock count started ce3 ? 1 tm3w ce3 count stopped ce3 ? 0 (b) when ??is written to the ce3 bit again after the count starts count started ce3 ? 1 rewrite ce3 ? 1 count clock tm3w ce3 0h 0h 1h 2h 3h 4h 5h 6h chapter 12 timer 3 380 preliminary users manual u13987ej1v0um00 12.4.2 clear operation (1) clear operation by match with compare register (cr30) timer counter 3 (tm3) is cleared automatically after a match with the compare register (cr30). when a clearance source arises, tm3 is cleared to 0h on the next count clock. therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives. figure 12-6. tm3 clearance by match with compare register (cr30) count clock tm3 n 0 1 n-1 compare register (cr30) n tm3 and cr30 match cleared here (2) clear operation by ce3 bit of timer control register 0 (tmc0) tm3 is also cleared when the ce3 bit of tmc0 is cleared (to 0) by software. the clear operation is performed following clearance (to 0) of the ce3 bit in the same way. 381 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 figure 12-7. clear operation when ce3 bit is cleared (0) (a) basic operation count clock tm3 n 0 n-1 ce3 (b) restart before count clock is input after clearance count clock tm3 n n-1 ce3 0 12 if the ce3 bit is set (to 1) before this count clock, the count starts from 0 on this count clock 0 (c) restart when count clock is input after clearance count clock tm3 n 0 n-1 ce3 0 01 if the ce3 bit is set (to 1) from this count clock onward, the count starts from 0 on the count clock after the ce3 bit is set (to 1). chapter 12 timer 3 382 preliminary users manual u13987ej1v0um00 12.5 compare register operation timer 3 performs compare operations in which the value set in the compare register (cr30) is compared with the timer counter 3 (tm3) count value. if the count value of tm3 matches the preset cr30 value as the result of the count operation, an interrupt request (intc30) is generated. after a match, the tm3 contents are cleared automatically, and therefore tm3 functions as an interval timer that repeatedly counts up to the value set in the cr30. figure 12-8. compare operation cr30 tm3 count value 0h intc30 interrupt request count start ce ? 1 clear (match) clear (match) cr30 383 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 12.6 example of use operation as interval timer: tm3 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see figure 12-9 ). tm3 can also be used for baud rate generation. this interval timer can count up to a maximum of 20.85 ms at the minimum resolution of 0.32 m s, and up to 5.33 s at the maximum resolution of 81.40 m s (internal system clock f xx = 12.58 mhz). the control register settings are shown in figure 12-10, and the setting procedure in figure 12-11. figure 12-9. interval timer operation timing n count start clear clear n interrupt acknowledgment interrupt acknowledgment interval interval tm3 count value 0h intc30 interrupt request compare register (cr30) n remark interval = (n+1) x/f xx 0 n ffh, x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024 chapter 12 timer 3 384 preliminary users manual u13987ej1v0um00 figure 12-10. control register settings for interval timer operation prescaler mode register 0 (prm0) 7 prs3 prm0 6 prs2 5 prs1 4 prs0 3 0 2 0 1 0 0 0 count clock specification (x/f xx ; x = 4, 8, 16, 32, 64, 128, 256, 512, 1,024) figure 12-11. interval timer operation setting procedure interval timer ; set 1 in bit 7 of tmc0 set prm0 set count value in cr30 cr30 ? n start count ce ? 1 intc30 interrupt 385 chapter 12 timer 3 preliminary users manual u13987ej1v0um00 ? disables interrupts from timer 3 ? clears timer 3 interrupt request flag ? interrupt request generated by timer 3 here 12.7 cautions (1) there is a possibility of malfunction if the next register contents are rewritten while the timer 3 is operating (when the ce3 bit of the timer control register 0 (tmc0) is set). the malfunction occurs as there is no defined order of priority in the event of contention between the timings at which the hardware function changes due to a register rewrite and the status changes in the function prior to the rewrite. when the contents of the following register are rewritten, counter operations must be stopped first to ensure stability. ? prescaler mode register 0 (prm0) (2) if the compare register (cr30) and timer counter 3 (tm3) contents match when an instruction that stops tm3 operation is executed, the tm3 count operation stops, but an interrupt request is generated. if you do not want an interrupt to be generated when tm3 operation is stopped, interrupts should be masked by means of interrupt the mask register before stopping the tm3. example program in which an interrupt request may be program in which an interrupt request is not generated generated clr1 ce3 set1 cmk30 set1 cmk30 clr1 ce3 clr1 cif30 (3) there is a delay of up to one count clock between the operation that starts a timer 3 (ce3 ? 1) and the actual start of the timer 3 (see figure 12-12 ). for example, if a timer 3 is used as an interval timer, the first interval will be extended by up to one clock. the second and subsequent intervals will be as specified. figure 12-12. operation when counting is started ? ? ? ? count clock tm3 0 ce3 03 1 2 timing at which count actually starts software count start command (ce3 ? 1) chapter 12 timer 3 386 preliminary users manual u13987ej1v0um00 (4) while an instruction that writes data to the compare register (cr30) is executed, match between cr30, to which the data is to be written, and timer counter 3 (tm3) is not detected. write data to cr30 when timer 3 is executing count operation so that the contents of tm3 do not match the value of cr30 before and after writing (e.g., immediately after an interrupt request has been generated because tm3 and cr30 have matched). (5) match between tm3 and compare register (cr30) is detected only when tm3 is incremented. therefore, the interrupt request is not generated even if the same value as tm3 is written to cr30. 387 preliminary users manual u13987ej1v0um00 chapter 13 watchdog timer the watchdog timer is a timer that detects inadvertent program loops. watchdog timer interrupts are used to detect system or program errors. for this purpose, instructions that clear the watchdog timer (start the count) within a given period are inserted at various places in a program. if an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (intwdt) is generated and a program error is reported. 13.1 configuration the watchdog timer block diagram is shown in figure 13-1. figure 13-1. watchdog timer block diagram watchdog timer clear signal f clk /2 17 f clk /2 19 f clk /2 20 f clk /2 21 intwdt selector f clk 388 chapter 13 watchdog timer preliminary users manual u13987ej1v0um00 13.2 watchdog timer mode register (wdm) wdm is an 8-bit register that controls the watchdog timer operation. to prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements of 1. if the 3rd and 4th bytes of the operation code are not mutual complements of 1, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a, and wdm, #byte, set1 wdm.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. after a system reset (reset input), once the watchdog timer has been started (by setting (to 1) the run bit), the wdm contents cannot be changed. the watchdog timer can only be stopped by a reset, but can be cleared at any time with a dedicated instruction. wdm can be read at any time by a data transfer instruction. reset input clears wdm to 00h. the wdm format is shown in figure 13-2. 389 chapter 13 watchdog timer preliminary users manual u13987ej1v0um00 figure 13-2. watchdog timer mode register (wdm) format run 0 0 prc 0 wdi2 wdi1 0 76543210 wdm ffc2h address 00h after reset r/w r/w wdi2 0 0 1 1 overflow time [ms] f clk = 12.58 mhz 2 17 /f clk (10.4) 2 19 /f clk (41.7) 2 20 /f clk (83.4) 2 21 /f clk (166.7) wdi1 0 1 0 1 remark f clk : internal system clock frequency prc 0 1 watchdog timer interrupt request priority specification watchdog timer interrupt request < nmi pin input interrupt request run 0 1 watchdog timer operation specification watchdog timer stopped clear watchdog timer and start count watchdog timer interrupt request > nmi pin input interrupt request cautions 1. the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). 2. the same value should be written each time in writes to the wdm to set (to 1) the run bit. the contents written at the first time cannot be changed even if a different value is written. 3. once the run bit has been set (to 1), it cannot be reset (to 0) by software. 390 chapter 13 watchdog timer preliminary users manual u13987ej1v0um00 13.3 operation 13.3.1 count operation the watchdog timer is cleared, and the count started, by setting (to 1) the run bit of the watchdog timer mode register (wdm). when overflow time specified by the wdm2 and wdm1 bits of wdm has elapsed after the run bit has been set (to 1), a non-maskable interrupt (intwdt) is generated. if the run bit is set (to 1) again before the overflow time elapses, the watchdog timer is cleared and the count operation is started again. 13.3.2 interrupt priorities the watchdog timer interrupt (intwdt) is a non-maskable interrupt. other non-maskable interrupts are interrupts from the nmi pin (nmi). the order of acknowledgment when an intwdt interrupt and nmi interrupt are generated simultaneously can be specified by the setting of bit 4 of the watchdog timer mode register (wdm). even if intwdt is generated while the nmi processing program is executed when nmi acknowledgement is specified to take precedence, intwdt is not acknowledged until completion of execution of the nmi processing program. 391 chapter 13 watchdog timer preliminary users manual u13987ej1v0um00 13.4 cautions 13.4.1 general cautions on use of watchdog timer (1) the watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program loops. therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing to be performed that will restore the normal state or establish a stable state and then stop the operation. (2) the watchdog timer cannot detect inadvertent program loops in the following cases. <1> if watchdog timer clearance is performed in the timer interrupt service program <2> if cases where an interrupt request or macro service is held pending (see 23.9 ) occur consecutively <3> if the watchdog timer is cleared periodically when inadvertent program looping is due to an error in the program logic (if each module of the program functions normally but the overall program does not) <4> if the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program loop occurs <5> if the stop mode or idle mode is entered as the result of an inadvertent program loop <6> if watchdog timer inadvertent program loop also occurs in the event of cpu inadvertent program loop due to external noise in cases <1>, <2>, and <3> the program can be amended to allow detection to be performed. in case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. similarly, in case <5>, the stop mode or idle mode cannot be set unless a 4-byte dedicated instruction is used. for state <2> to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a specific pattern (e.g. bt pswl.bit, $$, etc.). therefore, the establishment of state <2> as the result of <4>, <5> or an inadvertent program loop is likely to be extremely rare. 392 chapter 13 watchdog timer preliminary users manual u13987ej1v0um00 13.4.2 cautions on m pd784938 subseries watchdog timer (1) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). (2) the same value should be written each time in writes to the watchdog timer mode register (wdm) to set (to 1) the run bit. the contents written at the first time cannot be changed even if a different value is written. (3) once the run bit has been set (to 1), it cannot be reset (to 0) by software. 393 preliminary users manual u13987ej1v0um00 chapter 14 watch timer two types of count clocks can be input to the watch timer: main clock (12.58 mhz (max.)) and watch clock (32.768 khz). these count clocks can be selected by the control register. the watch clock is input only to the watch timer, and not to the cpu and other peripheral circuits. therefore, the operating speed of the cpu cannot be slowed down by using the watch clock. the watch timer generates an interrupt signal with a 0.5-second interval (intw) by dividing the count clock. at the same time, it also sets an interrupt request flag (wif: bit 7 of interrupt control register (wic)). the intw generation interval can be changed to about 1 ms by changing the mode (fast forward mode: 512 times faster than the normal mode). also, the intw generation interval can be set to 15.6 ms. when the main clock is selected as the count clock, the watch timer stops at standby in stop mode. however, it continues operating in the idle and halt modes. when the watch clock is selected as the count clock, the watch timer can continue operating in any standby mode (it means any of stop, idle, and halt modes). the operation of the watch clock oscillator is controlled by the watch timer mode register (wm). figure 14-1 shows the format of wm. figure 14-1. watch timer mode register (wm) format wm7 wm6 0 wm4 wm3 wm2 0 0 76543210 wm 0ff6fh address 00h after reset r/w r/w wm3 0 1 watch timer operation control clears division counter and stops counting starts operation of division counter wm6 0 1 watch timer operation clock specification main clock watch clock wm7 0 1 watch clock oscillator operation control stops watch clock oscillator operation watch clock oscillator wm4 0 1 0 1 watch timer operation mode normal watch mode (generates intw at 0.5 s intervals) medium-fast forward mode (32 times faster than normal mode, generates intw at 15.6 ms intervals) fast forward mode (512 times faster than normal mode, generates intw at 0.98 ms intervals) wm2 0 0 1 1 caution the time from when the watch timer is started up until the first intw occurs is less than 0.5 seconds. this time becomes 0.5 seconds from the second and subsequent intw occurrences. 394 chapter 14 watch timer preliminary users manual u13987ej1v0um00 the watch timer of the m pd784938 does not have a buzzer output function. table 14-1. relation between count clock and watch timer operation count clock selection normal operation mode type of standby mode halt mode stop mode idle mode main clock operable operable stopped operable note watch clock operable operable operable operable note when bit 3 (wm3) of the watch timer mode register (wm) is set to 1 and bit 6 (wm6) of the same register is set to 0, main clock operation in the idle mode is enabled. the watch timer consists of a divider circuit that divides the count clock by three, and a counter that divides the output signal of the divider circuit by 2 14 . as the count clock, select the signal obtained by dividing the internal system clock by 128, or the signal from the watch clock oscillator. figure 14-2. block diagram of watch timer 1234 10 11 12 13 14 56789 counter counter counter 1/3 divider sel sel s e l sel wm.3 reset watch clock oscillator on/off wm.7 wm.6 wm.2 wm.4 (set by instruction when main clock is 12.58 mhz) stbc.7 intw 1 0 0 1 0 0 1 main clock f xx /128 caution the interval until the first intw is generated is not 0.5 second after the operation has been enabled. 395 preliminary users manual u13987ej1v0um00 chapter 15 pwm output unit the m pd784938 incorporates two 12-bit resolution pwm (pulse width modulation) output circuit channels. the active level of the pwm output pulses can be selected as high or low. the pwm output ports consist of dedicated pins. 15.1 pwm output unit configuration the pwm output unit configuration is shown in figure 15-1. figure 15-1. pwm output unit configuration internal bus 16 15 87 43 0 pwmn 8 pwpr prescaler f clk 8 8-bit down counter f pwmc 1/256 4-bit counter pwm pulse generator 4 reload control reload reload 8 pwmc output control circuit pwmn remark n = 0, 1 chapter 15 pwm output unit 396 preliminary users manual u13987ej1v0um00 (1) 8-bit down counter generates the basic pwm signal timing. (2) pwm pulse generator (including 4-bit counter) controls addition of extra pulses and generates the pwm pulses to be output. (3) reload control controls 8-bit down counter and 4-bit count modulo value reloading. (4) output control circuit controls the active level of the pwm signal. (5) prescaler scales f clk , and generates the reference clock. 397 chapter 15 pwm output unit preliminary users manual u13987ej1v0um00 15.2 pwm output unit control registers 15.2.1 pwm control register (pwmc) pwmc is an 8-bit register that controls the operating status of the pwm output pins (pwmn: n = 0, 1). pwmc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. its format is shown in figure 15-2. when reset is input, pwmc is set to 05h, the pwmn pin is disabled from outputting signals. figure 15-2. pwm control register (pwmc) format 7 syn1 pwmc 6 0 5 syn0 4 0 3 en1 2 alv1 1 en0 0 alv0 address after reset r/w r/w 05h 0ff70h alvn pwmn pin pwm active level specification (n = 0, 1) active-low active-high 1 0 enn pwmn pin pwm output control output disabled pwm output enabled synn pwm pulse width rewrite cycle specification rewritten every 16 pwm cycles (2 12 /f pwmc ) rewritten every pwm cycle (2 8 /f pwmc ) 1 0 1 0 chapter 15 pwm output unit 398 preliminary users manual u13987ej1v0um00 15.2.2 pwm prescaler register (pwpr) pwpr is an 8-bit register that selects the pwm output circuit operating clock (f pwmc ). pwpr can be read or written to with an 8-bit manipulation instruction. its format is shown in figure 15-3. when reset is input, pwpr is cleared to 00h, and f clk is selected as f pwmc for both channels. figure 15-3. pwm prescaler register (pwpr) format 0 pwp12 pwp11 pwp10 0 pwp02 pwp01 pwp00 76543210 pwpr 0ff71h address 00h after reset r/w r/w pwpn2 0 0 0 0 1 pwmn operating clock (f pwmc ) f clk f clk /2 f clk /3 f clk /4 setting prohibited pwpn1 0 0 1 1 0 pwpn0 0 1 0 1 0 pwmn repetition frequency (f clk = 12.58 mhz) other than the above f clk /256 (49.14 khz) f clk /512 (24.58 khz) f clk /768 (16.38 khz) f clk /1,028 (12.28 khz) (n = 0, 1) 15.2.3 pwm modulo registers (pwm0, pwm1) the pwm modulo register (pwmn: n = 0, 1) is a 16-bit register that determines the pwm pulse width. reads/writes by a 16-bit manipulation instruction are possible for data setting. the contents of bits 4 to 15 of the pwmn determines the 12-bit pwm pulse width (12-bit resolution). bits 3 to 0 have no meaning, and pwm output is not affected whether 1 or 0 is written to these bits. when reset is input, the pwmn content are undefined, and therefore data must be set by the program before pwm output is enabled. caution a value between 0000h and 00ffh should not be set in the pwm modulo registers (pwmn: n = 0, 1). a value between 0100h and ffffh should be set in the pwmn registers. the pwm signal duty values that can be output are 17/4,096 to 4,096/4,096. 399 chapter 15 pwm output unit preliminary users manual u13987ej1v0um00 15.3 pwm output unit operation 15.3.1 basic pwm output operation the pwm pulse output duty is determined by the value set in bits 4 to 15 of the pwm modulo register (pwmn: n = 0, 1) as shown below. pwm pulse output duty = (value of pwmn bits 4 to 15) note + 1 4,096 note 16 (value of pwmn bits 4 to 15) 4095 the pwm pulse output repetition frequency is the frequency obtained by division-by-256 of the pwm clock f clk /1 to f clk /4 set by the pwm prescaler register (pwpr) (=f pwmc /256), and the minimum pulse width is 1/f pwmc . in pwm pulse output, 12-bit resolution is achieved by repeating output of a f pwmc /256 repetition frequency 8-bit resolution pwm signal 16 times. the addition of extra pulses (1/f pwmc ) to the 8-bit resolution pwm pulses determined by bits 8 to 15 of the pwmn every cycle is controlled in accordance with the value of bits 4 to 7 of the pwmn to implement a pwm pulse signal once every 16 cycles. figure 15-4. basic pwm output operation pwm signal note one 12-bit pwm signal cycle note 8-bit resolution per pwm pulse cycle chapter 15 pwm output unit 400 preliminary users manual u13987ej1v0um00 15.3.2 pwm pulse output enabling/disabling when pwm pulses are output, the enn (n = 0, 1) bits of the pmc register are set (to 1) after data is set in the pwm prescaler register (pwpr) and pwm modulo register (pwmn: n = 0, 1). as a result, pwm pulses with the active level specified by alvn (n = 0, 1) bit of the pwm control register (pwmc) are output from the pwm output pin. when the enn bits of the pwmc are cleared (to 0), the pwm output unit immediately stops the pwm output operation. 15.3.3 pwm pulse active level specification the alvn (n = 0, 1) bit of the pwm control register (pwmc) specify the active level of pwm pulses output from the pwm output pins. when alvn bit is set (to 1), active-high level pulses are output, and when cleared (to 0), active-low level pulses are output. when alvn bit is rewritten, the pwm active level changes immediately. pwm output active level setting and pin states are shown in figure 15-5. figure 15-5 shows the case where alvn bit is switched when the enn (n = 0, 1) bit of the pwmc is set (to 1) and pwm output is enabled. the pin state does not change if alvn is rewritten when enn bit is in the cleared (to 0) state. figure 15-5. pwm output active level setting alvn pwmn (active-high) (active-low) (alvn bit rewrite) remark enn = 1 (n = 0, 1) 401 chapter 15 pwm output unit preliminary users manual u13987ej1v0um00 15.3.4 pwm pulse width rewrite cycle specification the start of pwm output and pulse width changes are performed in synchronization either with every 16 pwm pulse cycles (2 12 /f pwmc ) or with every pwm pulse cycle (2 8 /f pwmc ). this pwm pulse width rewrite cycle specification is performed by means of the synn bits of the pwm control register (pwmc). when the synn bit is cleared (to 0), a pulse width change is performed every 16 pwm pulse cycles (2 12 /f pwmc ). it therefore takes a maximum of 2 12 clocks (326 m s when f pwmc = 12.58 mhz) until a pulse of a width corresponding to the data written in the pwm modulo register (pwmn: n = 0, 1) is output. an example of the pwm output timing at this time is shown in figure 15-6. when the synn bit is set (to 1), on the other hand, a pulse width change is performed every pwm pulse cycle (2 8 /f pwmc ). in this case, it takes a maximum of 2 8 clocks (20.4 m s when f pwmc = 12.58 mhz) until a pulse of a width corresponding to the data written in the pwmn is output. however, caution is required since, if the pwm pulse rewrite cycle is specified as every 2 8 /f pwmc , (if the synn bit is set (to 1)), the obtained pwm pulse precision is between 8 bits and 12 bits, and is lower than when the pwm pulse rewrite cycle is specified as 2 12 /f pwmc . an example of the pwm output timing when the rewrite timing is 2 8 /f pwmc is shown in figure 15-7. figure 15-6. pwm output timing example 1 (pwm pulse width rewrite cycle = 2 12 /f pwmc ) pwm output pin pwmn contents pwm output enabled pwm pulse width switching timing pwm pulse width switching timing pwm pulse width switching timing pwmn rewrite nm 16 pwm pulse cycles 16 pwm pulse cycles cautions 1. pulse width rewriting is performed every pwm pulse cycle. 2. the pwm pulse precision is 12 bits. chapter 15 pwm output unit 402 preliminary users manual u13987ej1v0um00 figure 15-7. pwm output timing example 2 (pwm pulse width rewrite cycle = 2 8 /f pwmc ) 1 pwm pulse cycle pwm output pin pwmn contents pwm output enabled pwmn rewrite pwmn rewrite pwmn rewrite pwm pulse width switching timing ni m n cautions 1. pulse width rewriting is performed every pwm pulse cycle. 2. the pwm pulse precision is between 8 and 12 bits. remark l, m, and n mean the pwmn contents. 15.4 caution a value between 0000h and 00ffh should not be set in the pwm modulo registers (pwmn: n = 0, 1). a value between 0100h and ffffh should be set in the pwmn. the pwm signal duty values that can be output are 17/4,096 to 4,096/ 4,096. 403 preliminary users manual u13987ej1v0um00 chapter 16 a/d converter the m pd784938 incorporates an analog/digital (a/d) converter with 8 multiplexed analog inputs (ani0 to ani7). the successive approximation conversion method is used, and the conversion result is held in the 8-bit a/d conversion result register (adcr). this allows fast, high-precision conversion to be performed. there are two modes for starting a/d conversion, as follows: ? hardware start: conversion started by trigger input (intp5). ? software start: conversion started in accordance with a/d converter mode register (adm) bit setting. after start-up, there are two operation modes, as follows: ? scan mode: multiple analog inputs are selected in order, and conversion data is obtained from all pins. ? select mode: one pin is used as the analog input, and conversion values are obtained in succession. stoppage of all the above modes and conversion operations is specified by the adm register. when the conversion result is transferred to the adcr, an intad interrupt request is generated. this allows conversion values to be transferred to memory in succession by means of macro service. cautions 1. apply a voltage same as the supply voltage (av dd ) to the reference voltage input pin (av ref1 ) of this product. 2. when port 7 is used for both output port and a/d input, do not write to output port during a/d conversion operations. 16.1 configuration the a/d converter configuration is shown in figure 16-1. 404 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 figure 16-1. a/d converter block diagram internal bus 8 8 a/d converter mode register (adm) reset 8 successive approximation register (sar) edge detection circuit intp5 ani7 ani6 ani5 ani4 ani3 ani2 ani1 ani0 sample & hold circuit tap selector av ref1 r/2 r r/2 voltage comparator intad control circuit conversion trigger trigger enable av ss a/d conversion result register (adcr) series resistor string input selector a/d current cut select register (iead) connection control av dd 405 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 cautions 1. a capacitor should be connected between the analog input pins (ani0 to ani7) and av ss , and between the reference voltage input pin (av ref1 ) and av ss to prevent malfunction due to noise. be sure to connect the capacitor as closely to ani0 through ani7 and av ref1 as possible. figure 16-2. example of capacitor connection on a/d converter pins analog input reference voltage input 100 to 500 pf ani0 to ani7 av ref1 av ss m pd784938 2. a voltage outside the range av ss to av ref1 should not be applied to pins used as a/d converter input pins. see 16.6 cautions for details. (1) input circuit the input circuit selects the analog input in accordance with the specification of the a/d converter mode register (adm), and sends the analog input to the sample & hold circuit according to the operation mode, (2) sample & hold circuit the sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input in the process of a/d conversion. (3) voltage comparator the voltage comparator determines the voltage difference between the analog input and the series resistor string value tap. (4) series resistor string the series resistor string is used to generate voltages that match the analog inputs. the series resistor string is connected between the a/d converter reference voltage pin (av ref1 ) and the a/d converter gnd pin (av ss ). to provide 256 equal voltage steps between the two pins, it is made up of 255 equal resistors and two resistors with half that resistance value. the series resistor string voltage tap is selected by a tap selector controlled by the sar successive approximation register. 406 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (5) sar: successive approximation register sar is an 8-bit register in which the data for which the series resistor string voltage tap value matches the analog input voltage value is set bit by bit starting from the most significant bit (msb). when data has been set up to the least significant bit (lsb) of the sar (when a/d conversion is completed), the sar contents (conversion result) are stored in the a/d conversion result register (adcr). (6) adcr: a/d conversion result register adcr is an 8-bit register that holds the a/d conversion result. the conversion result is loaded into this register from the successive approximation register (sar) each time a/d conversion finishes. the contents of this register approximation are undefined when reset is input. (7) edge detection circuit the edge detection circuit detects a valid edge from the interrupt request input pin (intp5) input, and generates an external interrupt request signal (intp5) and a/d conversion operation external trigger. the intp5 pin input valid edge is specified by external interrupt mode register 1 (intm1) (see figure 22-2 ). external trigger enabling/disabling is set by means of the a/d converter mode register (adm) (see 16.2 a/d converter mode register (adm) ). 407 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.2 a/d converter mode register (adm) adm is an 8-bit register that controls a/d converter operations. adm register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. its format is shown in figure 16-3. bit 0 (ms) controls the operation mode. bits 1, 2, and 3 (ani0, 1, 2) select the analog inputs for a/d conversion. bit 5 (scmd) controls the a/d conversion operation in scan mode. bit 6 (trg) enables external synchronization of the a/d conversion operation. if the trg bit is set (to 1) when the cs bit is set (to 1), the conversion operation is initialized with each input of a valid edge as an external trigger to the intp5 pin. when the trg bit is cleared (to 0), the conversion operation is performed without regard to the intp5 pin. bit 7 (cs) controls the a/d conversion operation. when the cs bit is set (to 1) the conversion operation is started, and when cleared (to 0), all conversion operations are stopped even if conversion is in progress. in this case, the a/d conversion result register (adcr) is not updated and an intad interrupt request is not generated. also, the power supply to the voltage comparator is stopped, and the a/d converter consumption current is reduced. reset input clears adm to 00h. caution when the stop mode or idle mode is used, the consumption current should be reduced by clearing (to 0) the cs bit before entering the stop or idle mode. if the cs bit remains set (to 1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter consumption current will not be reduced. 408 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 figure 16-3. a/d converter mode register (adm) format cs trg scmd fr anis2 anis1 anis0 ms 76543210 adm 0ff68h address 00h after reset r/w r/w anis2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a/d conversion operating mode setting scan mode (0/1) anis1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 anis0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ms 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ani0 input scanned input ani0 & ani1 scanned input ani0 to ani2 scanned input ani0 to ani3 scanned input ani0 to ani4 scanned input ani0 to ani5 scanned input ani0 to ani6 scanned input ani0 to ani7 scanned ani0 input selected ani1 input selected ani2 input selected ani3 input selected ani4 input selected ani5 input selected ani6 input selected ani7 input selected fr 0 1 conversion speed control (f clk = 12.58 mhz) 180/f clk (19.1 s) 120/f clk (9.6 s) low-speed conversion high-speed conversion scmd 0 1 0 1 scan mode selection scan mode 0 (no delay control) scan mode 1 (delay control) select mode setting prohibited ms 0 0 1 1 trg 0 1 external trigger control external trigger disabled external trigger enabled cs 0 1 a/d conversion operation control stop a/d conversion operation start a/d conversion operation m m select mode 409 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 caution once the a/d converter starts operating, conversion operations are performed repeatedly until the cs bit of the a/d converter mode register (adm) is cleared (to 0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., when a/d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm (cs bit must be set (to 1)) <2> interrupt request flag (adif) clearance (to 0) <3> interrupt mask flag or interrupt service mode flag setting operations <1> to <3> should not be divided by an interrupt or macro service. when scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one a/d conversion operation. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (to 0) the cs bit of the adm. <2> interrupt request flag (adif) clearance (to 0). <3> interrupt mask flag or interrupt service mode flag setting <4> write to the adm 410 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.3 a/d current cut select register (iead) iead is a register that selects whether av dd and av ref1 are connected. in a system where av dd = av ref1 and a high accuracy is not required, open the av ref1 pin. in the normal mode, connect av dd and av ref1 . in the standby mode, the connection between these pins is disconnected to lower the power consumption. iead is set with an 8-bit or 1-bit manipulation instruction. reset input clears iead to 00h. figure 16-4. a/d current cut select register (iead) format 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 iead0 address 0ff6ch after reset 00h r/w r/w iead0 0 controls connection between av dd and av ref1 disconnects av dd and av ref1 1 connects av dd and av ref1 iead symbol figure 16-5. a/d current cut select register function av dd av ref1 av ss connection control power consumption can be lowered by controlling connection between av dd and av ref1 with iead0. av dd av ref1 (open) av ss av dd 1 av ref1 or when high accuracy is required av dd = av ref1 and when high accuracy is not required . . 411 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.4 operation 16.4.1 basic a/d converter operation (1) a/d conversion operation procedure a/d conversion is performed by means of the following procedure: (a) analog pin selection and operation mode specification are set with the a/d converter mode register (adm). (b) bit 7 (cs) of the adm is set (to 1), and a/d conversion is started. (c) when conversion starts, the msb (bit 7) of the successive approximation register (sar) is set (to 1) automatically. (d) when bit 7 of the sar is set (to 1), the tap selector sets the series resistor string voltage tap to 225 512 av ref1 (= 1/2 av ref1 ). (e) the voltage difference between the series resistor string voltage tap and the analog input is determined by the voltage comparator. if the analog input is greater than (1/2) av ref1 , the msb of the sar remains set (to 1), and if it is less than (1/2) av ref1 , the msb is cleared (to 0). (f) next, bit 6 of the sar is set (to 1) automatically, and the next comparison is performed. here, the series resistor string voltage tap is selected according to the value of bit 7 for which the result has already been set, as shown below. ? bit 7 = 1 ........ 383 512 av ref1 = 3 4 av ref1 ? bit 7 = 0 ........ 127 512 av ref1 = 1 4 av ref1 this voltage tap is compared with the analog input voltage, and bit 6 of the sar is manipulated as follows according to the result: ? analog input voltage 3 voltage tap: bit 6 = 1 ? analog input voltage < voltage tap: bit 6 = 0 (g) the same kind of comparison is continued up to the lsb (bit 0) of the sar (binary search method). . . . . . . 412 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (h) when comparison of the 8 bits is completed, a valid digital result is left in the sar, and that value is transferred to the a/d conversion result register (adcr) and latched. an a/d conversion operation end interrupt request (intad) can be generated at the same time. figure 16-6. basic a/d converter operation 80h c0h or 40h conversion result conversion result undefined conversion time sampling time a/d converter operation sar adcr intad a/d conversion sampling a/d conversion operations are performed successively until the cs bit is cleared (to 0) by software. if a write operation is performed on the adm during an a/d conversion operation, the conversion operation is initialized, and if the cs bit is set (to 1), conversion will be started from the beginning. the contents of the adcr are undefined after reset input. 413 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (2) input voltage and conversion result the relationship between the analog input voltage input to an analog input pin (ani0 to ani7) and the a/d conversion result (value stored in adcr) is shown by the following expression: adcr = int( v av in ref1 256 + 0.5) or (adcr C 0.5) av ref1 256 v in < (adcr + 0.5) av ref1 256 remark int( ): function that returns the integer part of the value in ( ) v in : analog input voltage av ref1 :av ref1 pin voltage adcr: adcr value figure 16-7 shows the relationship between the analog input voltage and the a/d conversion result in graphic form. figure 16-7. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 input voltage/av ref1 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 a/d conversion result (adcr) 414 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (3) a/d conversion time the a/d conversion time is determined by the system clock frequency (f clk ) and the fr bit of the a/d converter mode register (adm). the a/d conversion time includes the entire time required for one a/d conversion operation, and the sampling time is also included in the a/d conversion time. these values are shown in table 16-1. table 16-1. a/d conversion time system clock (f clk ) range fr bit conversion time sampling time 2 mhz f clk 16 mhz 0 180/f clk 36/f clk (11.3 m s to 90 m s) (2.3 m s to 18 m s) 2 mhz f clk 16 mhz 1 120/f clk 24/f clk (7.5 m s to 60 m s) (1.5 m s to 12 m s) (4) a/d converter operation modes there are two a/d converter operation modes, scan mode and select mode. these modes are selected according to the setting of bit 0 (ms) of the a/d converter mode register (adm). in addition, scan mode 0 or 1 can be selected by bit 5 (scmd) of the adm. operation in either mode continues until the adm is rewritten. 415 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.4.2 select mode one analog input is specified by bits 1 to 3 (anis0 to anis2) of the a/d converter mode register (adm), and a/d conversion of the specified analog input pin is started. the conversion result is stored in the a/d conversion result register (adcr). an a/d conversion end interrupt request (intad) is generated at the end of each conversion operation. figure 16-8. select mode operation timing (a) trg bit ? 0 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 ani3 conversion start ( adcr a/d conversion intad ( cs ? 1 ms ? 1 anis2 to anis0 ? 011 (b) trg bit ? 1 conversion end conversion end conversion end conversion end conversion end ( ( ani0 a/d conversion ani0 ani0 initialization initialization initialization intp5 ani0 ani0 ani0 ani0 ani0 ani0 ani0 ani0 adcr intad conversion start cs ? 1 ms ? 1 anis2 to anis0 ? 000 416 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.4.3 scan mode two scan modes, 1 and 0, are available. in scan mode 0, delay control that takes delay in reading the a/d conversion result by the cpu into consideration can be performed. in scan mode 1, no delay control is performed but the a/d conversion interval is fixed. generally, use of scan mode 1 is recommended. (1) scan mode 0 (bit 5 (scmd) of a/d converter mode register (adm) = 0) input from the analog input pins specified by bits 1 to 3 (anis0 to anis2) of the adm is selected and converted in order. for example, if anis2 to anis0 of the adm = 001, ani0 and ani1 will be scanned repeatedly (ani0 ? ani1 ? ani0 ? ani1 ? ...). in the scan mode, at the end of the conversion operation for each input the conversion value is stored in the a/d conversion result register (adcr) and an a/d conversion end interrupt request (intad) is generated. figure 16-9. scan mode 0 operation timing (a) trg bit ? 0 ani0 ani0 ani1 ani0 ani1 ani0 ani1 conversion end conversion end conversion end conversion end conversion end conversion end ani1 ani0 ani1 ani0 conversion start ( adcr a/d conversion intad ( cs ? 1 ms ? 0 anis2 to anis0 ? 001 (b) trg bit ? 1 ani0 ani1 ani0 a/d conversion ani2 ani0 ani1 ani0 initialization initialization initialization initialization ani0 ani1 adcr ani0 conversion end conversion end conversion end conversion end conversion start ( ( intad intp5 cs ? 1 ms ? 1 anis2 to anis0 ? 010 417 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (2) scan mode 1 (bit 5 (scmd) of a/d converter mode register (adm) = 1) when bit 5 of the adm is set (to 1), the analog input pins specified by bits 1 to 3 (anis0 to anis2) are selected, and subjected to conversion, in order. if an a/d conversion result register (adcr) read is not performed by the cpu by the end of the next a/d conversion after a/d conversion end (intad) generation, conversion is restarted without performing intad generation, adcr updating or channel updating (see figure 16-10 ). if an adcr read is performed by the cpu before the end of the next a/d conversion, the same operation as in scan mode 0 is performed. figure 16-10. scan mode 1 operation timing ani1 a/d conversion ani2 ani2 ani3 ani0 ani0 ani0 adcr ani1 ani2 ani3 intad adcr read channel updating disabled adcr updating disabled interrupt generation disabled 418 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.4.4 a/d conversion operation start by software an a/d conversion operation start by software is performed by writing a value to the a/d converter mode register (adm) that sets the trg bit of the adm register to 0 and the cs bit to 1. if a value is written to the adm during an a/d conversion operation (cs bit = 1) such that the trg bit is set to 0 and the cs bit to 1 again, the a/d conversion operation being performed at that time is suspended, and a/d conversion is started immediately in accordance with the written value. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operation mode set by the adm, and conversion operations continue repeatedly until an instruction that writes to the adm is executed. when a/d conversion operation is started by software (trg bit = 0), intp5 pin (p26 pin) input does not affect the a/d conversion operation. (1) select mode a/d conversion operation an a/d conversion operation is started on the analog input pin set by the a/d converter mode register (adm). as soon as the a/d conversion operation ends, another a/d conversion operation is performed on the same analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. figure 16-11. software start select mode a/d conversion operation anin a/d conversion anin anim anim anim anin anin anin anim anim adm rewrite cs ? 1, trg ? 0 conversion start cs ? 1, trg ? 0 adcr intad remark n = 0, 1, , 7 m = 0, 1, , 7 419 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (2) scan mode a/d conversion operation when conversion operation is started, an a/d conversion operation is started on the ani0 pin input. when the a/d conversion operation ends, an a/d conversion operation is started on the next analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. figure 16-12. software start scan mode a/d conversion operation adm rewrite cs ? 1 trg ? 0 interrupt request acknowledgment ani0 ani1 ani2 ani0 ani1 ani2 ani0 ani1 ani0 ani0 ani1 ani2 ani0 ani1 ani2 ani0 conversion start cs ? 1 trg ? 0 a/d conversion (ani0 to ani2 scanned) adcr intad 420 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.4.5 a/d conversion operation start by hardware an a/d conversion operation start by hardware is made possible by setting both the trg bit and the cs bit of the a/d converter mode register (adm) to 1. when the trg bit and the cs bit of the adm are both set to 1, external signals are placed in the standby state, and an a/d conversion operation is started when a valid edge is input to the intp5 pin (p26 pin). if another valid edge is input to the intp5 pin after the a/d conversion operation has been started by a valid edge input to the intp5 pin, the a/d conversion operation being performed at that time is suspended, and a/d conversion is performed from the beginning in accordance with the contents set in the adm. if a value is written to the adm during an a/d conversion operation (cs bit = 1) such that the trg bit and cs bit are both set to 1 again, the a/d conversion operation being performed at that time is suspended (the standby state is also suspended), and a standby state is entered in which the a/d converter waits for input of a valid edge to the intp5 pin in the a/d conversion operation mode in accordance with the written value, and a conversion operation is started when a valid edge is input. use of this function allows a/d conversion operations to be synchronized with external signals. once a/d conversion operation is started, as soon as one a/d conversion operation ends the next a/d conversion operation is started in accordance with the operation mode set by the adm (the a/d converter does not wait for intp5 pin input), and conversion operations continue repeatedly until an instruction that writes to the adm is executed, or a valid edge is input to the intp5 pin. caution approximately 10 m s is required from the time a valid edge is input to the intp5 pin until the a/d conversion operation is actually started. this delay must be taken into account in the design stage. see chapter 22 edge detection function for details of the edge detection function. 421 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 (1) select mode a/d conversion operation an a/d conversion operation is started on the analog input pin set by the a/d converter mode register (adm). as soon as the a/d conversion operation ends, another a/d conversion operation is performed on the same analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. if a valid edge is input to the intp5 pin during an a/d conversion operation, the a/d conversion operation being performed at that time is suspended, and a new a/d conversion operation is started. figure 16-13. hardware start select mode a/d conversion operation standby state anin anin anin anin anin anim anim standby state anin anin anin anim adm rewrite cs ? 1, trg ? 1 adm rewrite cs ? 1, trg ? 1 intad acknowledgment adcr intad a/d conversion intp5 pin input (rising edge valid) remark n = 0, 1, , 7 m = 0, 1, , 7 (2) scan mode a/d conversion operation when conversion operation is started, an a/d conversion operation is started on the ani0 pin input. when the a/d conversion operation ends, an a/d conversion operation is started on the next analog input pin. an a/d conversion end interrupt request (intad) is generated at the end of each a/d conversion operation. if a valid edge is input to the intp5 pin during an a/d conversion operation, the a/d conversion operation being performed at that time is suspended, and a new a/d conversion operation is started on the ani0 pin input. 422 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 figure 16-14. hardware start scan mode a/d conversion operation standby state ani0 ani1 ani2 ani0 ani0 ani0 ani1 ani2 standby state ani0 ani1 ani2 ani0 ani1 ani0 ani1 ani2 ani0 ani0 ani1 ani0 ani1 ani2 adm rewrite cs ? 1, trg ? 1 adm rewrite cs ? 1, trg ? 1 a/d conversion (ani0 to anii2 scanned) adcr intad intp5 pin input (rising edge valid) intad aknowledgment 423 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 16.5 external circuit of a/d converter the a/d converter is provided with a sample & hold circuit to stabilize its conversion operation. this sample & hold circuit outputs sampling noise during sampling immediately after an a/d conversion channel has been changed. to absorb this sampling noise, an external capacitor must be connected. if the impedance of the signal source is high, an error may occur in the conversion result due to the sampling noise. especially when the scan mode is used, the impedance of the signal source must be kept low because the channel whose signal is to be converted changes one after another. one way to absorb the sampling noise is to increase the capacitance of the capacitor. however, if the capacitance is increased too much, the sampling noise is accumulated. therefore, the most effective way is to reduce the resistance component. 16.6 cautions (1) range of voltages applied to analog input pins the following must be noted concerning a/d converter analog input pins ani0 to ani7 (p70 to p77). ? a voltage outside the range av ss to av ref1 should not be applied to pins subject to a/d conversion during an a/d conversion operation. if this restriction is not observed, the m pd784938 may be damaged. (2) hardware start a/d conversion approximately 10 m s is required from the time a valid edge is input to the intp5 pin until the a/d conversion operation is actually started. this delay must be taken into account in the design stage. see chapter 22 edge detection function for details of the edge detection function. (3) connecting capacitor to analog input pins a capacitor should be connected between the analog input pins (ani0 to ani7) and av ss and between the reference voltage input pin (av ref1 ) and av ss to prevent misoperation due to noise. 424 chapter 16 a/d converter preliminary users manual u13987ej1v0um00 figure 16-15. example of capacitor connection on a/d converter pins analog input reference voltage input 100 to 500 pf ani0 to ani7 av ref1 av ss m pd784938 (4) when the stop mode or idle mode is used, the consumption current should be reduced by clearing (to 0) the cs bit before entering the stop or idle mode. if the cs bit remains set (to 1), the conversion operation will be stopped by entering the stop or idle mode, but the power supply to the voltage comparator will not be stopped, and therefore the a/d converter consumption current will not be reduced. (5) once the a/d converter starts operating, conversion operations are performed repeatedly until the cs bit of the a/d converter mode (adm) is cleared (to 0). therefore, a superfluous interrupt may be generated if adm setting is performed after interrupt-related registers, etc., are set when a/d converter mode conversion, etc., is performed. the result of this superfluous interrupt is that the conversion result storage address appears to have been shifted when the scan mode is used. also, when the select mode is used, the first conversion result appears to have been an abnormal value, such as the conversion result for the other channel. it is therefore recommended that a/d converter mode conversion be carried out using the following procedure. <1> write to the adm (cs bit must be set (to 1)) <2> interrupt request flag (adif) clearance (to 0) <3> interrupt mask flag or interrupt service mode flag setting operations <1> to <3> should not be divided by an interrupt or macro service. when scan mode 0 (no delay control) is used, in particular, you should ensure that the time between <1> and <2> is less than the time taken by one a/d conversion operation. alternatively, the following procedure is recommended. <1> stop the a/d conversion operation by clearing (to 0) the cs bit of the adm. <2> interrupt request flag (adif) clearance (to 0). <3> interrupt mask flag or interrupt service mode flag setting <4> write to the adm 425 preliminary users manual u13987ej1v0um00 chapter 17 outline of serial interface the m pd784938 subseries is provided with four independent serial interface channels. therefore, communication with an external system and local communication within the system can be simultaneously executed by using these four channels. ? asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 channels ? refer to chapter 18 . ? clocked serial interface (csi) 2 channels ? 3-wire serial i/o mode (msb/lsb first) ? refer to chapter 19 . figure 17-1 shows an example of the serial interface. figure 17-1. example of serial interface uart + 3-wire serial i/o + 2-wire serial i/o rs-232-c driver/ receiver pd4711a [uart] rxd txd port so1 si1 sck1 intpm port si0 so0 sck0 intpn pd784938 (master) note v dd v dd [2-wire serial i/o] si so sck port int sb0 port int sck0 slave slave [3-wire serial i/o] port note m m note handshake line 426 preliminary users manual u13987ej1v0um00 [memo] 427 preliminary users manual u13987ej1v0um00 chapter 18 asynchronous serial interface/3-wire serial i/o the m pd784938 incorporates two serial interface channels for which asynchronous serial interface (uart) mode or 3-wire serial i/o (ioe) mode can be selected. the two uart/ioe channels have completely identical functions. in this chapter, therefore, unless stated otherwise, uart/ioe1 will be described as representative of both uart/ioes. when used as uart2/ioe2, the uart/ioe1 register names, bit names and pin names should be read as their uart2/ioe2 equivalents as shown in table 18-1. table 18-1. differences between uart/ioe1 and uart2/ioe2 names item uart/ioe1 uart2/ioe2 pin names p25/asck/sck1, p30/rxd/si1, p12/asck2/sck2, p13/rxd2/si2, p31/txd/so2 p14/txd2/so2 asynchronous serial interface mode register asim asim2 asynchronous serial interface mode register bit names txe, rxe, ps1, ps0, cl, sl, txe2, rxe2, ps21, ps20, cl2, isrm, sck sl2, isrm2, sck2 asynchronous serial interface status register asis asis2 asynchronous serial interface status register bit names pe, fe, ove pe2, fe2, ove2 clocked serial interface mode register csim1 csim2 clocked serial interface mode register bit names ctxe1, crxe1, dir1, csck1 ctxe2, crxe2, dir2, csck2 baud rate generator control register brgc brgc2 baud rate generator control register bit names tps0 to tps3, mdl0 to mdl3 tps20 to tps23, mdl20 to mdl23 interrupt request names intsr/itcsi1, intser, intst intsr2/intcsi2, intser2, intst2 interrupt control registers and bit names used in this sric, csiic1, seric, stic, sric2, csiic2, seric2, stic2, chapter srif, csiif1, serif, stif srif2, sciif2, serif2, stif2 428 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.1 switching between asynchronous serial interface mode and 3-wire serial i/o mode the asynchronous serial interface mode and 3-wire serial i/o mode cannot be used simultaneously. switching between these modes is performed in accordance with the settings of the asynchronous serial interface mode register (asim/asim2) and the clocked serial interface mode register (csim1/csim2) as shown in figure 18-1. figure 18-1. switching between asynchronous serial interface mode and 3-wire serial i/o mode 7 txe asim 6 rxe 5 ps1 4 ps0 3 cl 2 sl 1 isrm 0 sck txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 asynchronous serial interface mode operation specification (see figure 18-3 ) after reset address address r/w r/w 00h 0ff88h asim2 r/w 00h 0ff89h txe txe2 rxe rxe2 ctxe1 ctxe2 crxe1 crxe2 operation mode setting prohibited other than the above operation-stopped mode 3-wire serial i/o mode asynchronous serial interface mode 0 0 0 0 00 00 0 0 1 1 1 0 0 1 01 10 11 0 0 0 0 0 0 7 ctxe1 csim1 6 crxe1 5 0 4 0 3 0 2 dir1 1 csck1 0 0 ctxe2 crxe2 0 0 0 dir2 csck2 0 after reset r/w r/w 00h 0ff84h csim2 r/w 00h 0ff85h 3-wire serial i/o mode operation specification (see figure 18-11 ) 429 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2 asynchronous serial interface mode a uart (universal asynchronous receiver transmitter) is incorporated as the asynchronous serial interface. with this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible. a baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates. also, the baud rate can be defined by scaling the clock input to the asck pin. 18.2.1 configuration in asynchronous serial interface mode the block diagram of the asynchronous serial interface is described in figure 18-2. see 18.4 baud rate generator for details of the baud rate generator. 430 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-2. asynchronous serial interface block diagram internal bus 1/8 1/8 serial receive buffer shift register reception control parity check fe fe2 pe pe2 ove ove2 reset asis, asis2 txe txe2 rxe rxe2 ps21 ps0 ps20 cl cl2 sl sl2 isrm isrm2 sck sck2 rxb, rxb2 p30/r x d, p13/r x d2 p31/t x d, p14/t x d2 serial transmit shift register transmission control parity addition intser, intser2 intst, txs, txs2 intst2 1 m intsr, intsr2 1 m 1 2 n selector p25/asck, p12/asck2 f xx baud rate generator reset asim, asim2 1/8 ps1 431 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 (1) serial receive buffer (rxb/rxb2) this is the register that holds the receive data. each time one byte of data is received, the receive data is transferred from the shift register. if a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of rxb/rxb2, and the msb of rxb/rxb2 is always 0. rxb/rxb2 can be read only by an 8-bit manipulation instruction. the contents of rxb/rxb2 are undefined after reset input. (2) serial transmit shift register (txs/txs2) this is the register in which the data to be transmitted is set. data written to the txs/txs2 is transmitted as serial data. if a 7-bit data length is specified, bits 0 to 6 of the data written in the txs/txs2 are treated as transmit data. a transmit operation starts when a write to the txs/txs2 is performed. the txs/txs2 cannot be written to during a transmit operation. txs/txs2 can be written to only with an 8-bit manipulation instruction. the contents of txs/txs2 are undefined after reset input. (3) shift register this is the shift register that converts the serial data input to the rxd pin to parallel data. when one byte of data is received, the receive data is transferred to the receive buffer. the shift register cannot be manipulated directly by the cpu. (4) reception control parity check receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode register (asim/asim2). in addition, parity error and other error checks are performed during receive operations, and if an error is detected, a value is set in the asynchronous serial interface status register (asis/asis2) according to the type of error. (5) transmission control parity addition transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the serial transmit shift registers (txs/txs2) in accordance with the contents set to the asynchronous serial interface mode registers (asim/asim2). (6) selector selects the baud rate clock source. 432 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.2 asynchronous serial interface control registers (1) asynchronous serial interface mode register (asim), asynchronous serial interface mode register 2 (asim2) asim and asim2 are 8-bit registers that specify the uart mode operation. these registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of asim and asim is shown in figure 18-3. reset input clears these registers to 00h. 433 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-3. format of asynchronous serial interface mode register (asim) and asynchronous serial interface mode register 2 (asim2) 7 txe asim 6 rxe 5 ps1 4 ps0 3 cl 2 sl 1 isrm 0 sck txe2 rxe2 ps21 ps20 cl2 sl2 isrm2 sck2 after reset address r/w r/w 00h 0ff88h asim2 r/w 00h 0ff89h sck sck2 specification of input clock to baud rate generator external clock input (asck, asck2) 0 internal clock (fxx) 1 cl cl2 data character length specification 7 bits 8 bits sl sl2 stop bit length specification (transmission only) 1 bit 0 2 bits 1 0 1 ps0 ps20 parity bit specification no parity transmission = 0 parity addition reception = parity error not generated odd parity 0 1 ps1 ps21 0 01 0 even parity 11 isrm isrm2 specification of enabling/disabling of reception completion interrupt generation in case of receive error enabled 0 disabled 1 txe txe2 transmit/receive operation transmission/reception disabled, or 3-wire serial i/o mode transmission enabled reception enabled 0 1 rxe rxe2 0 01 0 transmission/reception enabled 11 434 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 caution an asynchronous serial interface mode register (asim/asim2) rewrite should not be performed during a transmit operation. if an asim/asim2 register rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst/intst2) or the interrupt request flag (stif/stif2) set by intst/intst2. (2) asynchronous serial interface status register (asis), asynchronous serial interface status register 2 (asis2) asis and asis2 contain flags that indicate the error contents when a receive error occurs. flags are set (to 1) when a receive error occurs, and cleared (to 0) when data is read from the serial receive buffer (rxb/rxb2). if the next data is received before rxb/rxb2 is read, the overrun error flag (ove/ove2) is set (to 1), and the other error flags are cleared (to 0) (if there is an error in the next data, the corresponding error flag is set (to 1)). these registers can be read only with an 8-bit manipulation instruction or bit manipulation instruction. the format of asis and asis2 is shown in figure 18-4. reset input clears these registers to 00h. figure 18-4. format of asynchronous serial interface status register (asis) and asynchronous serial interface status register 2 (asis2) 7 0 asis 6 0 5 0 4 0 3 0 2 pe 1 fe 0 ove 0 0 0 0 0 pe2 fe2 ove2 after reset address r/w r 00h 0ff8ah asis2 r overrun error flag 00h 0ff8bh next receive completed before data is read from receive buffer 1 parity error flag transmit data parity specification and receive data parity do not match 1 framing error flag stop bit not detected 1 caution the serial receive buffer (rxb/rxb2) must be read even if there is a receive error. if rxb/rxb2 is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 435 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.3 data format serial data transmission/reception is performed in full-duplex asynchronous mode. the transmit/receive data format is shown in figure 18-5. one data frame is made up of a start bit, character bits, parity bit, and stop bit(s). character bit length specification, parity selection and stop bit length specification for one data frame are performed by means of the asynchronous serial interface mode register (asim). figure 18-5. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit(s) ? start bit 1 bit ? character bits 7 bits/8 bits ? parity bits even parity/odd parity/0 parity/no parity ? stop bits 1 bit/2 bits the serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate generator settings. if a serial data receive error occurs, the nature of the receive error can be determined by reading the asynchronous serial interface status register (asis) status. 436 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.4 parity types and operations the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmission side and the reception side. with even parity and odd parity, 1 bit (odd number) errors can be detected. with 0 parity and no parity, errors cannot be detected. ? even parity if the number of bits with a value of 1 in the transmit data is odd, the parity bit is set to 1, and if the number of 1 bits is even, the parity bit is set to 0. control is thus performed to make the number of 1 bits in the transmit data plus the parity bit an even number. in reception, the number of 1 bits in the receive data plus the parity bit is counted, and if this number is odd, a parity error is generated. ? odd parity conversely to the case of even parity, control is performed to make the number of 1 bits in the transmit data plus the parity bit an odd number. in reception, a parity error is generated if the number of 1 bits in the receive data plus the parity bit is even. ? 0 parity in transmission, the parity bit is set to 0 irrespective of the receive data. in reception, parity bit detection is not performed. therefore, no parity error is generated irrespective of whether the parity bit is 0 or 1. ? no parity in transmission, a parity bit is not added. in reception, reception is performed on the assumption that there is no parity bit. since there is no parity bit, no parity error is generated. 437 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.5 transmission the m pd784938s asynchronous serial interface is set to the transmission enabled state when the txe bit of the asynchronous serial interface mode register (asim) is set (to 1). a transmit operation is started by writing transmit data to the serial transmit shift register (txs) when transmission is enabled. the start bit, parity bit and stop bit(s) are added automatically. when a transmit operation is started, the data in the txs is shifted out, and a transmission completion interrupt (intst) is generated when the txs is empty. if no more data is written to the txs, the transmit operation is discontinued. if the txe bit is cleared (to 0) during a transmit operation, the transmit operation is discontinued immediately. figure 18-6. asynchronous serial interface transmission completion interrupt timing (a) stop bit length: 1 stop parity d0 start txd (output) intst d1 d2 d6 d7 (b) stop bit length: 2 parity d0 start txd (output) intst d1 d2 d6 d7 stop cautions 1. after reset input the serial transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. 2. an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. 438 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.6 reception when the rxe bit of the asynchronous serial interface mode register (asim) is set (to 1), receive operations are enabled and sampling of the rxd input pin is performed. rxd input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by asim and band rate generator control register (brgc). when the rxd pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal is output on the m'th count. if the rxd pin input is low when sampled again by this start timing signal, the input is recogniz ed as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. when the character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends. when reception of one data frame ends, the receive data in the shift register is transferred to the serial receive buffer, rxb, and a reception completion interrupt (intsr) is generated. if an error occurs, the receive data in which the error occurred is still transferred to rxb. if bit 1 (isrm) of the asim was cleared (to 0) when the error occurred, intsr is generated. if the isrm was set (to 1), intsr is not generated. if the rxe bit is cleared (to 0) during a receive operation, the receive operation is stopped immediately. in this case the contents of rxb and asis are not changed, and no intsr or intser interrupt is generated. figure 18-7. asynchronous serial interface reception completion interrupt timing stop parity d0 start rxd (input) intsr d1 d2 d6 d7 caution the serial receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 439 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.2.7 receive errors three kinds of errors can occur in a receive operation: parity errors, framing errors, and overrun errors. as the result of data reception, an error flag is raised in the asynchronous serial interface status register (asis) and a receive error interrupt (intser) is generated. receive error causes are shown in table 18-2. it is possible to detect the occurrence of any of the above errors during reception by reading the contents of the asis (see figures 18-4 and 18-8 ). the contents of the asis register are cleared (to 0) by reading the serial receive buffer (rxb) or by reception of the next data (if there is an error in the next data, the corresponding error flag is set). table 18-2. receive error causes receive error cause parity error transmit data parity specification and receive data parity do not match framing error stop bit not detected overrun error reception of next data completed before data is read from receive buffer figure 18-8. receive error timing stop parity d0 start rxd (input) intsr note d1 d2 d6 d7 intser note if a receive error occurs while the isrm bit is set (to 1), intsr is not generated. remark in the m pd784938, a break signal cannot be detected by hardware. as a break signal is a low-level signal of two characters or more, a break signal may be judged to have been input if software detects the occurrence of two consecutive framing errors in which the receive data was 00h. the chance occurrence of two consecutive framing errors can be distinguished from a break signal by having the rxd pin level read by software (confirmation is possible by setting 1 in bit 0 of the port 3 mode register (pm3) and reading port 3 (p3)) and confirming that it is 0. cautions 1. the contents of the asynchronous serial interface status register (asis) are cleared (to 0) by reading the serial receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. 2. the rxb must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. 440 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.3 3-wire serial i/o mode the 3-wire serial i/o mode is used to communicate with devices that incorporate a conventional clocked serial interface. basically, communication is performed using three lines: the serial clock (sck), serial data output (so), and serial data input (si). generally, a handshake line is necessary for checking the communication status. figure 18-9. example of 3-wire serial i/o system configuration 3-wire serial i/o ? 3-wire serial i/o sck so si port (interrupt) port sck si so port interrupt (port) master cpu note slave cpu note handshake lines 18.3.1 configuration in 3-wire serial i/o mode the block diagram in the 3-wire serial i/o mode is shown in figure 18-10. 441 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-10. 3-wire serial i/o mode block diagram internal bus reset 8 dq shift register direction control circuit 8 serial clock counter interrupt signal generator intcsi1, intcsi2 p27/sck1, p12/sck2 serial clock control circuit selector baud rate generator p30/si1, p13/si2 p31/so1, p14/so2 csck1, csck2 csck1, csck2 so latch 8 csck2 dir2 crxe2 ctxe2 csck1 dir1 crxe1 ctxe1 n-ch open-drain output enable 442 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 (1) serial shift register (sio1/sio2) sio1 and sio2 convert 8-bit serial data to 8-bit parallel data, and vice versa. sio1/sio2 is used for both transmission and reception. actual transmit/receive operations are controlled by writing to/reading from sio1/sio2. these registers can be read or written with an 8-bit manipulation instruction. the contents of sio1/sio2 are undefined after reset input. (2) so latch the so latch holds the so1/so2 pin output level. (3) serial clock selector (1/2n) generates and selects the serial clock to be used. (4) serial clock counter counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (5) interrupt signal generator generates an interrupt request when 8 serial clocks have been counted by the serial clock counter. (6) selector selects whether data is input to the serial shift registers 1 and 2 (sio1 and sio2) from the si1 and si2 pins or output latches. (7) direction control circuit switches between msb-first and lsb-first modes. 443 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.3.2 clocked serial interface mode registers (csim1, csim2) csim1 and csim2 are 8-bit registers that specify operations in the 3-wire serial i/o mode. these registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the csim1 and csim2 format is shown in figure 18-11. reset input clears these registers to 00h. figure 18-11. format of clocked serial interface mode register 1 (csim1) and clocked serial interface mode register 2 (csim2) 7 ctxe1 csim1 6 crxe1 5 0 4 0 3 0 2 dir1 1 csck1 0 0 ctxe2 crxe2 0 0 0 dir2 csck2 0 after reset address r/w r/w 00h 0ff84h csim2 r/w (n = 1, 2) 00h 0ff85h csckn serial clock selection bit source clock in case of sckn (ctxen, crxen = 1) external input clock to sckn pin input cmos output 0 baud rate generator output 1 dirn operation mode specification (transfer bit order) msb-first lsb-first 0 1 ctxen transmit/receive operation transmission/reception disabled, or asynchronous serial interface mode transmission enabled reception enabled 0 1 crxen 0 01 0 transmission/reception enabled 11 444 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.3.3 basic operation timing in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in msb-first or lsb-first order in synchronization with the serial clock. msb/lsb switching is specified by the dir1 bit of the clock serial interface mode register (csim1). transmit data is output in synchronization with the fall of sck1, and receive data is sampled on the rise of sck1. an interrupt request (intcsi1) is generated on the 8th rise of sck1. when the internal clock is used as sck1, sck1 output is stopped on the 8th rise of sck1 and sck1 remains high until the next data transmit or receive operation is started. 3-wire serial i/o mode timing is shown in figure 18-12. figure 18-12. 3-wire serial i/o mode timing (1/2) (a) msb-first intcsi1 di7 di6 di5 di4 di3 di2 di1 di0 sck1 note si1 (input) so1 (output) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 transfer end interrupt generation start of transfer synchronized with fall of sck1 note master cpu: slave cpu: execution of instruction that writes to sio1, etc. output input 445 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-12. 3-wire serial i/o mode timing (2/2) (b) lsb-first intcsi1 di0 di1 di2 di3 di4 di5 di6 di7 sck1 note si1 (input) so1 (output) 12345678 do0 do1 do2 do3 do4 do5 do6 do7 transfer end interrupt generation start of transfer synchronized with fall of sck1 note master cpu: slave cpu: execution of instruction that writes to sio1, etc. output input remark if the m pd784938 is connected to a 2-wire serial i/o device, a buffer should be connected to the so1 pin as shown in figure 18-13. in the example shown in figure 18-13, the output level is inverted by the buffer, and therefore the inverse of the data to be output should be written to sio1. in addition, non-connection of the on-chip pull-up resistor should be specified for the p31/so1 pin. figure 18-13. example of connection to 2-wire serial i/o m pd784938 sck1 si1 so1 2-wire serial i/o device sio sck (serial clock line) (serial data line) 446 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.3.4 operation when transmission only is enabled a transmit operation is performed when the ctxe1 bit of clocked serial interface mode register (csim1) is set (to 1). the transmit operation starts when a write to the serial shift register (sio1) is performed while the ctxe1 bit is set (to 1). when the ctxe1 bit is cleared (to 0), the so1 pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the sck1 pin and data is output in sequence from sio1 to the so1 pin in synchronization with the fall of the serial clock, and si1 pin signals are shifted into sio1 in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of transmission and the first fall of sck1. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe1 bit), sck1 clock output is stopped and the transmit operation is discontinued on the next rise of sck1. in this case an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sio1 to the so1 pin in synchronization with the fall of the serial clock input to the sck1 pin after the start of transmission, and si1 pin signals are shifted into sio1 in synchronization with the rise of the sck1 pin input. if transmission has not started, shift operations are not performed and the so1 pin output level does not change even if the serial clock is input to the sck1 pin. if transmission is disabled during the transmit operation (by clearing (to 0) the ctxe1 bit), the transmit operation is discontinued and subsequent sck1 input is ignored. in this case an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. 18.3.5 operation when reception only is enabled a receive operation is performed when the crxe1 bit of the clocked serial interface mode register (csim1) is set (to 1). the receive operation starts when the crxe1 changes from 0 to 1, or when a read from serial shift register (sio1) is performed. (1) when the internal clock is selected as the serial clock when reception starts, the serial clock is output from the sck1 pin and the si1 pin data is fetched in sequence into serial shift register (sio1) in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of reception and the first fall of sck1. if reception is disabled during the receive operation (by clearing (to 0) the crxe1 bit), sck1 clock output is stopped and the receive operation is discontinued on the next rise of sck1. in this case an interrupt request (intcsi1) is not generated, and the contents of the sio1 are undefined. (2) when an external clock is selected as the serial clock when reception starts, the si1 pin data is fetched into serial shift register (sio1) in synchronization with the rise of the serial clock input to the sck1 pin after the start of reception. if reception has not started, shift operations are not performed even if the serial clock is input to the sck1 pin. if reception is disabled during the receive operation (by clearing (to 0) the crxe1 bit), the receive operation is discontinued and subsequent sck1 input is ignored. in this case an interrupt request (intcsi1) is not generated. 447 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.3.6 operation when transmission/reception is enabled when the ctxe1 bit and crxe1 bit of the clocked serial interface mode register (csim1) register are both set (1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). the transmit/ receive operation is started when the crxe1 bit is changed from 0 to 1, or by performing a write to serial shift register (sio1). when a transmit/receive operation is started for the first time, the crxe1 bit always changes from 0 to 1, and there is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. the first transmit data should therefore be written to sio1 beforehand when both transmission and reception are disabled (when the ctxe1 bit and crxe1 bit are both cleared (to 0)), before enabling transmission/reception. however, specify whether data is transferred with msb or lsb first before writing the sio1. even if the specification is made after writing the sio1, the byte order of the data already stored in the sio1 cannot be changed. when transmission/reception is disabled (ctxe1 = crxe1 = 0), the so1 pin is in the output high level. (1) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the sck1 pin, data is output in sequence from serial shift register (sio1) to the (so1) pin in synchronization with the fall of the serial clock, and si1 pin data is shifted in order into sio1 in synchronization with the rise of the serial clock. there is a delay of up to one sck1 clock cycle between the start of transmission and the first fall of sck1. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so1 pin becomes output high level. if reception only is disabled, the contents of the sio1 will be undefined. if transmission and reception are disabled simultaneously, sck1 clock output is stopped and the transmit and receive operations are discontinued on the next rise of sck1. when transmission and reception are disabled simultaneously, the contents of sio1 are undefined, an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. (2) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from serial shift register (sio1) to the so1 pin in synchronization with the fall of the serial clock input to the sck1 pin after the start of transmission/reception, and si1 pin data is shifted in order into sio1 in synchronization with the rise of the serial clock. if transmission/reception has not started, the sio1 shift operations are not performed and the so1 pin output level does not change even if the serial clock is input to the sck1 pin. if either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is discontinued. if transmission only is disabled, the so1 pin becomes output high level. if reception only is disabled, the contents of the sio1 will be undefined. if transmission and reception are disabled simultaneously, the transmit and receive operations are discontinued and subsequent sck1 input is ignored. when transmission and reception are disabled simultaneously, the contents of sio1 are undefined, an interrupt request (intcsi1) is not generated, and the so1 pin becomes output high level. 18.3.7 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (to 0) the ctxe1 bit and crxe1 bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. 448 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.4 baud rate generator the baud rate generator is the circuit that generates the uart/ioe serial clock. two independent circuits are incorporated, one for each serial interface. 18.4.1 baud rate generator configuration the baud rate generator block diagram is shown in figure 18-14. 449 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-14. baud rate generator block diagram internal bus 8 baud rate generator control register brgc, brgc2 reset asynchronous serial interface mode registers 1 & 2 asim1, asim2 1/8 sck clocked serial interface mode registers 1 & 2 csim1, csim2 1/8 csck1 5-bit counter 5-bit counter reset start bit detection 1/2 uart reception shift clock clear match match 1/2 selector selector selector shift clock for uart transmission & ioe frequency divider selector f prs f xx p25/asck/sck1, p12/asck2/sck2 brgc write csck1 start bit detection sampling clock reset 450 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 (1) 5-bit counter counter that counts the clock (f prs ) by which the output from the frequency divider is selected. generates a signal with the frequency selected by the low-order 4 bits of the baud rate generator control registers (brgc/brgc2). (2) frequency divider scales the internal clock (f xx ) or, in asynchronous serial interface mode, a clock that is twice the external baud rate input (asck/asck2), and selects f prs with the next-stage selector. (3) both-edge detection circuit detects both edges of the asck/asck2 pin input signal and generates a signal with a frequency twice that of the asck/ asck2 input clock. 18.4.2 baud rate generator control register (brgc, brgc2) brgc and brgc2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift clock in 3-wire serial i/o mode. these registers can be written to only with an 8-bit manipulation instruction. the brgc and brgc2 format is shown in figure 18-15. reset input clears brgc to 00h. caution when a baud rate generator control register (brgc, brgc2) write instruction is executed, the 5-bit counter and 1/2 frequency divider operations are reset. consequently, if a write to the brgc and brgc2 is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc and brgc2 should therefore not be written to during communication. 451 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 figure 18-15. format of baud rate generator control register (brgc) and baud rate generator control register 2 (brgc2) 7 tps3 brgc 6 tps2 5 tps1 4 tps0 3 mdl3 2 mdl2 1 mdl1 0 mdl0 tps23 tps22 tps21 tps20 mdl23 mdl22 mdl21 mdl20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f prs /16 f prs /17 f prs /18 f prs /19 f prs /20 f prs /21 f prs /22 f prs /23 f prs /24 f prs /25 f prs /26 f prs /27 f prs /28 f prs /29 f prs /30 f prs note 2 after reset address r/w r/w 00h 0ff90h brgc2 r/w k baud rate generator input clock note 1 f prs : prescaler output selection clock 00h 0ff91h mdl3 mdl2 mdl1 mdl0 mdl23 mdl22 mdl21 mdl20 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 f xx /4,096 f asck /2 note f asck /4 f asck /8 f asck /16 f asck /32 f asck /64 f asck /128 f asck /256 f asck /512 f asck /1,024 f asck /2,048 f asck /4,096 n 12-bit prescaler tap selection (f prs ) other than the above setting prohibited f xx : oscillator frequency or external clock input tps3 tps2 tps1 tps0 tps23 tps22 tps21 tps20 notes 1. only f prs /16 can be selected when asck/asck2 input is used. 2. can only be used in 3-wire serial i/o mode. note can not be selected when the value set in bits mdl3 to mdl0, k = 15. 452 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.4.3 baud rate generator operation the baud rate generator only operates when uart/ioe transmit/receive operations are enabled. the generated baud rate clock is a signal scaled from the internal clock (f xx ) or a signal scaled from the clock input from the external baud rate input (asck) pin. caution if a write to the baud rate generator control register (brgc) is performed during communication, the generated baud rate clock may be disrupted, preventing normal communication from continuing. the brgc should therefore not be written to during communication. (1) baud rate clock generation in uart mode (a) using internal clock (f xx ) this function is selected by setting (to 1) bit 0 (sck) of the asynchronous serial interface mode register (asim). the internal clock (f xx ) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f xx (k + 16) ? 2 n+2 f xx : oscillator frequency or external clock input frequency k: value set in bits mdl3 to mdl0 of brgc (k = 0 to 14) n: value set in bits tps3 to tps0 of brgc (n = 0 to 11) (b) using external baud rate input this function is selected by clearing (to 0) bit 0 (sck) of the asynchronous serial interface mode register (asim). when this function is used, bits mdl3 to mdl0 of the baud rate generator control register (brgc) must all be cleared (to 0) (k = 0). when this function is used with uart2, it is necessary to set (to 1) bit 2 of the port 1 mode control register (pmc1) and set the p12 pin to control mode. the asck pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by 32 (f prs ) (division by 16 and division by 2) is used as the baud rate. the baud rate is given by the following expression: (baud rate) = f asck 2 n+6 f asck : asck pin input clock frequency n: value set in bits tps3 to tps0 of brgc (n = 0 to 11) when this function is used, a number of baud rates can be generated by one external input clock. 453 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 (2) serial clock generation in 3-wire serial i/o mode selected when the csck1 bit of the clocked serial interface mode register (csim1) is set (to 1) and sck1 is output. (a) normal mode the internal clock (f xx ) is scaled by the frequency divider, this signal (f prs ) is scaled by the 5-bit counter, and the signal further divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f xx (k + 16) ? 2 n+2 f xx : oscillator frequency or external clock input frequency k: value set in bits mdl3 to mdl0 of brgc (k = 0 to 14) n: value set in bits tps3 to tps0 of brgc (n = 0 to 11) (b) high-speed mode when this function is used, bits mdl3 to mdl0 of the baud rate generator control register (brgc) are all set (1) (k= 15). the internal clock (f xx ) is scaled by the frequency divider, and this signal (f prs ) divided by 2 is used as the serial clock. the serial clock is given by the following expression: (serial clock) = f xx 2 n+2 f xx : oscillator frequency or external clock input frequency n: value set in bits tps3 to tps0 of brgc (n = 1 to 11) 454 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.4.4 baud rate setting in asynchronous serial interface mode there are two methods of setting the baud rate, as shown in table 18-3. this table shows the range of baud rates that can be generated, the baud rate calculation expression and selection method for each case. table 18-3. baud rate setting methods baud rate clock source selection method baud rate calculation baud rate range expression baud rate generator internal system clock sck in asim = 1 f xx f xx to f xx (k + 16) ? 2 n+2 245,760 64 asck input sck in asim = 0 f asck f asck to f asck note 2 n+6 131,072 64 note including f asck input range: (0 to f xx /256) remarks f xx : oscillator frequency or external clock input frequency k: value set in bits mdl3 to mdl0 of brgc (k = 0 to 14; see figure 18-15) n: value set in bits tps3 to tps0 of brgc (n = 0 to 11; see figure 18-15) f asck : asck input clock frequency (0 to f xx /4) (1) examples of settings when baud rate generator is used examples of baud rate generator control register (brgc) settings when the baud rate generator is used are shown below. when the baud rate generator is used, the sck bit of the asynchronous serial interface mode register (asim) should be set (to 1). table 18-4. examples of brgc settings when baud rate generator is used oscillator frequency (f xx ) 12.0 mhz 11.0592 mhz or external clock (f x ) baud rate brgc value error brgc value error [bps] (%) (%) 75 a4h 2.34 a2h 0.00 110 9bh 1.36 99h 1.82 150 94h 2.34 92h 0.00 300 84h 2.34 82h 0.00 600 74h 2.34 72h 0.00 1,200 64h 2.34 62h 0.00 2,400 54h 2.34 52h 0.00 4,800 44h 2.34 42h 0.00 9,600 34h 2.34 32h 0.00 19,200 24h 2.34 22h 0.00 31,250 19h 0.00 16h 0.54 38,400 14h 2.34 12h 0.00 76,800 04h 2.34 02h 0.00 455 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 (2) examples of settings when external baud rate input (asck) is used table 18-5 shows an example of setting when external baud rate input (asck) is used. when using the asck input, clear the sck bit of the asynchronous serial interface mode register (asim) to 0, and set the corresponding pin in the control mode by using pmc3 or pmc1. table 18-5. examples of settings when external baud rate input (asck) is used f asck 153.6 khz 4.9152 mhz (asck input frequency) baud rate [bps] brgc value brgc value 75 50h a0h 150 40h 90h 300 30h 80h 600 20h 70h 1,200 10h 60h 2,400 00h 50h 4,800 40h 9,600 30h 19,200 20h 38,400 10h 76,800 00h 456 chapter 18 asynchronous serial interface/3-wire serial i/o preliminary users manual u13987ej1v0um00 18.5 cautions (1) an asynchronous serial interface mode register (asim) rewrite should not be performed during a transmit operation. if an asim rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by reset input). software can determine whether transmission is in progress by using a transmission completion interrupt (intst) or the interrupt request flag (stif) set by intst. (2) after reset input the serial transmit shift register (txs) is emptied but a transmission completion interrupt is not generated. a transmit operation can be started by writing transmit data to the txs. (3) the serial receive buffer (rxb) must be read even if there is a receive error. if rxb is not read, an overrun error will occur when the next data is received, and the receive error state will continue indefinitely. (4) the contents of the asynchronous serial interface status register (asis) are cleared (to 0) by reading the serial receive buffer (rxb) or by reception of the next data. if you want to find the details of an error, therefore, asis must be read before reading rxb. (5) the baud rate generator control register (brgc) should not be written to during communication. if a write instruction is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock may be disrupted, preventing normal communication from continuing. (6) to specify the transfer bit order with csim1 and csim2 (bit 2 manipulation), do not set the ctxe and crxe bits at the same time. if these bits are specified at the same time, the bit transfer order may not be as specified. 457 preliminary users manual u13987ej1v0um00 chapter 19 3-wire serial i/o mode the m pd784938 has two channels of serial interfaces in 3-wire serial i/o mode (ioe0/ioe3). the two channels of ioe have identical functions. unless otherwise specified, therefore, ioe0 is explained in this chapter. to use ioe3, refer to table 19-1 for the register name, bit name, and pin name of ioe3. table 19-1. differences in name between ioe0 and ioe3 item ioe0 ioe3 pin name p32/sck0 p105/sck3 p27/si0 p106/si3 p33/so0 p107/so3 clocked serial interface mode register csim csim3 clocked serial interface mode register bit names encsi, dir, crxe, mod, encsi3, dir3, crxe3, mod3, selcl2 to selcl0 selcl32 to selcl30 serial shift register sio sio3 interrupt request name intcsi intcsi3 19.1 function in the 3-wire serial i/o mode (msb/lsb first), basically, three lines are used for communication: serial clock (sck0), serial data output (so0), and serial data input (si0). generally, a handshake line is necessary for checking the communication status. 458 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.2 configuration figure 19-1 shows the block diagram of the clocked serial interface in the 3-wire serial i/o mode (note that the functions of both channels are identical). figure 19-1. clocked serial interface block diagram (1) serial shift register (sio) the sio converts 8-bit serial data to 8-bit parallel data, and vice versa. sio is used for both transmission and reception. data is received or transmitted starting from the msb (or lsb). actual transmit/receive operations are controlled by writing to/reading from sio. sio can be read or written to with an 8-bit manipulation instruction. the contents of sio are undefined after reset input. (2) serial clock counter counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/reception has been performed. (3) interrupt signal generator a interrupt request is generated when 8 serial clocks have been counted by the serial clock counter. p27/si0 to p33/so0 port block to p32/sck0 port block sio shift lsb/msb csim en csi crx e dir sel st mo d sel cl2 sel cl1 sel cl0 n-ch open-drain specification qs r write to sio read to sio intcsi interrupt signal generation circuit eighth clock serial clock counter selcl. 0 to 2 external clock selection f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector 0 1 459 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.3 control registers 19.3.1 clocked serial interface mode register (csim, csim3) csim and csim3 are 8-bit registers that specify the serial interface operation mode (enable/disable), serial clock, etc. these registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the csim and csim3 format is shown in figure 19-1. reset input clears these registers to 00h. figure 19-2. format of clocked serial interface mode register (csim) and clocked serial interface mode register 3 (csim3) encsi3 selst3 dir3 crxe3 mod3 selcl32 selcl31 selcl30 csim3 0ff80h 00h r/w serial clock specification external clock note 1 f xx /128 f xx /64 f xx /32 f xx /16 f xx /8 note 2 setting prohibited encsi selst dir crxe mod selcl2 selcl1 selcl0 7654 3210 csim 0ff82h address 00h after reset r/w r/w selcl n2 0 0 0 0 1 1 selcl n1 0 0 1 1 0 0 selcl n0 0 1 0 1 0 1 (n = 3 with csim3 only) other than the above n-ch open-drain specification (p32, p33, or p105, p107) not n-ch open drain n-ch open drain modn 0 1 enables/disables serial interface receive operation reception disabled reception enabled crxen 0 1 serial interface bit transfer order selection msb first lsb first dirn 0 1 transmit activation condition selection start with a write operation to sio (serial shift register) start with a read operation from sio selstn 0 1 enables/disables serial interface operation disabled enabled encsin 0 1 460 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 notes 1. when the external clock is selected, the usable serial clock is min f xx /8 in the case of f clk = f xx /1; otherwise, it is min f clk /4. 2. setting is prohibited when the system clock (f clk = f xx /8) is selected. caution when bit 3 is set, the p-ch of the output buffer is forcibly turned off. this channel is not affected by pm3 and pmc3, or pm10 and pmc10. therefore, if the input or output mode is changed by using the pm register with bit 3 set in the port mode, the content of the port latch can be output and the pin level can be read in the n-ch open-drain mode. 461 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.4 3-wire serial i/o mode the 3-wire serial i/o mode is used to communicate with devices that incorporate a conventional clocked serial interface. basically, communication is performed using three lines: the serial clock (sck0), serial data output (so0), and serial data input (si0). generally, a handshake line is necessary for checking the communication status. figure 19-3. example of 3-wire serial i/o system configuration sck0 so0 si0 port (interrupt) port sck si so port interrupt (port) master cpu note slave cpu pd784938 m note handshake lines 462 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.4.1 basic operation timing in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/received bit by bit in msb-first or lsb-first order in synchronization with the serial clock. msb first/lsb first switching is specified by the dir bit of the clocked serial interface mode register (csim). transmit data is output in synchronization with the fall of sck0, and receive data is sampled on the rise of sck0. an interrupt request (intcsi) is generated on the 8th rise of sck0. when the internal clock is used as sck0, sck0 output is stopped on the 8th rise of sck0 and sck0 remains high until the next data transmit or receive operation is started. 3-wire serial i/o mode timing is shown in figure 19-4. figure 19-4. 3-wire serial i/o mode timing (1/2) (a) msb-first intcsi di7 di6 di5 di4 di3 di2 di1 di0 sck0 note si0 (input) so0 (output) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 transfer end interrupt generation start of transfer synchronized with fall of sck0 note master cpu: slave cpu: execution of instruction that writes to sio, etc. output input cautions 1. if data is written to sio during transfer operation after the transfer was started by writing sio, malfunctioning may occur. therefore, do not rewrite sio during the transfer operation. 2. the operation is immediately stopped even during transfer operation if the encsi bit is cleared (to 0). 463 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 figure 19-4. 3-wire serial i/o mode timing (2/2) (b) lsb-first intcsi di0 di1 di2 di3 di4 di5 di6 di7 sck0 note si0 (input) so0 (output) 12345678 do0 do1 do2 do3 do4 do5 do6 do7 transfer end interrupt generation start of transfer synchronized with fall of sck0 note master cpu: slave cpu: execution of instruction that writes to sio, etc. output input in the 3-wire serial i/o mode, the so0 pin functions as a cmos push-pull output. 464 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.4.2 operation when transmission only is enabled when the crxe bit of the clocked serial interface mode register (csim) is cleared (to 0), data is only transmitted and reception is disabled. transmission is started when data is written to the serial shift register (sio) with the encsi bit set (to 1). transmit data is input to sio instead of the data received from the si0 pin. if reception is disabled, therefore, the transmit data can be saved without being lost. if an instruction that writes data to si0 is executed when encsi = 1 and crxe = 0, the data is transmitted in 1-bit units in synchronization with the serial clock. the data of the first bit is output from the so0 pin, and at the same time, input to the last bit of si0. when the transmission is completed by repeating this operation eight times, an interrupt request is generated. figure 19-5. operation when reception is disabled sio serial i/o shift register si0 pin (a) when the internal clock is selected as the serial clock when transmission starts, the serial clock is output from the sck0 pin and data is output in sequence from sio to the so0 pin in synchronization with the fall of the serial clock, and si0 pin signals are shifted into sio in synchronization with the rise of the serial clock. there is a delay of up to one sck0 clock cycle between the start of transmission and the first fall of sck0. (b) when an external clock is selected as the serial clock when transmission starts, data is output in sequence from sio to the so0 pin in synchronization with the fall of the serial clock input to the sck0 pin after the start of transmission, and si0 pin signals are shifted into sio in synchronization with the rise of the sck0 pin input. if transmission has not started, shift operations are not performed and the so0 pin output level does not change even if the serial clock is input to the sck0 pin. if transmission is disabled during the transmit operation (by clearing (to 0) the encsi), the transmit operation is discontinued and subsequent sck0 input is ignored. in this case an interrupt request (intcsi) is not generated. even if the serial clock is input to sck0 while the ctxe bit is cleared (to 0), shift operations are not performed and the so0 pin output level does not change. caution when the external clock is selected, do not input the serial clock to the sck0 pin before setting transmit data to sio after transmission has been started. otherwise, undefined data may be output. similarly, do not use the macro service when the external clock is selected. 465 chapter 19 3-wire serial i/o mode preliminary users manual u13987ej1v0um00 19.4.3 operation when reception only is enabled to enable only reception, set (to 1) the encsi and crxe bits of the clocked serial interface mode register (csim). also set the p33/so0 pin in the port mode by using the port 3 mode control register (pmc3) (if this pin is not set in the port mode, it outputs data). reception can be started by reading the serial shift register (sio). 19.4.4 operation when transmission/reception is enabled when the encsi bit and crxe bit of the clocked serial interface mode register (csim) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). both transmission and reception can be started by writing data to sio when both the encsi and crxe bits are set (to 1). (a) when the internal clock is selected as the serial clock when transmission/reception starts, the serial clock is output from the sck0 pin, data is output in sequence from serial shift register (sio) to the so0 pin in synchronization with the fall of the serial clock, and si0 pin data is shifted in order into sio in synchronization with the rise of the serial clock. there is a delay of up to one sck0 clock cycle between the start of transmission and the first fall of sck0. (b) when an external clock is selected as the serial clock when transmission/reception starts, data is output in sequence from serial shift register (sio) to the so0 pin in synchronization with the fall of the serial clock input to the sck0 pin after the start of transmission/reception, and si0 pin data is shifted in order into sio in synchronization with the rise of the serial clock. if transmission/reception has not started, shift operations are not performed and the so0 pin output level does not change even if the serial clock is input to the sck0 pin. caution when the external clock is selected, do not input the serial clock to the sck0 pin before setting transmit data to sio after transmission has been started. otherwise, undefined data may be output. similarly, do not use the macro service when the external clock is selected. 19.4.5 corrective action in case of slippage of serial clock and shift operations when an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc. in this case, since the serial clock counter is initialized by disabling both transmit ope rations and receive operations (by clearing (to 0) the encsi bit), synchronization of the shift operations and the serial clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock. 466 preliminary users manual u13987ej1v0um00 [memo] 467 preliminary users manual u13987ej1v0um00 chapter 20 iebus controller 20.1 iebus controller function iebus (inter equipment bus) is a small-scale digital data transmission system that transmits data between units. to implement iebus with the m pd784938 subseries, external iebus driver and receiver are necessary because they are not provided. the internal iebus controller of the m pd784938 subseries is of negative logic. 20.1.1 communication protocol of iebus the communication protocol of the iebus is as follows: (1) multi-master mode all the units connected to the iebus can transmit data to the other units. (2) broadcasting communication function communication between one unit and plural units can be performed as follows: ? group-unit broadcasting communication: broadcasting communication to group units ? all-unit broadcasting communication: broadcasting communication to all units. (3) effective transfer rate the effective transfer rate is in mode 1 (the m pd784938 does not support modes 0 and 2 of effective transfer rate). ? mode 1: approx. 17 kbps caution different modes must not be mixed on one iebus. (4) communication mode data transfer is executed in half-duplex asynchronous communication mode. (5) access control: csma/cd (carrier sense multiple access with collision detection) the priority of the iebus is as follows: <1> broadcasting communication takes precedence over individual communication (communication from one unit to another). <2> the lower master address takes precedence. (6) communication scale the communication scale of iebus is as follows: ? number of units: 50 max. ? cable length: 150 m max. (when twisted pair cable is used) caution the communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the iebus driver/receiver and iebus. 468 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.1.2 determination of bus mastership (arbitration) an operation to occupy the bus is performed when a unit connected to the iebus controls the other units. this operation is called arbitration. when two or more units simultaneously start transmission, arbitration is to grant one of the units the permission to occupy the bus. because only one unit is granted the bus mastership as a result of arbitration, the priority condition of the bus is predetermined as follows: caution the bus mastership is released if communication is aborted. (1) priority by communication type broadcasting communication (communication from one unit to plural units) takes precedence over normal communi- cation (communication from one unit to another). (2) priority by master address if the communication type is the same, communication with the lower master address takes precedence. a master address consists of 12 bits, with unit 000h having the highest priority and unit fffh having the lowest priority. 20.1.3 communication mode although the iebus has three communication modes each having a different transfer rate, the m pd784938 subseries supports only communication mode 1. the transfer rate and the maximum number of transmit bytes in one communication frame in communication mode 1 are as shown in table 20-1. table 20-1. transfer rate and maximum number of transmit bytes in communication mode 1 communication mode maximum number of transmit bytes (bytes/frame) effective transfer rate (kbps) note 1 32 approx. 17 note the effective transfer rate when the maximum number of transmit bytes is transmitted. select the communication mode (mode 1) for each unit connected to the iebus before starting communication. if the communication mode of the master unit and that of the mating unit (slave unit) are not the same, communication is not correctly executed. 20.1.4 communication address with the iebus, each unit is assigned a specific 12-bit address. this communication address consists of the following identification numbers: high-order 4 bits: group number (number to identify the group to which each unit belongs) low-order 8 bits: unit number (number to identify each unit in a group) 469 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.1.5 broadcasting communication normally, transmission or reception is performed between the master unit and its mating slave unit on a one-to-one basis. during broadcasting communication, however, two or more slave units exist and the master unit executes transmission to these slave units. because plural slave units exist, the slave units do not return an acknowledge signal during communication. whether broadcasting communication or normal communication is to be executed is selected by broadcasting bit (for this bit, refer to 20.1.6 (2) broadcasting request bit ). broadcasting communication can be classified into the following two types: (1) group-unit broadcasting communication broadcasting communication is performed to the units in a group identified by the group number indicated by the high- order 4 bits of the communication address. (2) all-unit broadcasting communication broadcasting communication is performed to all the units, regardless of the value of the group number. group-unit broadcasting and all-unit broadcasting are identified by the value of the slave address (for the slave address, refer to 20.1.6 (4) slave address field ). 20.1.6 transmission format of iebus figure 20-1 shows the transmission signal format of the iebus. figure 20-1. iebus transmission signal format header master address field slave address field control field telegraph length field data field start bit broad- casting bit master address bit p frame format slave address bit pa control bit pa tele- graph length bit pa data bit pa data bit pa remarks 1. p: parity bit, a: ack/nack bit 2. the master station ignores the acknowledge bit during broadcasting communication. (1) start bit the start bit is a signal that informs the other units of the start of data transmission. the unit that is to start data transmission outputs a high-level signal (start bit) from the tx pin for a specific time, and then starts outputting the broadcasting bit. if another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. when the output of the start bit by the other unit has completed, the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit. the units other than the one that has started communication detect this start bit, and enter the reception status. 470 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (2) broadcasting bit this bit indicates whether the master selects one slave (individual communication) or plural slaves (broadcasting communication) as the other party of communication. when the broadcasting request bit is 0, it indicates broadcasting communication; when it is 1, individual communication is indicated. broadcasting communication is classified into two types: group-unit communication and all-unit communication. these communication types are identified by the value of the slave address (for the slave address, refer to (4) slave address field) . because two or more slave units exist in the case of broadcasting communication, the acknowledge bit in each field subsequent to the master address field is not returned. if two or more units start transmitting a communication frame at the same time, broadcasting communication takes precedence over individual communication, and wins in arbitration. if one station occupies the bus as the master, the value set to the broadcasting request bit (allrq) of the bus control register (bcr) is output. (3) master address field the master address field is output by the master to inform a slave of the masters address. the configuration of the master address field is as shown in figure 20-2. if two or more units start transmitting the broadcasting bit at the same time, the master address field makes a judgment of arbitration. the master address field compares the data it outputs with the data on the bus each time it has output one bit. if the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. as a result, the master stops transmission and enters the reception status. because the iebus is configured of wired and, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. after a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. if one unit occupies the bus as the master, the address set by the unit address register (uar) is output. figure 20-2. master address field master address field master address (12 bits) msb lsb parity 471 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (4) slave address field the master outputs the address of the unit with which it is to communicate. figure 20-3 shows the configuration of the slave address field. a parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. next, the master unit detects an acknowledge signal from the slave unit to confirm that the slave unit exists on the bus. when the master has detected the acknowledge signal, it starts outputting the control field. during broadcasting communication, however, the master does not detect the acknowledge bit but starts outputting the control field. the slave unit outputs the acknowledge signal if its slave address coincides and if the slave detects that the parities of both the master address and slave address are even. the slave unit judges that the master address or slave address has not been correctly received and does not output the acknowledge signal if the parities are odd. at this time, the master unit is in the standby (monitor) status, and communication ends. during broadcasting communication, the slave address is used to identify group-unit broadcasting or all-unit broadcasting, as follows: if slave address is fffh: all-unit broadcasting communication if slave address is other than fffh: group-unit broadcasting communication remark the group no. during group-unit broadcasting communication is the value of the high-order 4 bits of the slave address. if one unit occupies the bus as the master, the address set by the slave address register (sar) is output. figure 20-3. slave address field slave address field unit no. msb lsb ack parity slave address (12 bits) group no. (5) control field the master outputs the operation it requires the slave to perform, by using this field. the configuration of the control field is as shown in figure 20-4. if the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an acknowledge signal and starts outputting the telegraph length field. if the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit does not output the acknowledge signal, and returns to the standby (monitor) status. the master unit starts outputting the telegraph field after confirming the acknowledge signal. if the master cannot confirm the acknowledge signal, the master unit enters the standby status, and communication ends. during broadcasting communication, however, the master unit does not confirm the acknowledge signal, and starts outputting the telegraph length field. table 20-2 shows the contents of the control bits. 472 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 table 20-2. contents of control bits bit 3 note 1 bit 2 bit 1 bit 0 function 0000 reads slave status 0001 undefined 0010 undefined 0011 reads data and locks note 2 0100 reads lock address (low-order 8 bits) note 3 0101 reads lock address (high-order 4 bits) note 3 0110 reads slave status and unlocks note 2 0111 reads data 1000 undefined 1001 undefined 1010 writes command and locks note 2 1011 writes data and locks note 2 1100 undefined 1101 undefined 1110 writes command 1111 writes data notes 1. the telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (msb). if bit 3 is 1: transfer from master unit to slave unit if bit 3 is 0: transfer from slave unit to master unit 2. this is a control bit that specifies locking or unlocking (refer to 20.1.7 (4) locking and unlocking ). 3. the lock address is transmitted in 1-byte (8-bit) units and is configured as follows: msb low-order 8 bits undefined high-order 4 bits control bit: 4h control bit: 5h lsb if the control bit received from the master unit is not as shown in table 20-3, the unit locked by the master unit rejects accepting the control bit, and does not output the acknowledge bit. 473 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 table 20-3. control field for locked slave unit bit 3 bit 2 bit 1 bit 0 function 0000 reads slave status 0100 reads lock address (low-order 8 bits) 0001 reads lock address (high-order 4 bits) if the unlocked unit receives the control data shown in table 20-4, the unit rejects accepting the control data and does not output the acknowledge bit. table 20-4. control field for unlocked slave unit bit 3 bit 2 bit 1 bit 0 function 0100 interrupts lock address (low-order 8 bits) 0101 interrupts lock address (high-order 4 bits) if one unit occupies the bus as the master, the value set to the control data register (cdr) is output. figure 20-4. control field msb lsb ack parity control bit (4 bits) control field (6) telegraph length field this field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. the configuration of the telegraph length field is as shown in figure 20-5. table 20-5 shows the relation between the telegraph length bit and the number of transmit data. figure 20-5. telegraph length field msb lsb telegraph length field telegraph length bit (8 bits) parity ack table 20-5. contents of telegraph length bit telegraph length bit (hex) number of transmit data bytes 01h 1 byte 02h 2 bytes || ffh 255 bytes 00h 256 bytes 474 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 the operation of the telegraph length field differs depending on whether the master transmits (when control bit 3 is 1) or receives (when control bit 3 is 0) data. <1> when master transmits data the telegraph length bit and parity bit are output by the master unit. when the slave unit detects that the parity is even, it outputs the acknowledge signal, and starts outputting the data field. during broadcasting communication, however, the slave unit does not output the acknowledge signal. if the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby (monitor) status. at this time, the master unit also returns to the standby status, and communication ends. <2> when master receives data the telegraph length bit and parity bit are output by the slave unit. if the master unit detects that the parity bit is even, it outputs the acknowledge signal. if the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, does not output the acknowledge signal, and returns to the standby status. at this time, the slave unit also returns to the standby status, and communication ends. (7) data field this is data output by the transmission side. the master unit transmits or receives data to or from a slave unit by using the data field. the configuration of the data field is as shown in figure 20-6. figure 20-6. data field data field (number specified by telegraph length field) msb lsb one data ack parity control bit (8 bits) ack parity following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. broadcasting communication is used only when the master unit transmits data. at this time, the acknowledge bit is ignored. 475 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 the operation differs as follows depending on whether the master transmits or receives data. <1> when master transmits data when the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. if the parity is even and receive data is not stored in the data register (dr) when the slave unit receives the data bit and parity bit, the slave unit outputs an acknowledge signal. if the parity is odd or if receive data is stored in the dr, the slave unit rejects receiving the data, and does not output the acknowledge signal. if the slave unit does not output the acknowledge signal, the master unit transmits the same data again. this operation continues until the master detects the acknowledge signal from the slave unit, or the data exceeds the maximum number of transmit bytes. if the data is continuous and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the acknowledge signal, the master unit transmits the next data. during broadcast communication, the slave unit does not output the acknowledge signal, and the master unit transfers 1 byte of data at a time. during broadcast communication, the slave unit receives the data and parity bits, and if the parity is odd or receive data is stored in the dr, reception is considered not to have been performed correctly and is stopped. <2> when master receives data when the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. the slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. the master unit reads the data and parity bits output by the slave unit, and checks the parity. if the parity is odd or the dr is receiving data, the master unit refuses to acknowledge this data and does not output the acknowledge signal. if the maximum number of transmit bytes is a value within the range that can be transmitted in one communication frame, the master unit repeats reading the same data. if the parity is even and the dr is not receiving data, the master unit accepts the data and returns the acknowledge signal. if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. (8) parity bit the parity bit is used to confirm that the transmit data has no error. the parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. the parity is an even parity. if the number of bits in the data that are 1 is odd, the parity bit is 1. if the number of bits in the data that are 1 is even, the parity bit is 0. (9) acknowledge bit during normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to confirm that the data has been correctly received. ? end of slave address field ? end of control field ? end of telegraph length field ? end of data field the definition of the acknowledge bit is as follows: ? 0: indicates that the transmit data is recognized (ack). ? 1: indicates that the transmit data is not recognized (nack). 476 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 during broadcast communication, however, the content of the acknowledge bit is ignored. <1> last acknowledge bit of slave address field the last acknowledge bit of the slave address field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the master address bit or slave address bit is incorrect ? if a timing error (error in bit format) occurs ? if a slave unit does not exist <2> last acknowledge bit of control field the last acknowledge bit of the control field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the control bit is incorrect ? when control bit 3 is 1 (write operation) when the slave receive enable flag (enslvrx) note is not set ? when control bits for which enslvrx note is not set are data read (3h, 7h) ? if control bits 3h, 6h, 7h, ah, bh, eh, or fh are requested from a unit other than one for which lock has been set ? if the control bit indicates reading of a lock address (4h or 5h) even when locking is not set ? if a timing error occurs ? if the control bit is undefined note bit 3 of the bus control register (bcr) cautions 1. when the slave status request control data is received even if the slave transmit enable flag (enslvtx) is not set, ack is always returned. 2. when data/command write control data is received even when the slave receive enable flag (enslvrx) is not set, the control field acknowledge bit returns nack. prohibiting receive operations (stopping communication) using enslvrx is limited to individual sommunication. in the case of broadcast communication, communication continues until a data request interrupt (intie1) or end interrupt (intie2) is generated. <3> last acknowledge bit of telegraph length field the last acknowledge bit of the telegraph length field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the telegraph length bit is incorrect ? if a timing error occurs <4> last acknowledge bit of data field the last acknowledge bit of the data field serves as nack in any of the following cases, and transmission is stopped. ? if the parity of the data bit is incorrect note ? if a timing error occurs after the preceding acknowledge bit has been transmitted ? when receive data is stored in the data register (dr), and no more data can be accepted note . note in this case, for the individual communication, if the maximum number of transmission bytes is a value within the range that can be transmitted in one frame, the transmission side performs transmission of that data field again. in the case of broadcast communication, the transmission side does not perform transmission of that data field again, and a transmission error occurs on the receiving side and reception is stopped. 477 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.1.7 transmit data (1) slave status the master unit can learn why the slave unit did not return the acknowledge bit (ack), by reading the slave status. the slave status is determined depending on the result of the last communication the slave unit has executed. all the slave units can supply information on the slave status. table 20-6 shows the meaning of the slave status. figure 20-7. bit configuration of slave status msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 20-6. meaning of slave status bit value meaning bit 0 note 1 0 transmit data is not written to data register (dr) 1 transmit data is written to dr bit 1 note 2 0 receive data is not saved to dr 1 receive data is saved to dr bit 2 0 unit is not locked 1 unit is locked bit 3 0 fixed to 0 bit 4 note 3 0 slave transmission is stopped 1 slave transmission is ready bit 5 0 fixed to 0 bit 7 00 mode 0 indicates highest mode supported by unit note 4 bit 6 01 mode 1 10 mode 2 11 not used notes 1. the value of this buffer of the m pd784938 subseries is initialized to 1 at reset. 2. the receive buffer of the m pd784938 subseries has a capacity of 1 byte. 3. when the m pd784938 subseries serves as a slave unit, this bit corresponds to the status indicated by bit 4 (enslvtx) of the bus control register (bcr). 4. when the m pd784938 subseries serves as a slave unit, bits 7 and 6 are fixed to 0 and 1 (mode 1), respectively. 478 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (2) lock address when the lock address is read (control bit: 4h or 5h), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. figure 20-8. configuration of lock address msb low-order 8 bits undefined high-order 4 bits control bit: 4h control bit: 5h lsb (3) data if the control bit indicates reading of data (3h or 7h), the data in the data buffer of the slave unit is read by the master unit. if the control bit indicates writing of data (bh or fh), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) locking and unlocking the lock function is used when a message is transferred in two or more communication frames. the unit that is locked does not receive data from units other than the one that has locked the unit. a unit is locked or unlocked as follows: <1> locking if the communication frame is completed without succeeding in transmission or reception of the data of the number of bytes specified by the telegraph length bit after the acknowledge bit 0 of the telegraph length field has been transmitted or received by the control bit that specifies locking (3h, ah, or bh), the slave unit is locked by the master unit. at this time, the bit (bit 2) in the byte indicating the slave status is set to 1. <2> unlocking after transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3h, ah, or bh), or the control bit that has specified unlocking (6h), the slave unit is unlocked by the master unit. at this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to 0. locking or unlocking is not performed during broadcasting communication. 479 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.1.8 bit format figure 20-9 shows the format of the bits constituting the communication frame of the iebus. figure 20-9. bit format of iebus logic ? logic ? preparation period synchronization period data period stop period preparation period: first low-level (logic 1) period synchronization period: next high-level (logic 0) period data period: period indicating value of bit stop period: last low-level (logic 1) period the synchronization period and data period are almost equal to each other in length. the iebus synchronizes each 1 bit. the specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. 480 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.2 simple iebus controller the m pd784938 has a newly developed iebus controller. the functions of this iebus controller are limited as compared with the iebus interface functions of the existing models (provided to the 78k/0 series). table 20-7 compares the iebus interface functions of the existing models with the simple iebus interface functions of the m pd784938 subseries. table 20-7. comparison between existing and simple iebus interface functions item existing function (iebus of 78k/0) simple iebus communication mode modes 0, 1, and 2 fixed to mode 1 internal system clock 6.0 (6.29) mhz internal buffer size transmit buffer: 33 bytes (fifo) transmit/receive data register receive buffer: 40 bytes (fifo) up to 4 frames can be received. cpu processing hardware processing communication start preprocessing (data setting) setting and management of each communication status 1-byte data write processing 1-byte data read processing management of transmission such as slave status management of plural frames, master request reprocessing bit processing (modulation/demodulation, error detection) field processing (generation/management) arbitration result detection parity processing (generation/error detection) automatic return of ack/nack automatic data transmission re-processing communication start preprocessing (data setting) setting and management of each communication status writing data to transmit buffer reading data from receive buffer bit processing (modulation/demodulation, error detection) field processing (generation/management) arbitration result detection parity processing (generation/error detection) automatic return of ack/nack automatic data re-processing automatic master re-processing note transmission processing such as automatic slave status transmission plural-frame reception processing note automatic master re-processing: after generating the master request, if the master request is cancelled by arbitration, etc., the bus is released and automatically re-issue the master request. 481 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.3 iebus controller configuration figure 20-10 shows the block diagram of the iebus controller. figure 20-10. iebus controller block diagram bcr (8 ) uar ( 12 ) sar ( 12 ) par ( 12 ) cdr ( 8) dlr ( 8) dr ( 8 ) usr (8 ) isr ( 8 ) ssr (8 ) scr (8 ) ccr (8 ) 81212 888 8 12 888 888 888 88 8 nf rx tx mpx mpx 12-bit latch comparator contention detection ack generation parity generation error detection tx/rx interrupt control circuit interrupt control block int request ? ? ? ? ? cpu interface block internal registers (vector, macro service) iebus interface block clk bit processing block field processing block internal bus r/w psr (8 bits) 8 5 8 12 12 12 internal bus 8 12 482 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 ? hardware configuration and function the iebus mainly consists of the following six internal blocks. ? cpu interface block ? interrupt control block ? internal registers ? bit processing block ? field processing block ? iebus interface block 483 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.4 internal registers of iebus controller the iebus controller consists of the following registers: 20.4.1 internal register list table 20-8 lists the internal registers of the iebus controller. table 20-8. internal registers of iebus controller address iebus register name symbol r/w bit units for manipulation initial value 1 bit 8 bits 16 bits 0ffb0h bus control register bcr r/w ?? 00h 0ffb2h unit address register uar ? 0000h 0ffb4h slave address register sar ? 0ffb6h partner address register par r ? 0ffb8h control data register cdr r/w ? 01h 0ffb9h telegraph length register dlr ? 0ffbah data register dr ? 00h 0ffbbh unit status register usr r ?? 0ffbch interrupt status register isr r/w ?? 0ffbdh slave status register ssr r ?? 41h 0ffbeh communication success counter scr ? 01h 0ffbfh transmit counter ccr ? 20h cautions 1. the above registers are mapped to the sfr space. 2. registers uar, sar, and par must be manipulated in word units. 3. instructions in read modify write mode (such as xch and rol4) cannot be used for dr, cdr, dlr, and isr. 484 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.4.2 description of internal registers each internal register of the iebus controller is explained below. (1) bus control register (bcr) figure 20-11. bus control register (bcr) format 7 eniebus 6 mstrq 5 allrq 4 enslvtx 3 enslvrx 2 0 1 0 0 0 address 0ffb0h after reset 00h r/w r/w enslvrx 0 1 slave reception enable flag slave reception disabled slave reception enabled enslvtx 0 slave transmission enable flag slave transmission disabled 1 slave transmission enabled allrq 0 broadcasting request flag requests individual communication 1 requests broadcasting communication mstrq 0 master request flag does not request iebus unit as master 1 requests iebus unit as master bcr eniebus 0 communication enable flag stops iebus unit 1 makes iebus unit active 485 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 ? communication enable flag (eniebus) ... bit 7 [set/reset condition] set: through software manipulation reset: through software manipulation caution before setting this flag, the following registers for communication must be set. during master transmission uar during master reception during slave transmission during slave reception ? master request flag (mstrq) ... bit 6 [set/reset condition] set: through software manipulation reset: through hardware at the end of the arbitration period caution make a remaster request through software processing in case the unit loses in contention. ? broadcasting request flag (allrq) ... bit 5 [set/reset condition] set: through software manipulation reset: through software manipulation caution be sure to set this flag to request broadcasting communication, and set bit 6. ? slave transmission enable flag (enslvtx) ... bit 4 [set/reset condition] set: through software manipulation reset: through software manipulation cautions 1. clear this flag before setting the master request flag during master request. if a slave transmission request is made by the master with this flag not set during slave, or if the disabled status is to be returned to the enabled status, the next new frame and those that follow become valid. 2. when enslvtx is not set, upon reception of data/command write control data 3h, 7h, the acknowledge bit of the control field returns nack. 3. even if enslvtx has been reset, when slave status request control data is returned, a status interrupt (intie2) is generated and communication is continued. ? slave reception enable flag (enslvrx) ... bit 3 [set/reset condition] set: through software manipulation reset: through software manipulation 486 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 caution when the cpu is busy with other processing, slave reception can be disabled by resetting this flag and returning nack with the acknowledge bit of the control field. therefore, when this flag is reset, individual communication can be disabled, but broadcasting communication cannot. furthermore, during individual communication, start interrupt (intie2) is generated. when cpu processing is prioritized (in case neither reception nor transmission are to be performed), reset eniebus (communication enable flag) and stop the iebus unit. also, when returning to the enabled status from the disabled status, the operation becomes effective from the next new frame. (2) unit address register (uar) this register sets the unit address of an iebus unit. this register must be always set before starting communication. figure 20-12. unit address register (uar) format 15 0 14 0 13 0 12 0 uar 11109876543210address 0ffb2h after reset 0000h r/w r/w sets unit address (12 bits) (3) slave address register (sar) during master request, the value of this register is reflected on the value of the transmit data in the slave address field. this register must be always set before starting communication. figure 20-13. slave address register (sar) format 15 0 14 0 13 0 12 0 sar 11 10 9 8 7 6 5 4 3 2 1 0 address 0ffb4h after reset 0000h r/w r/w sets slave address (12 bits) (4) partner address register (par) [during slave unit] the value of the receive data in the master address field (address of the master unit) is written to this register. if a request 4h to read the lock address (low-order 8 bits) is received from the master, the cpu must read the value of this register, and write the data of the low-order 8 bits to the data register (dr). if a request 5h to read the lock address (high-order 4 bits) is received from the master, the cpu must read the value of this register and write the data of the high-order 4 bits to dr. figure 20-14. partner address register (par) format 15 0 14 0 13 0 12 0 par 11 10 9 8 7 6 5 4 3 2 1 0 address 0ffb6h after reset 0000h r/w r sets partner address (12 bits) 487 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (5) control data register (cdr) [during master unit] the data of the low-order 4 bits is reflected on the data transmitted in the control field. during master request, this register must be set in advance before starting communication. [during slave unit] the data received in the control field is written to the low-order 4 bits. when the status transmission flag (status) is set, an interrupt (intie2) is issued, and each processing should be performed by software, according to the value of the low-order 4 bits of this register. figure 20-15. control data register (cdr) format 7 6 5 4 3 2 1 0 address after reset r/w selcl2 function 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 reads slave status undefined undefined reads data and locks reads lock address (low-order 8 bits) reads lock address (low-order 4 bits) reads slave status and unlocks reads data undefined undefined writes command and locks writes data and locks undefined undefined writes command writes data selcl1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 selcl0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 mod selcl2 selcl1 selcl0 0ffb8h 01h r/w cdr mod 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 cautions 1. because the slave unit must judge whether the received data is a ?ommand?or ?ata? it must read the value of this register after completing communication. 2. the read modify write instruction (such as xch and rol4) cannot be used for cdr. 3. if the master unit sets an undefined value, nack is returned from the slave unit, and communication is aborted. during broadcasting communication, however, the master unit continues communication without recognizing ack/nack; therefore, make sure not to set an undefined value to this register during broadcasting communication. 4. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, telegraph length register (dlr) is fixed to ?1h? therefore, in a re-request of the master follows, the appointed telegraph length must be set to dlr. 488 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 [slave status response operation] the ack response operation of the control field differs depending on the status of slave side when a slave status request (control data: 0h, 6h) and a lock address request 4h, 5h are received. <1> in unlocked status, when 0h, 6h control data is received ? return ack <2> in unlocked status, when 4h, 5h control data is received ? dont return ack <3> in locked status, when 0h, 4h, 5h, 6h control data is ? return ack received from the request unit <4> in locked status, when 0h, 4h, 5h control data is received from an address other than the request unit ? return ack <5> in locked status, when 6h control data is received from an address other than the request unit ? return ack in all cases from <1> to <5>, the status transmission flag (bit 4 of the interrupt status register (isr)) is set upon reception of the slave status and lock address request, and the status interrupt request (intie2) is generated. the generation timing is the end of the control field parity bit (start of the ack bit). however, if ack communication is not performed, an nack error occurs at the end of the ack bit and communication is stopped. figure 20-16. interrupt generation timing (in case of <1>, <3>, <4>) control bits (4 bits) 489 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 in the case of <4> and <5>, communication is performed from other than lock request in the locked status, so that even if the unit address is the target of the communication, no start interrupt or communication end interrupt (intie2) is generated. however, if a slave status, lock address request is received, the status transmission flag (bit 4 of interrupt status register (isr)) is set, and a status interrupt request (intie2) is generated. in this way, even if the same control data is received in the locked status, the intie2 generation timing differs depending on whether the master side is the lock request address (<3>) or it is a different address. figure 20-18. intie2 interrupt generation timing in locked status (in case of <4>, <5>) 490 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (6) telegraph length register (dlr) [during transmission unit] ... master transmission, slave transmission the data of this register is reflected on the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. this register must be set in advance before transmission. [during reception unit] ... master reception, slave reception the receive data in the telegraph length field transmitted from the transmission unit is written to this register. figure 20-20. telegraph length register (dlr) format 7 6 5 4 3 2 1 0 address after reset r/w remaining number of communication data bytes 1 byte 2 bytes 32 bytes 255 bytes 256 bytes 0 0 0 0 0 0 0 0 0ffb9h 01h r/w dlr 01h 02h 20h ffh 00h cautions 1. if the master issues a request ?h, 4h, 5h, or 6h?to transmit a slave status and lock address (high-order 4 bits, low-order 8 bits), the contents of this register are set to ?1h?by hardware; therefore, the cpu does not have to set this register. an instruction of read modify write mode (such as xch and rol4) cannot be used for dlr. 2. in the case of defeat in a bus conflict and a slave status request is received from the unit that won, dlr is fixed to ?1h? therefore, if a re-request of the master follows, the appointed telegraph length must be set to dlr. 491 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (7) data register (dr) [during transmission unit] the data (1 byte) written to the data register (dr) is stored to the internal shift register of the iebus. it is then output from the most significant bit, and an interrupt (intie1) is issued to the cpu each time 1 byte has been transmitted. intie is generated at the timing of the data register (dr) value stored in the internal shift register of the iebus. however, intie1 is not generated when the last byte and the 32nd byte (last byte of one communication frame) is delivered to the internal register. [during reception unit] one byte of the data received by the internal shift register of the iebus is stored to this register. each time 1 byte has been correctly received, an interrupt (intie1) is issued. figure 20-21. data register (dr) format 7 6 5 4 3 2 1 0 address after reset r/w 0ffbah 00h r/w dr sets communication data (8 bits) caution if the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt (intie2) occurs. an instruction of read modify write mode (such as xch and rol4) cannot be used for dr. 492 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (8) unit status register (usr) figure 20-22. unit status register (usr) format 0 slvrq arbit alltrns ack lock 0 0 76543210 usr 0ffbbh address 00h after reset r r/w lock 0 1 lock status flag non-lock status lock status ack 0 1 ack transmission flag transmits nack transmits ack alltrns 0 1 broadcasting communication flag individual communication status broadcasting communication status arbit 0 1 contention flag wins in contention loses in contention slvrq 0 1 slave request flag no slave request slave request 493 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 ? slave request flag (slvrq) ... bit 6 this flag indicates whether the master has issued a slave request. ? contention flag (arbit) ... bit 5 this flag indicates the result of contention. [set/reset condition] set: set if the data output by a unit does not coincide with the data on the bus line during the arbitration period after the master request has been made. reset: cleared at start bit timing ? broadcasting communication flag (alltrans)... bit 4 this flag indicates if the unit is performing broadcasting communication. the contents of the flag are initialized upon detection of the start bit of each frame, and updated to the broadcasting field. the set/bit conditions change depending on the broadcasting field bit reception data at all times except initialization (reset) through system reset. [set/reset condition] set: upon reception of broadcasting in broadcasting field reset: upon reception of individual in broadcasting field, or upon input of system reset. caution update of the broadcasting communication flag is performed regardless of whether or not the communication target is the unit address. figure 20-23. broadcasting communication flag operation example broad- casting iebus sequence no reset with start bit intie2 set reset m10 m11 m10 m11 broad- casting start start ack transmission flag (ack) ... bit 3 this flag indicates whether ack is transmitted during the ack period of each field while the unit serves as a reception unit. the content of the flag is updated during the ack period of each frame. if the internal circuit is initialized due to the occurrence of a parity error, the content of the flag cannot be updated during the ack period of the field. ? lock status flag (lock) ... bit 2 this flag indicates whether the unit is locked. [set/reset condition] set: set if lock specifications 3h, 6h, ah, and bh are received in the control field, and if the communication end flag is l and frame end flag is h. reset: if the communication enable flag is cleared. if unlocking commands 3h, 6h, ah, and bh are received by the control field and the communication end flag is set. caution locking or unlocking is not performed during broadcasting communication. 494 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (9) interrupt status register (isr) this status register indicates the status when an interrupt of the iebus is issued. user must read this register and perform the subsequent processing each time an interrupt has been generated. clear the contents of the following communication error flag (ieerr), start interrupt flag (start), and status transmission flag (status) through software manipulation in vector interrupt processing. also be sure to check and clear the contents of the communication end flag (endtrans) and frame end flag (endfram) through software manipulation. figure 20-24. interrupt status register (isr) format 0 ieerr start status endtrns endfram 00 76543210 isr 0ffbch address 00h after reset r/w r/w endfram 0 1 frame end flag frame does not end frame ends endtrns 0 1 communication end flag communication does not end communication ends status 0 1 status transmission flag no status transmission request status transmission request start 0 1 start interrupt flag interrupt after ack period of slave address field interrupt during ack period of slave address field ieerr 0 1 communication error flag no communication error communication error occurs remark reset of ieer, startf, and statusf flags is performed by writing a byte in to the interrupt status register (isr). 495 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 ? communication error flag (ieerr) ... bit 6 this flag detects an error during communication. [set/reset condition] set: set if a timing error, parity error (except the data field), nack reception (except the data field), or underrun occurs reset: through software manipulation ? start interrupt flag (start) ... bit 5 this flag indicates the interrupt during the ack period of the slave address field. [set/reset condition] set: set in the slave address field during the master request. set if there was a slave request from the master. (in the case of lock status, only if there was a slave request from the lock request unit.) reset: through software manipulation ? status transmission flag (status) ... bit 4 this flag indicates that the master transmits a slave status or lock address (high-order 4 bits, low-order 8 bits) while the unit serves as a slave. [set/reset condition] set: set when 0h, 4h, 5h, or 6h is received from the master in the control field while the unit serves as a slave. reset: through software manipulation ? communication end flag (endtrns) ... bit 3 this flag indicates whether communication has been completed by the number of transmit bytes set by the telegraph length field. [set/reset condition] set: when the count value of the scr counter has reached 0. reset: when any of the master request flag, slave transmission enable flag, or slave reception enable flag is set. ? frame end flag (endfram) ... bit 2 this flag indicates whether communication of the maximum number of transmit bytes (32 bytes) specified by each communication mode is completed. [set/reset condition] set: when the count value of the ccr has reached 0. reset: when any of the master request fag, slave transmission enable flag, or slave reception enable flag is set 496 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 [description of communication error source] 497 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 [supplementary explanation of overrun error] (1) if overrun occurs during individual communication reception, resulting in frame end if dr read is not performed following the overrun status and data retransmission reaches the maximum number of data transfer bytes (32 bytes), a frame end interrupt (intie2) occurs. the overrun status is maintained until dr read is performed even after frame end. (2) if the next reception starts in the case of (1) above, or if the next transmission starts without dr read being performed, following reception of the last data, regardless of whether it is broadcasting or individual communication even if communication is started to ones own address in the overrun status, an overrun caused nack return does not occur during the ack period in each of the slave address, control, and telegraph length fields. however, when dr read is not performed until data reception completion in the data field, no acknowledge is returned and reception is not performed (dr update is not performed). if the next communication is not directed to ones own address, dr is not updated until dr read is performed. since the communication is not directed at ones own address, data interrupt (intie1) or communication error interrupt (intie2) is not generated. 498 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (10) slave status register (ssr) this register indicates the communication status of the slave unit. after receiving a slave status transmission request from the master, the cpu reads this register, and writes a slave status to the data register (dr) to transmit the slave status. at this time, the telegraph length is automatically set to 01h that setting of telegraph length register (dlr) is not required (because it is preset by hardware). figure 20-25. slave status register (ssr) format 010 statslv 0 statlock statrx stattx 76543210 ssr 0ffbdh address 41h after reset r r/w stattx 0 1 dr transmit status transmission data not stored in dr transmission data stored in dr statrx 0 1 dr receive status receiving data not stored in dr receiving data stored in dr statlock 0 1 lock status flag unlock status lock status statslv 0 1 slave transmission enable flag slave transmission stops slave transmission enabled slave transmission status flag (statslv) ... bit 4 reflects the content of the slave transmission enable flag. ? lock status flag (statlock) ... bit 2 reflects the content of the lock status flag. ? dr receive status (statrx) ... bit 1 the flag that indicates the receive status of the dr. ? dr transmit status (stattx) ... bit 0 the flag that indicates the transmit status of the dr. bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to 01h (mode 1). 499 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (11) success count register (scr) this register reads the count value of the counter that decrements the value set by the telegraph length register by ack in the data field. when the count value has reached 00h, the communication end flag (endtrns) is set. figure 20-26. success count register (scr) format 76543210 scr 0ffbeh address 01h after reset r r/w remaining number of communication data bytes 01h 02h 20h ffh 00h 1 byte 2 bytes 32 bytes 255 bytes 0 byte (end of communication) or 256 bytes note note the bit length of the actual hard counter consists of 9 bits. when 00h is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. therefore, either the communication end flag is used, or if 00h is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. (12) communication count register (ccr) this register reads the count value of the counter that is preset to the maximum number of transmitted bytes (32 bytes) per frame specified in mode 1 and is decremented during the ack period of the data field regardless of ack/nack. when the count value has reached 00h, the frame end flag (endfram) is set. figure 20-27. communication count register (ccr) format 7 6 5 4 3 2 1 0 address after reset r/w 0ffbfh 20h r ccr number of transmitted bytes preset value in mode 1 and maximum number of transmitted bytes per frame ... 20h (32 bytes) 500 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.5 interrupt operations of iebus controller 20.5.1 interrupt control block 501 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.5.2 interrupt source list the interrupt request signals of the internal iebus controller in the 78k/iv series can be classified into vector interrupts and macro service interrupts. these interrupt processing can be specified through software manipulation. the interrupt sources are listed below. table 20-9. interrupt source list interrupt source condition of generation cpu processing after remark unit field generation of interrupt communication error undo communication processing communication error is or output (timing error) master/slave all fields of timing error, parity error, nack (parity error) reception other than data reception, underrun error, and (individual) overrun error. all fields (broadcasting) (nack reception) transmission other than data (individual) (underrun error) transmission data (overrun error) reception data (broadcasting) start interrupt master slave/address slave request judgment interrupt always occurs if loses in contention judgment contention during master request. (if loses, remaster processing) communication preparation processing slave slave/address slave request judgment generated only during slave communication preparation request processing status transmission slave control refer to transmission processing generated regardless of the example such as slave status. slave transmission enable flag. invalid if flag is disabled. end of communication transmission data macro service end processing set if scr is cleared to 0 reception data macro service end processing set if ccr is cleared to 0 receive data processing end of frame transmission data retransmission preparation set if ccr is cleared to 0 processing reception data re-reception preparation set if ccr is cleared to 0 processing transmit data write transmission data none (processed by macro set after transfering of transmit service) data to internal shift register receive data read reception data none (processed by macro set after normal data reception service) 502 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.6 interrupt generation timing and main cpu processing 20.6.1 master transmission start broad- casting m address p s address p a control p a telegraph length p a data 1 pa data 1 data 2 p a data n? p a data n p a <1> i <2> h i i i approx. 624 s (mode 1) approx. 390 s (mode 1) n = final number of data bytes m m caution indicates that an interrupt (intie1) does not occur. initial preparation processing sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. communication start processing sets the bus control register (enables communication, master request, and slave reception). <1> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of slave request ? slave reception processing note 1 judgment of contention result ? remaster request processing interrupt (intie1) occurrence note 2 the transmit data of the second byte and those that follow are written to the data register (dr) by macro service. at this time, the data transfer direction is ram (memory) ? sfr (peripheral) <2> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of end of communication ? end of communication processing judgment of end of frame ? re-communication processing note 3 503 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 notes 1. if a slave reception request is confirmed during vector interrupt processing, the data transfer direction of macro service must change from ram (memory) ? sfr (peripheral) to sfr (peripheral) ? ram (memory) until the first data is received. the maximum pending period of this data transfer direction changing processing is about 1,040 m s in communication mode 1. 2. if nack is received from the slave in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted by hardware. if the transmit data is not written during the period while the next data is being written, a communication error interrupt occurs due to the occurrence of an underrun, and communication is ended midway through. 3. the vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted. 504 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.6.2 master reception if master reception is performed, it is necessary to give prior notice of slave transmission to the unit set as slave. therefore, master reception requires at least two communication frames. the slave unit prepares the transmission data, sets enslvtx (slave request transmission flag (bit 4 of the bus control register (bcr)), and then waits. approx. 1,014 s (mode 1) m start broad- casting m address p s address p a control a p telegraph length a p data 1 approx. 390 s (mode 1) m data 1 p a data 2 p a data n? p a data n p a < 2 > n = final number of data bytes < 1 > initial preparation processing sets a unit address, slave address, and control data. communication start processing sets the bus control register (enables communication and master request). <1> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of slave request ? slave processing judgment of collision result ? remaster request processing interrupt (intie1) occurrence note 1 the receive data stored to the data register (dr) is read by macro service. at this time, the data transfer direction is sfr (peripheral) ? ram (memory). <2> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of end of communication ? end of communication processing judgment of end of frame ? re-communication processing note 2 notes 1. if nack is transmitted (hardware processing) in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted from the slave. if the receive data is not read in time until the next data is received, the hardware automatically transmits nack. 2. the vector interrupt processing in <2> judges whether the data has been correctly received within one frame. if the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame. 505 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.6.3 slave transmission start m address p s address p a control p a data 1 pa data 1 data 2 p a data n? p a data n p a <1> i <2> h i i i n = final number of data bytes pa approx. 390 s (mode 1) approx. 624 s (mode 1) m m broad- casting telegraph length caution indicates that an interrupt (intie1) does not occur. initial preparation processing sets a unit address, telegraph length, and the first byte of the transmit data. communication start processing sets the bus control register (enables communication, slave transmission, and slave reception). <1> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of slave request interrupt (intie2) occurrence an interrupt occurs only when 0h, 4h, 5h, or 6h is received in the control field in the slave status. interrupt (intie1) occurrence note 1 the transmit data of the second byte and those that follow are written to the data register (dr) by macro service. at this time, the data transfer direction is ram (memory) ? sfr (peripheral). <2> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of end of communication ? end of communication processing judgment of end of frame ? re-communication processing note 2 notes 1. if nack is received from the master in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt occurs due to occurrence of underrun, and communication is abnormally ended. 2. the vector interrupt processing in <2> judges whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the continuation of the data must be transmitted. 506 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.6.4 slave reception start m address p s address p a control p a data 1 pa data 1 data 2 p a data n? p a data n p a <1> i i i n = final number of data bytes pa i <2> approx. 390 s (mode 1) approx. 1,014 s (mode 1) m m broad- casting telegraph length initial preparation processing sets a unit address. communication start processing sets the bus control register (enables communication, disables slave transmission, and enables slave reception). <1> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of slave request ? slave processing note 1 interrupt (intie1) occurrence note 1 the receive data stored to the data register (dr) is read by macro service. at this time, the data transfer direction is sfr (peripheral) ? ram (memory). <2> interrupt (intie2) occurrence judgment of occurrence of error ? error processing judgment of end of communication ? end of communication processing judgment of end of frame ? end of frame processing note 2 notes 1. if nack is transmitted in the data field, an interrupt (intie1) is not issued to the cpu, but the same data is retransmitted from the master. if the receive data is not read in time until the next data is received, nack is automatically transmitted. 2. the vector interrupt processing in <2> judges whether the data has been correctly received within one frame. 507 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.6.5 interval of occurrence of interrupt for iebus control each control interrupt must occur at each point of communication and perform the necessary processing until the next interrupt occurs. therefore, the cpu must control the iebus control block, taking the shortest time of this interrupt into consideration. the locations at which the following interrupts may occur are indicated by - in the field where it may occur. - does not mean that the interrupt occurs at each of the points indicated by - . if an error interrupt (timing error, parity error, or ack error) occurs, the iebus internal circuit is initialized. as a result, the following interrupt does not occur in that communic ation frame. (1) master transmission start bit t t1 t broad- casting master address t t2 p slave address t pa at t3 control p a a t4 p tat telegraph lengh p a data p a communication starts communication starts pa data data a p data tt t4 end of communication end of frame u u t5 remarks 1. t: timing error, p: parity error, a: ack error, u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: @ 6-mhz operation) item symbol min. unit communication starts C timing error t1 approx. 97 m s communication starts C communication start interrupt t2 approx. 1,380 m s communication start interrupt C ack error t3 approx. 16 m s communication start interrupt C end of communication t4 approx. 1,014 m s data transmission C underrun error t5 approx. 390 m s 508 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 (2) master reception start bit t t1 t broad- casting master address t t2 p slave address t pa at t3 control p a a t4 p tat telegraph lengh p a data p a communication starts communication starts pa data data a p data tt t4 end of communication end of frame p t5 remarks 1. t: timing error, p: parity error, a: ack error, : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: @ 6-mhz operation) item symbol min. unit communication starts C timing error t1 approx. 97 m s communication starts C communication start interrupt t2 approx. 1,380 m s communication start interrupt C ack error t3 approx. 16 m s communication start interrupt C end of communication t4 approx. 1,014 m s receive data read interval t5 approx. 390 m s (3) slave transmission start bit t t1 t broad- casting master address t t2 p slave address t pa t control p a a t4 tat telegraph lengh p a data p a communication starts communication starts pa data data a p data tt t4 end of communication end of frame u t5 u p p p t5 t3 status request 509 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 remarks 1. t: timing error, p: parity error, a: ack error, u: underrun error, : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: @ 6-mhz operation) item symbol min. unit communication starts C timing error t1 approx. 97 m s communication starts C communication start interrupt t2 approx. 1,380 m s communication start interrupt C status request t3 approx. 234 m s communication start interrupt C end of communication t4 approx. 1,014 m s status request C end of communication t5 approx. 780 m s (4) slave reception start bit t t1 t broad- casting master address t t2 p p slave address t pa at t3 control p a pa t4 p tpt telegraph lengh p a data p a communication starts communication starts pa data data a p data tt t4 t5 end of communication end of frame remarks 1. t: timing error, p: parity error, a: ack error, : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. (iebus: @ 6-mhz operation) item symbol min. unit communication starts - timing error t1 approx. 97 m s communication starts - communication start interrupt t2 approx. 1,380 m s communication start interrupt - ack error t3 approx. 16 m s communication start interrupt - end of communication t4 approx. 1,014 m s receive data read interval t5 approx. 390 m s 510 chapter 20 iebus controller preliminary users manual u13987ej1v0um00 20.7 cautions when using iebus controller (1) receiving slave status request the m pd784938 subseries operates differently from the m pd784908 subseries when receiving the slave status request. the differences are as follows. table 20-10 shows the operation (slave status request) of iebus controller of the m pd784938 subseries. table 20-10. iebus controller operation (slave status request) of m pd784938 subseries state of m pd784938 slave status received control operation during reception subseries request data unlocked state all units 0h, 4h, 5h, 6h ? ack return at ack period of the control field. locked state units that have ? sets status transmission flag and generates intie2. lock requested except units that have lock requested (2) data register (dr) read operation when receiving a unit, after the reception of each byte is completed, a macro-service activated signal (intie1) is generated, and the cpu needs to perform data register (dr) read processing. when this dr read processing is delayed and the next data reception is completed, dr will be updated. therefore, dr read processing should be completed in the period between intie1 generation and the next data reception. the maximum holding time from intie1 generation to dr read is approximately 390 m s. the m pd784908 subseries has 40 bytes of reception buffer. when receiving data when there is no space in the reception buffer, nack is returned and a request for data to be retransmitted to the transmission unit is automatically generated. because, in the case of the m pd784938 subseries (simple iebus controller), intie1 is generated for every 1 byte reception, that dr needs to be read by interrupt processing (macro service recommendation). 511 preliminary users manual u13987ej1v0um00 chapter 21 clock output function the m pd784938 has a clock function that outputs a signal scaled from the system clock. the clock output function can output the system clock directly, or a 1/2, 1/4, 1/8, or 1/16 system clock signal. in addition, it can be used as a 1-bit output port. the output pin has a alternate function as the astb pin. caution this function cannot be used when the external memory expansion mode is used. 21.1 configuration the clock output function configuration is shown in figure 21-1. figure 21-1. clock output function configuration f clk f clk /2 f clk /4 f clk /8 f clk /16 selector 2 output control selector 1 address latch signal reset astb/clockout clock output mode register (clom) lv 0 0 cle 0 fs2 fs1 fs0 512 chapter 21 clock output function preliminary users manual u13987ej1v0um00 (1) clock output mode register (clom) register that controls the operation of the clock output function. (2) selector 1 selector that selects the frequency of the clock to be output. (3) output control controls the output signal in accordance with the contents of the clock output mode register (clom). (4) selector 2 selects either the astb signal or the clockout signal as the signal to be output to the astb/clockout pin. (5) astb/clockout pin pin that outputs the signal selected by selector 2. while the reset input is low, the astb/clockout pin is in the hi-z state, and when the reset input becomes high, it outputs a low-level signal, and then outputs a signal according to the set function. 513 chapter 21 clock output function preliminary users manual u13987ej1v0um00 21.2 clock output mode register (clom) the clom controls the clock output function. clom can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the clom format is shown in figure 21-2. reset input clears clom to 00h. figure 21-2. clock output mode register (clom) format 7 lv clom 6 0 5 0 4 cle 3 0 2 fs2 1 fs1 0 fs0 frequency selection f clk note f clk /2 f clk /4 f clk /8 f clk /16 fs2 0 0 fs1 0 0 fs0 1 0 010 011 100 outputs lv bit contents outputs clock selected by bits fs2 to fs0 clock output control cle 1 0 outputs low level outputs high level output level control lv 1 0 address after reset r/w r/w 00h 0ffc6h note outputs the system clock duty 50 % cautions 1. when the external memory expansion mode is used, the clock output mode register (clom) should be set to 00h (value after reset release). 2. the other bits (fs0 to fs2 and lv) must not be changed while the cle bit is set (to 1). 3. the other bits (fs0 to fs2 and lv) must not be changed at the same time when the cle bit is changed. 514 chapter 21 clock output function preliminary users manual u13987ej1v0um00 21.3 operation 21.3.1 clock output a signal with the clock output frequency selected by bits fs0 to fs2 is selected by selector 1 and output. the output signal has the same level as the lv bit when the cle bit is cleared (to 0), and is output from the clock signal immediately after the cle bit is set (to 1). when the cle bit is cleared (to 0), the contents of the lv bit are output in synchronization with the clock signal, and further output operations are stopped. figure 21-3. clock output operation timing (a) lv = 0 f clk /n (n = 1, 2, 4, 8, 16) clockout cle (b) lv = 1 f clk /n (n = 1, 2, 4, 8, 16) cle clockout setting of bits fs0 to fs2 and the lv bit should only be performed when cle = 0 (bits fs0 to fs2 and the lv bit should not be changed within the same instruction that changes the cle bit contents). 515 chapter 21 clock output function preliminary users manual u13987ej1v0um00 21.3.2 1-bit output port when the cle bit is cleared (to 0), the contents of the lv bit are output from the clockout pin. the clockout pin changes as soon as the contents of the lv bit change. figure 21-4. 1-bit output port operation clockout set1 lv instruction executed clr1 lv instruction executed lv 21.3.3 operation in standby mode (1) halt mode the state prior to setting of the halt mode is maintained. that is, if, during clock output, clock output has been performed continuously, and clock output has been disabled, the lv bit contents set before the halt mode setting are output unchanged. (2) stop mode and idle mode clock output must be disabled before setting the stop mode or idle mode (this must be done by software). the clockout pin level output is the level before the stop mode or idle mode was set (the contents of the lv bit). 21.4 cautions (1) this function cannot be used when the external memory expansion mode is used. (2) when the external memory expansion mode is used, the clock output mode register (clom) should be set to 00h (value after reset release). (3) the other bits (fs0 to fs2 and lv) must not be changed while the cle bit is set (to 1). (4) the other bits (fs0 to fs2 and lv) must not be changed at the same time when the cle bit is changed. 516 preliminary users manual u13987ej1v0um00 [memo] 517 preliminary users manual u13987ej1v0um00 chapter 22 edge detection function p20 to p26 have an edge detection function that allows a rising edge/falling edge to be set programmable, and the detected edge is sent to internal hardware. the relation between pins p20 to p26 and the use of the detected edge is shown in table 22-1. table 22-1. pins p20 to p26 and use of detected edge pin use detected edge specification register p20 nmi, standby circuit control intm0 p21 intp0, timer/event counter 1 capture signal timer/event counter 1 count clock signal real-time output port trigger signal p22 intp1, timer/event counter 2 cr22 capture signal p23 intp2, ci (timer/event counter 2 count clock signal), timer/event counter 2 cr21 capture signal p24 intp3, timer/event counter 0 capture signal intm1 timer/event counter 0 count clock signal p25 intp4, standby circuit control p26 intp5, a/d converter conversion start signal, standby circuit control the edge detection function operates at all times except in stop mode and idle mode (although the edge detection function for pins p20, p25, and p26 also operates in stop mode and idle mode). for the p21/intp0 pin, the noise elimination time when edge detection is performed can be selected by software. 22.1 edge detection function control registers 22.1.1 external interrupt mode registers (intm0, intm1) the intmn (n = 0, 1) specify the valid edge to be detected on pins p20 to p26. the intm0 specifies the valid edge for pins p20 to p23, and the intm1 specifies the valid edge for pins p24 to p26. the intmn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the format of intm0 and intm1 are shown in figures 22-1 and 22-2 respectively. reset input clears these registers to 00h. 518 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 figure 22-1. external interrupt mode register 0 (intm0) format 7 es21 intm0 6 es20 5 es11 4 es10 3 es01 2 es00 1 0 0 esnm1 falling edge rising edge p20 (nmi) pin input detected edge specification esnm1 1 0 falling edge rising edge p21 (intp0, cr11/cr11w capture trigger, tm1/tm1w count clock, real-time output port output trigger) pin input detected edge specification es01 0 0 setting prohibited 1 both falling & rising edges 1 es00 1 0 0 1 falling edge rising edge p22 (intp1, cr22/cr22w capture trigger) pin input detected edge specification es11 0 0 setting prohibited 1 both falling & rising edges 1 es10 1 0 0 1 falling edge rising edge p23 (intp2, cr21/cr21w capture trigger, ci) pin input detected edge specification es21 0 0 setting prohibited 1 both falling & rising edges 1 es20 1 0 0 1 address after reset r/w r/w 00h 0ffa0h 519 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 figure 22-2. external interrupt mode register 1 (intm1) format 7 0 intm1 6 0 5 es51 4 es50 3 es41 2 es40 1 es31 0 es30 falling edge rising edge p24 (intp3, cr02 capture trigger, tm0 count clock) pin input detected edge specification es31 0 0 setting prohibited 1 both falling & rising edges 1 es30 1 0 0 1 falling edge rising edge p25 (intp4) pin input detected edge specification es41 0 0 setting prohibited 1 both falling & rising edges 1 es40 1 0 0 1 falling edge rising edge p26 (intp5, a/d conversion start signal) pin input detected edge specification es51 0 0 setting prohibited 1 both falling & rising edges 1 es50 1 0 0 1 address after reset r/w r/w 00h 0ffa1h caution valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (intmn: n = 0, 1). also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. 520 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 22.1.2 sampling clock selection register (scs0) scs0 specifies the sampling clock (f smp ) for digital noise elimination performed on pin p21. scs0 can be read or written to with an 8-bit manipulation instruction. the format of scs0 is shown in figure 22-3. reset input clears scs0 to 00h. figure 22-3. sampling clock selection register (scs0) format 000000 scs01 scs00 76543210 scs0 0ffa4h address 00h after reset r/w r/w scs01 sampling clock (f smp ) f clk f xx /32 f xx /64 f xx /128 scs00 0 0 1 1 0 1 0 1 pulse width eliminated as noise minimum pulse width recognized as signal 3/f clk (239 ns) 96/f xx (7.7 s) 192/f xx (15.3 s) 384/f xx (30.5 s) 2/f clk (159 ns) 64/f xx (5.1 s) 128/f xx (10.2 s) 256/f xx (20.3 s) f xx = 12.58 mhz f clk = 12.58 mhz ? ? ? ? m m m m m m 521 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 22.2 edge detection for pins p20, p25, and p26 on pins p20, p25, and p26, noise elimination is performed by means of analog delay before edge detection. therefore, an edge cannot be detected unless the pulse width is a given time (10 m s) or longer. figure 22-4. edge detection for pins p20, p25, and p26 p20/p25/p26 input p20/p25/p26 input signal after noise elimination falling edge rising edge eliminated as noise since pulse is short falling edge detected since pulse is sufficiently wide eliminated as noise since pulse is short rising edge detected since pulse is suficiently wide 10 s (min.) m 10 s (max.) m 10 s (max.) m caution since analog delay noise elimination is performed on pins p20, p25, and p26, an edge is detected up to 10 m s after it is actually input. also, unlike pins p21 to p24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. 522 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 22.3 p21 pin edge detection in p21 edge detection, digital noise elimination is performed using the clock (f smp ) specified by the sampling clock selection register (scs0). in digital noise elimination, input is sampled using the f smp clock, and if the input level is not the same at least three times in succession (if it is the same only two or fewer times in succession), it is eliminated as nois e. therefore, the level must be maintained for at least 3 f smp clock cycles in order to be recognized as a valid edge. remark when the pulse width of a signal with a comparatively long pulse width and a lot of noise, such as a reception signal infrared remote controller, is measured, or when a signal is input in which oscillation occurs when an edge occurs, as with switch input chattering, for instance, it is better to set the sampling clock to low speed with the sampling clock selection register (scs0). if the sampling clock is high-speed, there will be a reaction to the short-pulse noise components as well, and the program will frequently have to judge whether the input is noise or a signal. however, by slowing down the sampling clock, reaction to short pulse width noise is eliminated and thus the program does not have to make judgments so frequently, and can thus be simplified. figure 22-5. p21 pin edge detection p21 input f smp p21 input signal after noise elimination rising edge falling edge digital noise elimination by f smp clock cautions 1. since digital noise elimination is performed with the f smp clock, there is a delay of 2 to 3 f smp clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. if the input pulse width is 2 to 3 f smp clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 3 clocks. 3. if noise input to the pin is synchronized with the f smp clock in the m pd784938, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pin. 523 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 22.4 pin edge detection for pins p22 to p24 edge detection for pins p22 to p24 is performed after digital noise elimination by means of clock sampling. unlike the p21 pin, f clk is used as the sampling clock. in digital noise elimination, input is sampled using the f clk clock, and if the input level is not the same at least three times in succession (if it is the same only two or fewer times in succession), it is eliminated as noise. therefore, the level must be maintained for at least 3 f clk clock cycles (0.24 m s: f clk = 12.58 mhz) in order to be recognized as a valid edge. figure 22-6. edge detection for pins p22 to p24 p22 to p24 input f clk p22 to p24 input signal after noise elimination rising edge falling edge digital noise elimination with f clk clock cautions 1. since digital noise elimination is performed with the f clk clock, there is a delay of 2 to 3 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. 2. if the input pulse width is 2 to 3 f clk clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 3 clocks. 3. if noise input to a pin is synchronized with the f clk clock in the m pd784938, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. 524 chapter 22 edge detection function preliminary users manual u13987ej1v0um00 22.5 cautions (1) valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (intmn: n = 0, 1). also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge. (2) since analog delay noise elimination is performed on pins p20, p25, and p26, an edge is detected up to 10 m s after it is actually input. also, unlike pins p21 to p24, the delay before an edge is detected is not a specific value, because of differences in the characteristics of various devices. (3) since digital noise elimination is performed on the p21 pin with the f smp clock, there is a delay of 2 to 3 f smp clocks between input of an edge to the pin and the point at which the edge is actually detected. (4) if the input pulse width on the p21 pin is 2 to 3 f smp clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 3 clocks. (5) if noise input of the p21 pin is synchronized with the f smp clock in the m pd784938, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. (6) since digital noise elimination is performed on pins p22 to p24 with the f clk clock, there is a delay of 2 to 3 f clk clocks between input of an edge to the pin and the point at which the edge is actually detected. (7) if the input pulse width on pins p22 to p24 is 2 to 3 f clk clocks, it is uncertain whether a valid edge will be detected. therefore, to ensure reliable operation, the level should be held for at least 3 clocks. (8) if noise input to pins p22 to p24 is synchronized with the f clk clock in the m pd784938, it may not be recognized as noise. if there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input pins. 525 preliminary users manual u13987ej1v0um00 chapter 23 interrupt functions the m pd784938 is provided with three interrupt request service modes (see table 23-1 ). these three service modes can be set as required in the program. however interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in table 23-2. context switching cannot be selected for non-maskable interrupts or operand error interrupts. multiple-interrupt control using 4 priority levels can easily be performed for maskable vectored interrupts. table 23-1. interrupt request service modes interrupt request servicing performed pc & psw contents service service mode vectored interrupts software saving to & restoration executed by branching to service program at from stack address note specified by vector table context switching saving to & restoration executed by automatic switching to register from fixed area in bank specified by vector table and branching register bank to service program at address note specified by fixed area in register bank macro service hardware retained execution of pre-set service such as data (firmware) transfers between memory and i/o note the start addresses of all interrupt service programs must be in the base area. if the body of a service program cannot be located in the base area, a branch instruction to the service program should be written in the base area. 526 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.1 interrupt request sources the m pd784938 has the 29 interrupt request sources shown in table 23-2, with a vector table allocated to each. table 23-2. interrupt request sources (1/2) type of default interrupt request generating interrupt context macro macro vector interrupt priority generating source unit control switching service service table request register control address name word address software none brk instruction execution not not 3eh possible possible brkcs instruction execution possible not operand none invalid operand in mov stbc, not not 3ch error #byte instruction or mov wdm, possible possible #byte instruction, and location instruction non- none nmi (pin input edge detection) edge not not 2h maskable detection possible possible intwdt (watchdog timer watchdog not not 4h overflow) timer possible possible 527 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 table 23-2. interrupt request sources (2/2) type of default interrupt request generating interrupt context macro macro vector interrupt priority generating source unit control switching service service table request register control address name word address maskable 0 intp0 (pin input edge detection) edge pic0 possible possible 0fe06h 6h 1 intp1 (pin input edge detection) detection pic1 0fe08h 8h 2 intp2 (pin input edge detection) pic2 0fe0ah 0ah 3 intp3 (pin input edge detection) pic3 0fe0ch 0ch 4 intc00 (tm0-cr00 match signal timer/event cic00 0fe0eh 0eh generation) counter 0 5 intc01 (tm0-cr01 match signal cic01 0fe10h 10h generation) 6 intc10 (tm1-cr10 or tm1w- timer/event cic10 0fe12h 12h cr10w match signal generation) counter 1 7 intc11 (tm1-cr11 or tm1w- cic11 0fe14h 14h cr11w match signal generation) 8 intc20 (tm2-cr20 or tm2w- timer/event cic20 0fe16h 16h cr20w match signal generation) counter 2 9 intc21 (tm2-cr21 or tm2w- cic21 0fe18h 18h cr21w match signal generation) 10 intc30 (tm3-cr30 or tm3w- timer 3 cic30 0fe1ah 1ah cr30w match signal generation) 11 intp4 (pin input edge detection) edge pic4 0fe1ch 1ch 12 intp5 (pin input edge detection) detection pic5 0fe1eh 1eh 13 intad (a/d conversion end) a/d adic 0fe20h 20h converter 14 intser (asynchronous serial asynchro- seric not 0fe22h 22h interface receive error) nous possible 15 intsr (asynchronous serial serial sric possible 0fe24h 24h interface reception end) interface/ intcsi1 (clocked serial interface clocked csiic1 transfer end) serial 16 intst (asynchronous serial interface 1 stic 0fe26h 26h interface transmission end) 17 intcsi (clocked serial interface clocked csiic 0fe28h 28h transfer end) serial interface 18 intser2 (asynchronous serial asynchro- seric2 not 0fe2ah 2ah interface 2 receive error) nous possible 19 intsr2 (asynchronous serial serial sric2 possible 0fe2ch 2ch interface 2 reception end) interface 2/ intcsi2 (clocked serial interface 2 clocked csiic2 transfer end) serial 20 intst2 (asynchronous serial interface 2 stic2 0fe2eh 2eh interface 2 transmission end) 21 intie1 (iebus data access request) i ebus ieic1 0fe32h 32h 22 intie2 (iebus communication controller ieic2 0fe34h 34h error and communication end) 23 intw (watch timer output) watch wic 0fe36h 36h timer 24 intcsi3 (clocked serial interface 3 clocked csiic3 0fe38h 38h transfer end) serial interface 3 528 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 remarks 1. the default priority is a fixed number. this indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. 23.1.1 software interrupts interrupts by software consist of the brk instruction which generates a vectored interrupt and the brkcs instruction which performs context switching. software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.2 operand error interrupts these interrupts are generated if there is an illegal operand in an mov stbc, #byte instruction or mov wdmc, #byte instruction, and location instruction. operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control. 23.1.3 non-maskable interrupts a non-maskable interrupt is generated by nmi pin input or the watchdog timer. non-maskable interrupts are acknowledged unconditionally note , even in the interrupt disabled state. they are not subject to interrupt priority control, and are of higher priority that any other interrupt. note except during execution of the service program for the same non-maskable interrupt, and during execution of the service program for a higher-priority non-maskable interrupt 23.1.4 maskable interrupts a maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. in addition, acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the ie flag in the program status word (psw). in addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro service (though some interrupts cannot use macro service: see table 23-2 ). the priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority) as shown in table 23-2. also, multiprocessing control can be performed with interrupt priorities divided into 4 levels. however, macro service requests are acknowledged without regard to priority control or the ie flag. 529 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.2 interrupt service modes there are three m pd784938 interrupt service modes, as follows: ? vectored interrupt service ? macro service ? context switching 23.2.1 vectored interrupt service when an interrupt is acknowledged, the program counter (pc) and program status word (psw) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routi ne is executed. 23.2.2 macro service when an interrupt is acknowledged, cpu execution is temporarily suspended and a data transfer is performed by hardware. since macro service is performed without the intermediation of the cpu, it is not necessary to save or restore cpu statuses such as the program counter (pc) and program status word (psw) contents. this is therefore very effective in improving the cpu service time (see 23.8 macro service function ). 23.2.3 context switching when an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre- set vector address in the register bank, and at the same time the current program counter (pc) and program status word (psw) are saved in the register bank (see 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation and 23.7.2 context switching ). remark context refers to the cpu registers that can be accessed by a program while that program is being executed. these registers include general registers, the program counter (pc), program status word (psw), and stack pointer (sp). 530 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3 interrupt service control registers m pd784938 interrupt service is controlled for each interrupt request by various control registers that perform interrupt service specification. the interrupt control registers are listed in table 23-3. table 23-3. control registers register name symbol function interrupt control registers pic0 registers that perform each interrupt request generation recording, mask pic1 control, vectored interrupt service or macro service specification, context pic2 switching function enabling/disabling, and priority specification. pic3 cic00 cic01 cic10 cic11 cic20 cic21 cic30 pic4 pic5 adic seric sric csiic1 stic csiic seric2 sric2 csiic2 stic2 ieic1 ieic2 wic csiic3 interrupt mask registers mk0 maskable interrupt request mask control mk1 linked to mask control flags in interrupt control registers word accesses or byte accesses possible in-service priority register ispr records priority of interrupt request currently being acknowledged interrupt mode control register imc controls nesting of maskable interrupts for which lowest priority level (level 3) is specified watchdog timer mode register wdm specifies priority of interrupts due to nmi pin input and interrupts due to watchdog timer overflow program status word psw specifies enabling/disabling of maskable interrupt acknowledgment an interrupt control register is allocated to each interrupt source. the flags of each register perform control of the content s corresponding to the relevant bit position in the register. the interrupt control register flag names corresponding to each interrupt request signal are shown in table 23-4. 531 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 table 23-4. interrupt control register flags corresponding to interrupt request (1/2) default interrupt interrupt control registers priority request interrupt interrupt macro service priority speci- context switching signal request flag mask flag enable flag fication flag enable flag 0 intp0 pic0 pif0 pmk0 pism0 ppr00 pcse0 ppr01 1 intp1 pic1 pif1 pmk1 pism1 ppr10 pcse1 ppr11 2 intp2 pic2 pif2 pmk2 pism2 ppr20 pcse2 ppr21 3 intp3 pic3 pif3 pmk3 pism3 ppr30 pcse3 ppr31 4 intc00 cic00 cif00 cmk00 cism00 cpr000 ccse00 cpr001 5 intc01 cic01 cif01 cmk01 cism01 cpr010 ccse01 cpr011 6 intc10 cic10 cif10 cmk10 cism10 cpr100 ccse10 cpr101 7 intc11 cic11 cif11 cmk11 cism11 cpr110 ccse11 cpr111 8 intc20 cic20 cif20 cmk20 cism20 cpr200 ccse20 cpr201 9 intc21 cic21 cif21 cmk21 cism21 cpr210 ccse21 cpr211 10 intc30 cic30 cif30 cmk30 cism30 cpr300 ccse30 cpr301 11 intp4 pic4 pif4 pmk4 pism4 ppr40 pcse4 ppr41 12 intp5 pic5 pif5 pmk5 pism5 ppr50 pcse5 ppr51 13 intad adic adif admk adism adpr0 adcse adpr1 14 intser seric serif sermk serpr0 sercse serpr1 15 intsr sric srif srmk srism srpr0 srcse srpr1 intcsi1 csiic1 csiif1 csimk1 csiism1 csipr10 csicse1 csipr11 16 intst stic stif stmk stism stpr0 stcse stpr1 17 intcsi csiic csiif csimk csiism csipr0 csicse csipr1 18 intser2 seric2 serif2 sermk2 serpr20 sercse2 serpr21 19 intsr2 sric2 srif2 srmk2 srism2 srpr20 srcse2 srpr21 intcsi2 csiic2 csiif2 csimk2 csiism2 csipr20 csicse2 csipr21 532 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 table 23-4. interrupt control register flags corresponding to interrupt request (2/2) default interrupt interrupt control registers priority request interrupt interrupt macro service priority speci- context switching signal request flag mask flag enable flag fication flag enable flag 20 intst2 stic2 stif2 stmk2 stism2 stpr20 stcse2 serpr21 21 intie1 ieic1 ieif1 iemk1 ieism1 iepr10 iecse1 iepr11 22 intie2 ieic2 ieif2 iemk2 ieism2 iepr20 iecse2 iepr21 23 intw wic wif wmk wism wrp0 wcse wrp1 24 intcsi3 csiic3 csiif3 csimk3 csiism3 csipr30 csicse3 csipr31 533 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.1 interrupt control registers an interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for the corresponding interrupt request. the interrupt control register format is shown in figure 23-1. (1) priority specification flags ( pr1/ pr0) the priority specification flags specify the priority on an individual interrupt source basis for the 25 maskable interrupts. up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. among maskable interrupt sources, level 0 is the highest priority. if multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they are acknowledged in default priority order. these flags can be manipulated bit-wise by software. reset input sets all bits to 1. (2) context switching enable flag ( cse) the context switching enable flag specifies that a maskable interrupt request is to be serviced by context switching. in context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector address stored beforehand in the register bank, and at the same time the current contents of the program counter (pc) and program status word (psw) are saved in the register bank. context switching is suitable for real-time processing, since execution of interrupt servicing can be started faster than with normal vectored interrupt servicing. this flag can be manipulated bit-wise by software. (3) macro service enable flag ( ism) the macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by vectored interruption or context switching, or by macro service. when macro service processing is selected, at the end of the macro service (when the macro service counter reaches 0) the macro service enable flag is automatically cleared (to 0) by hardware (vectored interrupt service/context switching service). this flag can be manipulated bit-wise by software. reset input sets all bits to 0. (4) interrupt mask flag ( mk) an interrupt mask flag specifies enabling/disabling of vectored interrupt servicing and macro service processing for the interrupt request corresponding to that flag. the interrupt mask contents are not changed by the start of interrupt service, etc., and are the same as the interrupt mask register contents (see 23.3.2 interrupt mask registers (mk0/mk1) ). macro service processing requests are also subject to mask control, and macro service requests can also be masked with this flag. this flag can be manipulated by software. reset input sets all bits to 1. (5) interrupt request flag ( if) an interrupt request flag is set (to 1) by generation of the interrupt request that corresponds to that flag. when the interrupt is acknowledged, the flag is automatically cleared (to 0) by hardware. this flag can be manipulated by software. reset input sets all bits to 0. 534 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-1. interrupt control registers ( icn) (1/4) 7 pif0 pic0 6 pmk0 5 pism0 4 pcse0 3 0 2 0 1 ppr01 0 ppr00 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching service specification serviced by vectored interrupt serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interrupt service/ context switching service macro service ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffe0h pif1 pic1 pmk1 pism1 pcse1 0 0 ppr11 ppr10 r/w 43h 0ffe1h pif2 pic2 pmk2 pism2 pcse2 0 0 ppr21 ppr20 r/w 43h 0ffe2h pif3 pic3 pmk3 pism3 pcse3 0 0 ppr31 ppr30 r/w 43h 0ffe3h cif00 cic00 cmk00 cism00 ccse00 0 0 cpr001 cpr000 cif01 cmk01 cism01 ccse01 0 0 cpr011 cpr010 cif10 cmk10 cism10 ccse10 0 0 cpr101 cpr100 cif11 cmk11 cism11 ccse11 0 0 cpr111 cpr110 r/w 43h 0ffe4h cic01 r/w 43h 0ffe5h cic10 r/w 43h 0ffe6h cic11 r/w 43h 0ffe7h 535 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-1. interrupt control registers ( icn) (2/4) 7 cif20 cic20 6 cmk20 5 cism20 4 ccse20 3 0 2 0 1 cpr201 0 cpr200 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching service specification serviced by vectored interrupt serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interrupt service/ context switching service macro service ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffe8h cif21 cic21 cmk21 cism21 ccse21 0 0 cpr211 cpr210 r/w 43h 0ffe9h cif30 cic30 cmk30 cism30 ccse30 0 0 cpr301 cpr300 r/w 43h 0ffeah pif4 pic4 pmk4 pism4 pcse4 0 0 ppr41 ppr40 r/w 43h 0ffebh pif5 pic5 pmk5 pism5 pcse5 0 0 ppr51 ppr50 r/w 43h 0ffech adif adic admk adism adcse 0 0 adpr1 adpr0 r/w 43h 0ffedh serif seric sermk 0 sercse 0 0 serpr1 serpr0 r/w 43h 0ffeeh srif sric srmk srism srcse 0 0 srpr1 srpr0 r/w 43h 0ffefh 536 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-1. interrupt control registers ( icn) (3/4) 7 csiif1 csiic1 6 csimk1 5 csiism1 4 csicse1 3 0 2 0 1 csipr11 0 csipr10 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching service specification serviced by vectored interrupt serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interrupt service/ context switching service macro service ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0ffefh stif stic stmk stism stcse 0 0 stpr1 stpr0 r/w 43h 0fff0h csiif csiic csimk csiism csicse 0 0 csipr1 csipr0 r/w 43h 0fff1h serif2 seric2 sermk2 0 sercse2 00 serpr21 serpr20 r/w 43h 0fff2h srif2 sric2 srmk2 srism2 srcse2 0 0 srpr21 srpr20 csiif2 csimk2 csiism2 csicse2 0 0 csipr21 csipr20 stif2 stmk2 stism2 stcse2 0 0 stpr21 stpr20 r/w 43h 0fff3h csiic2 r/w 43h 0fff3h stic2 r/w 43h 0fff4h 537 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-1. interrupt control registers ( icn) (4/4) 7 ieif1 ieic1 6 iemk1 5 ieism1 4 iecse1 3 0 2 0 1 iepr11 0 iepr10 interrupt request priority specification priority 0 (highest priority) priority 1 priority 2 priority 3 prn1 (bit 1) 0 0 prn0 (bit 0) 1 0 10 11 context switching service specification serviced by vectored interrupt serviced by context switching csen (bit 4) 0 1 interrupt service mode specification vectored interrupt service/ context switching service macro service ismn (bit 5) 0 1 interrupt service enabling/disabling interrupt service enabled interrupt service disabled mkn (bit 6) 0 1 interrupt request generation presence/absence no interrupt request (interrupt signal not being generated) interrupt request state (interrupt signal being generated) ifn (bit 7) 0 1 address after reset r/w r/w 43h 0fff6h ieif2 iemk2 ieism2 iecse2 0 0 iepr21 iepr20 wif wmk wism wcse 0 0 wpr1 wpr0 csiif3 csimk3 csiism3 csicse3 0 0 csipr31 csipr30 ieic2 r/w 43h 0fff7h wic r/w 43h 0fff8h csiic3 r/w 43h 0fff9h 538 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.2 interrupt mask registers (mk0/mk1) mk0 and mk1 are composed of interrupt mask flags. mk0 and mk1 are 16-bit register which can be manipulated as 8-bit units, mk0l, mk0h, mk1l, and mk1h, as well as being manipulated as a 16-bit unit. in addition, each bit of mk0 and mk1 can be manipulated individually with a bit manipulation instruction. each interrupt mask flag controls enabling/disabling of the corresponding interrupt request. when an interrupt mask flag is set (to 1), acknowledgment of the corresponding interrupt request is disabled. when an interrupt mask flag is cleared (to 0), the corresponding interrupt request can be acknowledged as a vectored interrupt or macro service request. each interrupt mask flag in mk0 and mk1 is the same flag as the interrupt mask flag in the interrupt control register. mk0 and mk1 are provided for en bloc control of interrupt masking. reset input sets mk0 and mk1 to ffffh, and all maskable interrupts are disabled. figure 23-2. interrupt mask register (mk0, mk1) format (1/2) (1) byte accesses cmk11 mk0l cmk10 cmk01 cmk00 pmk3 pmk2 pmk1 pmk0 address after reset r/w r/w ffh 0ffach csimk1 srmk csimk2 srmk2 mk0h sermk admk pmk5 pmk4 cmk30 cmk21 cmk20 r/w ffh 0ffadh iemk2 mk1l iemk1 1 stmk2 sermk2 csimk stmk r/w ffh 0ffaeh interrupt request enabling/disabling specification interrupt service enabled interrupt service disabled mk 0 1 7654 3 21 0 1 mk1h 1 1 1 1 1 csimk3 wmk r/w ffh 0ffafh 539 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-2. interrupt mask register (mk0, mk1) format (2/2) (2) word accesses 7 cmk11 mk0 6 cmk10 5 cmk01 4 cmk00 3 pmk3 2 pmk2 1 pmk1 0 pmk0 interrupt request enabling/disabling specification interrupt service enabled interrupt service disabled mk 0 1 15 14 13 12 11 10 9 8 address after reset r/w r/w ffffh 0ffach csimk1 srmk sermk admk pmk5 pmk4 cmk30 cmk21 cmk20 7 iemk2 mk1 6 iemk1 5 1 4 stmk2 3 csimk2 srmk2 2 sermk2 1 csimk 0 stmk 15 14 13 12 11 10 9 8 1 1 11 11 csimk3 wmk address after reset r/w r/w ffffh 0ffaeh 540 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.3 in-service priority register (ispr) ispr shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being serviced. when a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (to 1), and remains set until the service program ends. when a non-maskable interrupt is acknowledged, the bit corresponding to the priority of that non-maskable interrupt is set (to 1), and remains set until the service program ends. when an reti instruction or retcs instruction is executed, the bit, among those set (to 1) in the ispr, that corresponds to the highest-priority interrupt request is automatically cleared (to 0) by hardware. the contents of ispr are not changed by execution of an retb or retcsb instruction. reset input clears ispr to 00h. figure 23-3. in-service priority register (ispr) format 7 nmis ispr 6 wdts 5 0 4 0 3 ispr3 2 ispr2 1 ispr1 0 ispr0 priority n interrupt not being acknowledged priority n interrupt being acknowledged (n = 0 to 3) isprn 1 0 nmi interrupt not being acknowledged nmi interrupt being acknowledged nmis 1 0 watchdog timer interrupt not being acknowledged watchdog timer interrupt being acknowledged wdts 1 0 address after reset r/w r 00h 0ffa8h priority level watchdog timer interrupt service state nmi service state caution in-service priority register (ispr) is a read-only register. there is a risk of misoperation if a write is performed on this register. 541 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.4 interrupt mode control register (imc) imc contains the prsl flag. the prsl flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. when imc is manipulated, the interrupt disabled state (di state) should be set first to prevent misoperation. imc can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. reset input sets imc to 80h. figure 23-4. interrupt mode control register (imc) format 7 prsl imc 6 0 5 0 4 0 3 0 2 0 1 0 0 0 control of nesting operations for maskable interrupts (lowest level) nesting between interrupts set as level 3 (lowest level) enabled nesting between interrupts set as level 3 (lowest level) disabled prsl 1 0 address after reset r/w r/w 80h 0ffaah 542 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.5 watchdog timer mode register (wdm) the prc bit of wdm specifies the priority of nmi pin input non-maskable interrupts and watchdog timer overflow non- maskable interrupts. wdm can be written to only by a dedicated instruction. this dedicated instruction, mov wdm, #byte, has a special code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual complements of 1. if the 3rd and 4th bytes of the operation code are not complements of 1, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec assembler, ra78k4, only the correct dedicated instruction is generated when mov wdm, #byte is written), system initialization should be performed by the program. other write instructions (mov wdm, a, and wdm, #byte instruction, set1 wdm.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to the wdm, and an interrupt such as an operand error interrupt is not generated. wdm can be read at any time by a data transfer instruction. reset input clears wdm to 00h. figure 23-5. watchdog timer mode register (wdm) format 7 run wdm 6 0 5 0 4 prc 3 0 2 wdi2 1 wdi1 0 0 watchdog timer interrupt request priority specification watchdog timer interrupt request < nmi pin input interrupt request watchdog timer interrupt request > nmi pin input interrupt request prc 1 0 address after reset r/w r/w 00h 0ffc2h see figure 13-2 in chapter 13 watchdog timer function for details. caution the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm, #byte). 543 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.3.6 program status word (psw) psw is a register that holds the current status regarding instruction execution results and interrupt requests. the ie flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the psw (pswl). pswl can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (ei/di). when a vectored interrupt is acknowledged or a brk instruction is executed, pswl is saved to the stack and the ie flag is cleared (to 0). pswl is also saved to the stack by the push psw instruction, and is restored from the stack by the reti, retb and pop psw instructions. when context switching or a brkcs instruction is executed, pswl is saved to a fixed area in the register bank, and the ie flag is cleared (to 0). pswl is restored from the fixed area in the register bank by an retcsi or retcsb instruction. reset input clears pswl to 00h. figure 23-6. program status word (pswl) format 7 s pswl 6 z 5 rss 4 ac 3 ie 2 p/v 1 0 0 cy after reset 00h ie interrupt acknowledgment enabling/disabling disabled enabled 1 0 used in normal instruction execution 544 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.4 software interrupt acknowledgment operations a software interrupt is acknowledged in response to execution of a brk or brkcs instruction. software interrupts cannot be disabled. 23.4.1 brk instruction software interrupt acknowledgment operation when a brk instruction is executed, the program status word (psw), program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0), the vector table (003eh/003fh) contents are loaded into the low-order 16 bits of the pc, and 0000b into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base area). the retb instruction must be used to return from a brk instruction software interrupt. caution the reti instruction must not be used to return from a brk instruction software interrupt. 23.4.2 brkcs instruction software interrupt (software context switching) acknowledgment operation the context switching function can be initiated by executing a brkcs instruction. the register bank to be used after context switching is specified by the brkcs instruction operand. when a brkcs instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (psw) and program counter (pc) are saved in the register bank. figure 23-7. context switching operation by execution of a brkcs instruction the retcsb instruction is used to return from a software interrupt due to a brkcs instruction. the retcsb instruction must specify the start address of the interrupt service program for the next time context switching is performed by a brkcs instruction. this interrupt service program start address must be in the base area. caution the retcs instruction must not be used to return from a brkcs instruction software interrupt. register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 3 register bank switching (rbs0 to rbs2 ? n) 4 rss ? 0 ( ie ? 0 ) 1 save 2 save (bits 8 to 11 of temporary register) 6 exchange 5 save pc 15 to 0 pc 19 to16 0000b temporary register psw 545 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-8. return from brkcs instruction software interrupt (retcsb instruction operation) pc 19 to 16 pc 15 to 0 1 restoration 3 transfer 4 restoration (to original register bank) 2 restoration psw vvp uup te wl retcsb instruction operand register bank n (n = 0 to 7) a r5 r7 d h b x r4 r6 c 546 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.5 operand error interrupt acknowledgment operation an operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of a mov stbc, #byte instruction , location instruction or a mov wdm, #byte instruction does not match the 4th byte of the operand. operand error interrupts cannot be disabled. when an operand error interrupt is generated, the program status word (psw) and the start address of the instruction that caused the error are saved to the stack, the ie flag is cleared (to 0), the vector table value is loaded into the program counter (pc), and a branch is performed (within the base area only). as the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an retb instruction at the end of the operand error interrupt service program will result in generation of another operand error interrupt. you should therefore either process the address in the stack or initialize the program by referring to 23.12 restoring interrupt function to initial state . 23.6 non-maskable interrupt acknowledgment operation non-maskable interrupts are acknowledged even in the interrupt disabled state. non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non- maskable interrupt of higher priority. the relative priorities of non-maskable interrupts are set by the prc bit of the watchdog timer mode register (wdm) (see 23.3.5 watchdog timer mode register (wdm) ). except in the cases described in 23.9 when interrupt requests and macro service are temporarily held pending , a non-maskable interrupt request is acknowledged immediately. when a non-maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0), the in-service priority register (ispr) bit corresponding to the acknowledged non-maskable interrupt is set (to 1), the vector table contents are loaded into the pc, and a branch is performed. the ispr bit that is set (to 1) is the nmis bit in the case of a non-maskable interrupt due to edge input to the nmi pin, and the wdts bit in the case of watchdog timer overflow. when the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable interrupt currently being executed are held pending. a pending non-maskable interrupt is acknowledge after completion of the non-maskable interrupt service program currently being executed (after execution of the reti instruction). however, even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service program. 547 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-9. non-maskable interrupt request acknowledgment operations (1/2) (a) when a new nmi request is generated during nmi service program execution main routine nmi request nmi request (nmis = 1) nmi request held pending since nmis = 1 pending nmi request is processed (b) when a watchdog timer interrupt request is generated during nmi service program execution (when the watchdog timer interrupt priority is higher (when prc in the wdm = 1)) main routine nmi request watchdog timer interrupt request 548 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-9. non-maskable interrupt request acknowledgment operations (2/2) (c) when a watchdog timer interrupt request is generated during nmi service program execution (when the nmi interrupt priority is higher (when prc in the wdm = 0)) main routine nmi request watchdog timer interrupt request pending watchdog timer interrupt is processed watchdog timer interrupt held pending since prc = 0 (d) when an nmi request is generated twice during nmi service program execution main routine nmi request nmi request held pending since nmi service program is being executed nmi request held pending since nmi service program is being executed nmi request was generated more than once, but is only acknowledged once 549 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 cautions 1. macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. 2. the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 3. non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9 when interrupt requests and macro service are temporarily held pending. therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (see table 3-5 in 3.9 special function registers (sfr)), and the cpu becomes deadlocked, or an unexpected signal is output from a pin, or the pc and psw are written to an address in which ram is not mounted, with the result that the return from the non-maskable interrupt service program to the main routine is not performed normally and an inadvertent program routine occurs. therefore, the program following reset release must be as shown below. cseg at 0 dw strt cseg base strt: location 0fh; or location 0 movg sp, #imm24 550 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.7 maskable interrupt acknowledgment operation a maskable interrupt can be acknowledged when the interrupt request flag is set (to 1) and the mask flag for that interrupt is cleared (to 0). when servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately. in the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt enabled state (when the ie flag is set (to 1)) if the priority of that interrupt is one for which acknowledgment is permitted. if maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by the priority specification flag is acknowledged. if the interrupts have the same priority specified, they are acknowledged in accordance with their default priorities. a pending interrupt is acknowledged when a state in which it can be acknowledged is established. the interrupt acknowledgment algorithm is shown in figure 23-10. 551 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-10. interrupt acknowledgment processing algorithm no if = 1 mk = 0 ism = 1 cse = 1 ie = 1 higher priority than interrupt currently being serviced? higher priority than other existing interrupt requests? highest default priority among interrupt requests of same priority? vectored interrupt generation interrupt request? yes no interrupt mask released? yes no yes yes yes yes no no interrupt enabled state? macro service? no no no interrupt request held pending yes context switching? context switching generation yes highest default priority among macro service requests? macro service processing execution interrupt request held pending no yes 552 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.7.1 vectored interrupt when a vectored interrupt maskable interrupt request is acknowledged, the program status word (psw) and program counter (pc) are saved in that order to the stack, the ie flag is cleared (to 0) (the interrupt disabled state is set), and the in-service priority register (ispr) bit corresponding to the priority of the acknowledged interrupt is set (to 1). also, data in the vector table predetermined for each interrupt request is loaded into the pc, and a branch is performed. the return from a vectored interrupt is performed by means of the reti instruction. caution when a maskable interrupt is acknowledged by vectored interrupt, the reti instruction must be used to return from the interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. 23.7.2 context switching initiation of the context switching function is enabled by setting (to 1) the context switching enable flag of the interrupt control register. when an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified by 3 bits of the lower address (even address) of the corresponding vector table address is selected. the vector address stored beforehand in the selected register bank is transferred to the program counter (pc), and at the same time the contents of the pc and program status word (psw) up to that time are saved in the register bank and a branch is made to the interrupt service program. figure 23-11. context switching operation by generation of an interrupt request register bank (0 to 7) a b r5 r7 x c r4 r6 d h vp up e l v u t w register bank n (n = 0 to 7) 7 transfer 6 exchange 4 2 save (temporary register bits 8 to 11) 5 save 1 save pc 15 to 0 pc 19 to 16 0000b temporary register psw n 3 register bank switching (rbs0 to rbs2 ? n) vector table rss ? 0 ( ie ? 0 ) 553 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 the retcs instruction is used to return from an interrupt that uses the context switching function. the retcs instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. this interrupt service program start address must be in the base area. caution the retcs instruction must be used to return from an interrupt serviced by context switching. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. figure 23-12. return from interrupt that uses context switching by means of retcs instruction pc 19 to 16 pc 15 to 0 2 restoration 4 restoration (to original register bank) psw retcs instruction operand 3 transfer register bank n (n = 0 to 7) vvp uup tde wh l ax r5 r4 r7 r6 bc 1 restoration 554 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.7.3 maskable interrupt priority levels the m pd784938 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. multiple interrupts can be controlled by priority levels. there are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag. in priority control by means of default priority, interrupt service is perform ed in accordance with the priority preassigned to each interrupt request (default priority) (see table 23-2 ). in programmable priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. interrupt requests for which multiple interruption is permitted are shown in table 23-5. since the ie flag is cleared (to 0) automatically when an interrupt is acknowledged, when multiple interruption is used, the ie flag should be set (to 1) to enable interrupts by executing an ei instruction in the interrupt service program, etc. table 23-5. multiple interrupt servicing priority of interrupt currently ispr value ie flag in psw prsl flag in acknowledgeable maskable interrupts being acknowledged imc no interrupt being 00000000 0 ? all macro service only acknowledged 1 ? all maskable interrupts 3 00001000 0 ? all macro service only 1 0 ? all maskable interrupts 1 1 ? all macro service ? maskable interrupts specified as priority 0/1/2 2 0000 100 0 ? all macro service only 1 ? all macro service ? maskable interrupts specified as priority 0/1 1 0000 10 0 ? all macro service only 1 ? all macro service ? maskable interrupts specified as priority 0 0 0000 1 ? all macro service only non-maskable interrupts 1000 ? all macro service only 0100 1100 555 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-13. examples of servicing when another interrupt request is generated during interrupt service (1/3) main routine ei ei ei interrupt request a (level 3) interrupt request b (level 2) interrupt request d (level 2) interrupt request e (level 2) interrupt request f (level 3) interrupt request g (level 1) a servicing b servicing c servicing d servicing e servicing f servicing g servicing h servicing since interrupt request b has a higher priority than interrupt request a, and interrupts are enabled, interrupt request b is acknowledged. the priority of interrupt request d is higher than that of interrupt request c, but since interrupts are disabled, interrupt request d is held pending. although interrupts are enabled, interrupt request f is held pending since it has a lower priority than interrupt request e. although interrupts are enabled, interrupt request h is held pending since it has the same priority as interrupt request g. interrupt request h (level 1) ei interrupt request c (level 3) 556 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-13. examples of servicing when another interrupt request is generated during interrupt service (2/3) main routine ei ei interrupt request i (level 1) interrupt request k (level 2) interrupt request n (level 2) macro service request j (level 2) i servicing j macro service k servicing l servicing m servicing n servicing o servicing p servicing the macro service request is serviced irrespective of interrupt enabling/disabling and priority. the interrupt request is held peding since it has a lower priority than interrupt request k. interrupt request m generated after interrupt request l has a higher priority, and is therefore acknowledged first. since servicing of interrupt request n performed in the interrupt disabled state, interrupt requests o and p are held pending. after interrupt request n servicing, the pending interrupt requests are acknowledged. although interrupt request o was generated first, interrupt request p has a higher priority and is therefore acknowledged first. interrupt request l (level 3) interrupt request m (level 1) interrupt request o (level 3) interrupt request p (level 1) 557 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-13. examples of servicing when another interrupt request is generated during interrupt service (3/3) main routine ei ei ei ei ei ei interrupt request q (level 3) interrupt request s (level 1) interrupt request u (level 0) interrupt request v (level 0) w macro service q servicing r servicing s servicing t servicing u servicing v servicing x servicing y servicing z servicing interrupt request x (level 1) interrupt request r (level 2) interrupt request t (level 0) interrupt request y note (level 2) interrupt request w (level 3) multiple acknowledgment of levels 3 to 0. if the prsl bit of the imc register is set (to 1), only macro service requests and non- maskable interrupts generate nesting beyond this. if the prsl bit of the imc register is cleared (to 0), level 3 interrupts can also be nested during level 3 interrupt servicing (see figure 23-15 ). even though the interrupt enabled state is set during servicing of level 0 interrupt request u, the interrupt request is not acknowledged but held pending even though its priority is 0. however, the macro service request is acknowledged and serviced irrespective of its level and even though there is a peding interrupt with a higher priority level. pending interrupt requests y and z are acknowledged after servicing of interrupt request x. as interrupt requests y and z have the same priority level, interrupt request z which has the higher default priority is acknowledged first, irrespective of the order in which the interrupt requests were generated. interrupt request z note (level 2) notes 1. low default priority 2. high default priority remarks 1. a to z in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high/low default priorities in the figure indicate the relative priority levels of the two interrupt requests. 558 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-14. examples of servicing of simultaneously generated interrupts main routine ei interrupt request a (level 2) macro service request b (level 3) macro service request c (level 1) interrupt request d (level 1) interrupt request e (level 1) macro service request f (level 1) default priority order a > b > c > d > e > f macro service request b servicing macro service request c servicing macro service request f servicing interrupt request d servicing interrupt request e servicing interrupt request a servicing when requests are generated simultaneously, they are acknowledged in the order starting with macro service. macro service requests are acknowledged in default priority order (b/c/f) (not dependent upon the programmable priority order). as interrupt requests are acknowledged in high-to-low priority level order, d and e are acknowledged first. as d and e have the same prority level, the interrupt request with the higher default priority, d, is acknowledged first. remark a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 559 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-15. differences in level 3 interrupt acknowledgment according to imc register setting main routine ei ei interrupt request a (level 3) interrupt request b (level 3) a servicing b servicing interrupt request c (level 3) interrupt request d (level 3) c servicing d servicing interrupt request e note1 (level 3) interrupt request f note2 (level 3) f servicing e servicing imc ? 80h ei main routine imc ? 00h ei main routine ei ei the prsl bit of the imc is set to 1, and nesting between level 3 interrupts is disabled. even though interrupts are enabled, interrupt request b is held pending since it has the same priority as interrupt request a. the prsl bit of the imc is set to 0, so that a level 3 interrupt is acknowledged even during level 3 interrupt servicing (nesting is possible). since level 3 interrupt request c is being serviced in the interrupt enabled state and prsl = 0, interrupt request d, which is also level 3, is acknowledged. as interrupt requests e and f are the same level, the one with the higher default priority, f, is acknowledged first. when the interrupt enabled state is set during servicing of interrupt request f, pending interrupt request e is acknowledged since prsl = 0. imc ? 00h notes 1. low default priority 2. high default priority remarks 1. a to f in the figure are arbitrary names used to differentiate between the interrupt requests and macro service requests. 2. high or low in default priorities in the figure indicate the relative priority levels of the two interrupt requests. 560 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8 macro service function 23.8.1 outline of macro service function macro service is one of the method of interrupts servicing. in the normal interrupt, the start address in the interrupt servic e program is loaded into the program counter (pc) by saving the pc or program status word (psw), in the macro service, however, another processing (mainly data transfers) is performed instead of these processing. this processing enables a quick response to interrupt requests. moreover, processing time can be reduced because the higher transfer speed can be obtained. in addition, there is another advantage in simplifying the vectored interrupt program since the vectored interrupt is generated after the specified number of processing. figure 23-16. differences between vectored interrupt and macro service processing macro service context switching note 1 vectored interrupt note 1 vectored interrupt interrupt request generation main routine main routine main routine main routine macro service processing main routine note 2 note 4 note 4 note 3 interrupt servicing main routine sel rbn interrupt servicing restore pc, psw save general registers initialize general registers interrupt servicing restore general registers main routine restore pc & psw main routine notes 1. when register bank switching is used, and an initial value has been set in the register beforehand 2. register bank switching by context switching, saving of pc and psw 3. register bank, pc and psw restoration by context switching 4. pc and psw saved to the stack, vector address loaded into pc 23.8.2 types of macro service macro service can be used with the 23 kinds of interrupt shown in table 23-6. there are four kinds of operation, which can be used to suit the application. 561 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 table 23-6. interrupts for which macro service can be used default interrupt request generation source generating unit macro service control priority word address 0 intp0 (pin input edge detection) edge detection 0fe06h 1 intp1 (pin input edge detection) 0fe08h 2 intp2 (pin input edge detection) 0fe0ah 3 intp3 (pin input edge detection) 0fe0ch 4 intc00 (tm0-cr00 match signal generation) timer/event counter 0 0fe0eh 5 intc01 (tm0-cr01 match signal generation) 0fe10h 6 intc10 (tm1-cr10 or tm1w-cr10w match signal generation) timer/event counter 1 0fe12h 7 intc11 (tm1-cr11 or tm1w-cr11w match signal generation) 0fe14h 8 intc20 (tm2-cr20 or tm2w-cr20w match signal generation) timer/event counter 2 0fe16h 9 intc21 (tm2-cr21 or tm2w-cr21w match signal generation) 0fe18h 10 intc30 (tm3-cr30 or tm3w-cr30w match signal generation) timer 3 0fe1ah 11 intp4 (pin input edge detection) edge detection 0fe1ch 12 intp5 (pin input edge detection) 0fe1eh 13 intad (a/d conversion end) a/d converter 0fe20h 14 intsr (asynchronous serial interface reception end) asynchronous 0fe24h intcsi1 (clocked serial interface transfer end) serial interface/ 15 intst (asynchronous serial interface transmission end) clocked serial 0fe26h interface 1 16 intcsi (clocked serial interface transfer end) clocked serial 0fe28h interface 17 intsr2 (asynchronous serial interface 2 reception end) asynchronous 0fe2ch intcsi2 (clocked serial interface 2 transfer end) serial interface 2/ 18 intst2 (asynchronous serial interface 2 transmission end) clocked serial 0fe2eh interface 2 19 intie1 (iebus data access request) iebus controller 0fe32h 20 intie2 (iebus communication error and communication end) 0fe34h 21 intw (watch timer output) watch timer 0fe36h 22 intcsi3 (clocked serial interface 3 transfer end) clocked serial 0fe38h interface 3 remarks 1. the default priority is a fixed number. this indicates the order of priority when macro service requests are generated simultaneously, 2. the intsr and intcsi1 interrupts are generated by the same hardware (they cannot both be used simultaneously). therefore, although the same hardware is used for the interrupts, two names are provided, for use in each of the two modes. the same applies to intsr2 and intcsi2. 562 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 there are four kinds of macro service, as shown below. (1) type a one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. memory that can be used in the transfers is limited to internal ram addresses 0fe00h to 0feffh when the location 0 instruction is executed, and addresses 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the specification method is simple and is suitable for low-volume, high-speed data transfers. (2) type b as with type a, one byte or one word of data is transferred between a special function register (sfr) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. the sfr and memory to be used in the transfers is specified by the macro service channel (the entire 1-mbyte memory space can be used). this is a general version of type a, suitable for large volumes of transfer data. (3) type c data is transferred from memory to two special function registers (sfr) each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed. with type c macro service, not only are data transfers performed to two locations in response to a single interrupt request, but it is also possible to add output data ring control and a function that automatically adds data to a compare register. the entire 1-mbyte memory space can be used. type c is mainly used with the intc10 and intc11 interrupts, and is used for stepping motor control, etc., by macro service, with p0l or p0h and cr10, cr10w, cr11, and cr11w used as the sfrs to which data is transferred. (4) counter mode this mode is to decrement the macro service counter (msc) when an interrupt occurs and is used to count the division operation of an interrupt and interrupt generation circuit. when msc is 0, a vector interrupt can be generated. to restart the macro service, msc must be set again. msc is fixed to 16 bits and cannot be used as an 8-bit counter. 563 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.3 basic macro service operation interrupt requests for which the macro service processing generated by the algorithm shown in figure 23-10 can be specified are basically serviced in the sequence shown in figure 23-17. interrupt requests for which macro service processing can be specified are not affected by the status of the ie flag, but are disabled by setting (to 1) an interrupt mask flag in the interrupt mask register (mk0). macro service processing can be executed in the interrupt disabled state and during execution of an interrupt service program. figure 23-17. macro service processing sequence the macro service type and transfer direction are determined by the value set in the macro service control word mode register. transfer processing is then performed using the macro service channel specified by the channel pointer according to the macro service type. the macro service channel is memory which contains the macro service counter which records the number of transfers, the transfer destination and transfer source pointers, and data buffers, and can be located at any address in the range fe00h to feffh when the location 0 instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed. no msc = 0? vcie = 1? msc ? msc-1 interrupt service mode bit ? 0 interrupt request flag ? 0 yes no yes macro service processing execution ; data transfer, real-time output port control ; decrement macro service counter (msc) interrupt request generation execute next instruction generation of interrupt request for which macro service processing can be specified 564 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.4 operation at end of macro service in macro service, processing is performed the number of times specified during execution of another program. macro service ends when the processing has been performed the specified number of times (when the macro service counter (msc) reaches 0). either of two operations may be performed at this point, as specified by the vcie bit (bit 7) of the macro service mode register for each macro service. (1) when vcie bit is 0 in this mode, an interrupt is generated as soon as the macro service ends. figure 23-18 shows an example of macro service and interrupt acknowledgment operations when the vcie bit is 0. this mode is used when a series of operations end with the last macro service processing performed, for instance. it is mainly used in the following cases: ? asynchronous serial interface receive data buffering (intsr/intsr2) ? a/d conversion result fetch (intad) ? compare register update as the result of a match between a timer register and the compare register (intc00/ intc01/intc10/intc11/intc20/intc21/intc30) ? timer/counter capture register read due to edge input to the intpn pin (intp0/intp1/intp2/intp3) figure 23-18. operation at end of macro service when vcie = 0 main routine ei main routine ei macro service request last macro service request macro service processing macro service processing servicing of interrupt request due to end of macro service other interrupt request last macro service request servicing of other interrupt macro service processing servicing of interrupt request due to end of macro service at the end of macro service (msc = 0), an interrupt request is generated and acknowledged. if the last macro service is performed when the interrupt due to the end of macro service cannot be acknowledged while other interrupt servicing is being executed, tec., that interrupt is held pending until it can be acknowledged. 565 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) when vcie bit is 1 in this mode, an interrupt is not generated after macro service ends. figure 23-19 shows an example of macro service and interrupt acknowledgment operations when the vcie bit is 1. this mode is used when the final operation is to be started by the last macro service processing performed, for instance. it is mainly used in the following cases: ? clocked serial interface receive data transfers (intcsi/intcsi1/intcsi2) ? asynchronous serial interface data transfers (intst/intst2) ? to stop a stepping motor in the case (intc10/intc11) of stepping motor control by means of macro service type c using the real-time output port and timer/counter. figure 23-19. operation at end of macro service when vcie = 1 main routine ei macro service request last macro service request interrupt request due to the end of the hardware operation started by the last macro service processing macro service processing processing of last macro service interrupt servicing 566 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.5 macro service control registers (1) macro service control word the m pd784938s macro service function is controlled by the macro service control mode register and macro service channel pointer. the macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer. the macro service mode register and macro service channel pointer are mapped onto the part of the internal ram shown in figure 23-20 for each macro service as the macro service control word. when macro service processing is performed, the macro service mode register and channel pointer values corresponding to the interrupt requests for which macro service processing can be specified must be set beforehand. figure 23-20. macro service control word format reserved word channel pointer mode register 0fe39h 0fe38h 0fe37h 0fe36h 0fe35h 0fe34h 0fe33h 0fe32h 0fe2fh 0fe2eh 0fe2dh 0fe2ch csichp3 csimmd3 wchp wmmd iechp2 iemmd2 iechp1 iemmd1 stchp2 stmmd2 srchp2/csichp2 srmmd2/csimmd2 0fe29h 0fe28h 0fe27h 0fe26h 0fe25h 0fe24h csichp csimmd stchp stmmd srchp/csichp1 srmmd/csimmd1 0fe21h 0fe20h 0fe1fh 0fe1eh 0fe1dh 0fe1ch 0fe1bh 0fe1ah 0fe19h 0fe18h 0fe17h 0fe16h 0fe15h 0fe14h 0fe13h 0fe12h 0fe11h 0fe10h 0fe0fh 0fe0eh 0fe0dh 0fe0ch 0fe0bh 0fe0ah 0fe09h 0fe08h 0fe07h 0fe06h adchp admmd pchp5 pmmd5 pchp4 pmmd4 cchp30 cmmd30 cchp21 cmmd21 cchp20 cmmd20 cchp11 cmmd11 cchp10 cmmd10 cchp01 cmmd01 cchp00 cmmd00 pchp3 pmmd3 pchp2 pmmd2 pchp1 pmmd1 pchp0 pmmd0 intst2 channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register channel pointer mode register y t intsr2/intcsi2 y t intcsi y t intst y t intad y t intp5 y t intp4 y t intc30 y t intc21 y t intc20 y t intc11 y t intc10 y t intc01 intc00 y t intp3 y t intp2 y t intp1 y t intp0 y t y t intsr/intcsi1 y t source address channel pointer mode register intcsi3 y t channel pointer mode register channel pointer mode register channel pointer mode register intw y t intie2 y t intie1 y t 567 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) macro service mode register the macro service mode register is an 8-bit register that specifies the macro service operation. this register is written in internal ram as part of the macro service control word (see figure 23-20 ). the format of the macro service mode register is shown in figure 23-21. figure 23-21. macro service mode register format (1/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 0 1 0 cht1 0 0 0 cht2 0 0 0 cht3 1 0 0 mod2 mod1 mod0 000 001 010 011 100 101 110 111 vcie 0 1 type a counter mode counter decrement data transfer direction memory ? sfr data size: 1 byte data transfer direction sfr ? memory data transfer direction memory ? sfr data size: 1 byte data transfer direction sfr ? memory data transfer direction memory ? sfr data size: 2 bytes data transfer direction sfr ? memory data transfer direction memory ? sfr data size: 2 bytes data transfer direction sfr ? memory not generated (next interrupt processing is vectored interrupt) generated interrupt request when msc = 0 type b 568 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-21. macro service mode register format (2/2) 7 vcie 6 mod2 5 mod1 4 mod0 3 cht3 2 cht2 1 cht1 0 cht0 cht0 1 1 0 cht1 1 0 0 cht2 1 1 1 cht3 1 1 1 0 1 1 1 mod2 mod1 mod0 000 001 010 011 100 101 110 111 type c decrements mpd increments mpd retains mpt decrements mpt retains mpt increments mpt data size for timer specified by mpt: 1 byte no automatic addition no ring control ring control automatic addition no ring control ring control no ring control ring control no ring control ring control data size for timer specified by mpt: 2 bytes no automatic addition automatic addition vcie 0 1 generated not generated (next interrupt processing is vectored interrupt) interrupt request when msc = 0 (3) macro service channel pointer the macro service channel pointer specifies the macro service channel address. the macro service channel can be located in the 256-byte space from fe00h to feffh when the location 0 instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed, and the high-order 16 bits of the address are fixed. therefore, the low-order 8 bits of the data stored to the highest address of the macro service channel are set in the macro service channel pointer. 569 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.6 macro service type a (1) operation data transfers are performed between buffer memory in the macro service channel and an sfr specified in the macro service channel. with type a, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. type a macro service is useful when the amount of data to be transferred is small, as transfers can be performed at high speed. 570 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-22. macro service data transfer processing flow (type a) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing read msc contents (n) calculate buffer address note read sfr pointer contents determine transfer direction sfr ? memory memory ? sfr read buffer contents, then transfer read data to specified sfr specified sfr contents, then transfer read data to buffer msc ? msc-1 msc = 0? no yes clear (to 0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type a yes no 1-byte transfer: m-n-1 2-byte transfer: m-n 2-1 note macro service request acknowledgment clear (to 0) interrupt request flag (if) end end 571 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) macro service channel configuration the channel pointer and 8-bit macro service counter (msc) indicate the buffer address in internal ram (fe00h to feffh when the location 0 instruction is executed, or ffe00h to ffeffh when the location 0fh instruction is executed) which is the transfer source or transfer destination (see figure 23-23 ). in the channel pointer, the low- order 8 bits of the address are written to the macro service counter in the macro service channel. the sfr involved with the access is specified by the sfr pointer (sfrp). the low-order 8 bits of the sfr address are written to the sfrp. 572 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-23. type a macro service channel (a) 1-byte transfers (b) 2-byte transfers 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high-order addresses low-order addresses macro service buffer address = (channel pointer) ?(macro service counter) ?1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mcs = 1 mcs = 2 mcs = n 70 macro service counter (msc) sfr pointer (sfrp) macro service buffer 1 macro service buffer 2 macro service buffer n channel pointer mode register macro service control word macro service channel high-order addresses low-order addresses macro service buffer address = (channel pointer) ?(macro service counter) 2 ?1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mcs = 1 mcs = 2 mcs = n (high-order byte) (low-order byte) (high-order byte) (low-order byte) (high-order byte) (low-order byte) 573 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (3) example of use of type a an example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in on-chip ram. figure 23-24. asynchronous serial reception (internal ram) 0fe7fh channel pointer 7fh mode register 11h note low-order 8 bits of rxb address type a, sfr ? memory, 8-bit transfer, interrupt request generation when msc = 0 ? internal bus msc 0eh sfrp 8ch note 0fe70h r x d/p30 intsr macro service request receive buffer (rxb) shift register remark addresses in the figure are the values when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 574 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.7 macro service type b (1) operation data transfers are performed between a data area in memory and an sfr specified by the macro service channel. with type b, the data transfer direction can be selected as memory-to-sfr or sfr-to-memory. data transfers are performed the number of times set beforehand in the macro service counter. one macro service processing transfers 8-bit or 16-bit data. this type of macro service is macro service type a for general purposes and is ideal for processing a large amount of data because up to 64 kbytes of data buffer area when 8-bit data is transferred or 1 mbyte of data buffer area when 16-bit data is transferred can be set in any address space. 575 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-25. macro service data transfer processing flow (type b) read contents of macro service mode register determine channel type other to other macro service processing 1-byte transfer: +1 2-byte transfer: +2 determine transfer direction sfr ? memory memory ? sfr msc ? msc? msc = 0? no yes clear (to 0) interrupt service mode bit (ism) vcie = 1? (vectored interrupt request generation) type b yes no increment mp note read data from sfr, and write to memory addressed by mp read data from memory, and write to sfr specified by sfr pointer select transfer source memory with macro service pointer (ms) note select transfer source sfr with sfr pointer end end macro service request acknowledgment read channel pointer contents (m) clear (to 0) interrupt request flag (if) 576 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) macro service channel configuration the macro service pointer (mp) indicates the data buffer area in the 1-mbyte memory space that is the transfer destination or transfer source. the low-order 8 bits of the sfr that is the transfer destination or transfer source is written to the sfr pointer (sfrp). the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the macro service channel that stores the mp, sfrp and msc is located in internal ram space addresses 0fe00h to 0feffh when the location 0 instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 23-26. in the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. figure 23-26. type b macro service channel note bits 20 to 23 must be set to 0. macro service counter (msc) sfr pointer (sfrp) (bits 8 to 15) (bits 0 to 7) (bits 16 to 23) note (bits 8 to 15) (bits 0 to 7) channel pointer mode register macro service pointer (mp) macro service control word low-order addresses macro service channel high-order addresses sfr buffer area macro service buffer address = macro service pointer 577 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (3) example of use of type b an example is shown below in which parallel data is input from port 3 in synchronization with an external signal. the intp4 external interrupt pin is used for synchronization with the external signal. figure 23-27. parallel data input synchronized with external interrupts 64 k memory space macro service control word, macro service channel (internal ram) 0fe6eh buffer area note low-order 8 bits of port 3 address - 1 +1 internal bus port 3 p37 p36 p35 p34 p33 p32 p31 p30 intp4 edge detection macro service request intp4 msc 00h 20h 03h mp 00h a0h 00h sfrp type b, sfr ? memory, 8-bit transfer, interrupt request generation when msc = 0 channel pointer 6eh mode register 18h 0a01fh 0a000h note remark macro service channel addresses in the figure are the values when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 578 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-28. parallel data input timing intp4 port 3 data fetch (macro service) 579 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.8 macro service type c (1) operation in type c macro service, data in the memory specified by the macro service channel is transferred to two sfrs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the sfrs can be freely selected). an 8-bit or 16-bit timer sfr can be selected. in addition to the basic data transfers described above, type c macro service, the following functions can be added to type c macro service to reduce the size of the buffer area and alleviate the burden on software. these specifications are made by using the mode register of the macro service control word. (a) updating of timer macro service pointer it is possible to choose whether the timer macro service pointer (mpt) is to be kept as it is or incremented/ decremented. the mpt is incremented or decremented in the same direction as the macro service pointer (mpd) for data. (b) updating of data macro service pointer it is possible to choose whether the data macro service pointer (mpd) is to be incremented or decremented. (c) automatic addition the current compare register value is added to the data addressed by the timer macro service pointer (mpt), and the result is transferred to the compare register. if automatic addition is not specified, the data addressed by the mpt is simply transferred to the compare register. (d) ring control an output data pattern of the length specified beforehand is automatically output repeatedly. 580 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-29. macro service data transfer processing flow (type c) (1/2) read contents of macro service mode register determine channel type read channel pointer contents (m) other to other macro service processing note transfer data to compare register automatic addition specified? no increment mpt? no increment mpd? type c yes read memory addressed by mpt retain mpt? no increment mpd (+1) no yes yes yes increment mpt note 1 1-byte transfer: +1 2-byte transfer: +2 add data to compare register decrement mpd (?) decrement mpt transfer data to buffer register read memory addressed by mpd macro service request acknowledgment 581 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-29. macro service data transfer processing flow (type c) (2/2) no no yes no no yes yes yes no yes 1 end ring control? ring counter = 0? increment mpd? msc = 0? vcie = 1? subtract modulo register contents from data macro service pointer (mpd), and return pointer to start address add modulo register contents to data macro service pointer (mpd), and return pointer to start address msc ? msc? clear (to 0) interrupt service mode bit (ism) clear (to 0) interrupt request flag (if) load modulo register contents into ring counter end decrement ring counter (vectored interrupt request generation) 582 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) macro service channel configuration there are two kinds of type c macro service channel, as shown in figure 23-30. the timer macro service pointer (mpt) mainly indicates the data buffer area in the 1-mbyte memory space to be transferred or added to the timer/event counter compare register. the data macro service pointer (mpd) indicates the data buffer area in the 1-mbyte memory space to be transferred to the real-time output port. the modulo register (mr) specifies the number of repeat patterns when ring control is used. the ring counter (rc) holds the step in the pattern when ring control is used. when initialization is performed, the same value as in the mr is normally set in this counter. the macro service counter (msc) is a 16-bit counter that specifies the number of data transfers. the low-order 8 bits of the sfr that is the transfer destination is written to the timer sfr pointer (tsfrp) and data sfr pointer (dsfrp). the macro service channel that stores these pointers and counters is located in internal ram space addresses 0fe00h to 0feffh when the location 0 instruction is executed, or 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the macro service channel is indicated by the channel pointer as shown in figure 23-30. in the channel pointer, the low-order 8 bits of the address are written to the macro service counter in the macro service channel. figure 23-30. type c macro service channel (1/2) (a) no ring control note bits 20 to 23 must be set to 0. macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 0 to 7) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note channel pointer mode register timer macro service pointer (mpt) data macro service pointer (mpd) data sfr pointer (dsfrp) macro service control word low-order addresses macro service channel high-order addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer 583 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-30. type c macro service channel (2/2) (b) with ring control note bits 20 to 23 must be set to 0. (3) examples of use of type c (a) basic operation an example is shown below in which the output pattern to the real-time output port and the output interval are directly controlled. update data is transferred from the two data storage areas set in the 1-mbyte space beforehand to the real-time output function buffer register (p0l) and the compare register (cr10). macro service counter (msc) timer sfr pointer (tsfrp) (bits 8 to 15) (bits 8 to 15) (bits 8 to 15) (bits 0 to 7) (bits 0 to 7) (bits 0 to 7) (bits 16 to 23) note (bits 16 to 23) note ring counter (rc) channel pointer mode register timer macro service pointer (mpt) data sfr pointer (dsfrp) data macro service pointer (mpd) modulo register (mr) macro service control word low-order addresses macro service channel high-order addresses tsfr dsfr timer buffer area data buffer area macro service buffer address = macro service pointer 584 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-31. stepping motor open loop control by real-time output port 1 m memory space macro service control word, macro service channel (internal ram) timer counter 1 tm1 output latch p0 0fe5eh 123408h 123400h output data area low-order 8 bits of cr10 address type c, mpt/mpd incremented, 1-byte timer data, no automatic addition, no ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address intc10 match real-time output trigger/ macro service start ? +1 123411h 123409h output timing data area t9 ... t2 t1 d9 d2 d1 ... msc 00h 04h 14h mpt 12h 34h dsfrp 09h 0eh 12h mpd channel pointer 34h 00h 5eh tsfrp mode register 0fh stepping motor internal bus compare register cr10 buffer register p0l p00 p01 p02 p03 +1 p0 remark internal ram addresses in the figure are the values when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 585 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-32. data transfer control timing tm1 count value 0h compare register (cr10) t1 buffer register p0l intc10 timer interrupt p00 p02 p03 p01 t1 t7 t8 t9 d1 d2 d3 d4 d5 d6 d7 d9 t2 t3 t4 t5 t6 t8 t7 t3 t2 t4 t5 t6 d8 586 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (b) examples of use of automatic addition control and ring control (i) automatic addition control the output timing data ( d t) specified by the macro service pointer (mpt) is added to the contents of the compare register, and the result is written back to the compare register. use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time. (ii) ring control with ring control, the predetermined output patterns is prepared for one cycle only, and the one-cycle data patterns are output repeatedly in order in ring form. when ring control is used, only the output patterns for one cycle need be prepared, allowing the size of the data rom area to be reduced. the macro service counter (msc) is decremented each time a data transfer is performed. with ring control, too, an interrupt request is generated when msc = 0. when controlling a stepping motor, for example, the output patterns will vary depending on the configuration of the stepping motor concerned, and the phase excitation method (single-phase excitation, two-phase excitation, etc.), but repeat patterns are used in all cases. examples of single-phase excitation and 1-2-phase excitation of a 4-phase stepping motor are shown in figures 23-33 and 23-34. 587 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-33. single-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (4 patterns) 1 2 3 4 1 2 3 figure 23-34. 1-2-phase excitation of 4-phase stepping motor phase a phase b phase c phase d 1 cycle (8 patterns) 1 2 3 4 5 6 7 8 1 2 3 4 8 5 588 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-35. automatic addition control + ring control block diagram 1 (when output timing varies with 1-2-phase excitation) . . . d1 1 m memory space macro service control word, macro service channel (internal ram) compare register cr10w timer counter 1 tm1w addition buffer register p0l output latch p0 p00 p02 p01 p03 0fe5ah 1237feh 123007h output timing: 123400h 123000h output data (8 items) d7 d0 msc 02h 00h 14h mpt 12h 34h dsfrp 00h 0eh 12h mpd 30h mr 00h rc 08h 08h channel pointer 5ah tsfrp mode register 7fh low-order 8 bits of cr10 address type c, mpt/mpd incremented, 2-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address to stepping motor intc10 match t512 ? +2 +1 ? t2 t1 . . . ? ? ? remark internal ram addresses in the figure are the values when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 589 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-36. automatic addition control + ring control timing diagram 1 (when output timing varies with 1-2-phase excitation) tm1w count value 0h ffffh compare register (cr10w) t0 buffer register p0l intc10 d t1 p00 p02 p03 p01 t2 t1+ d t2 t3 t2+ d t3 t7 t6+ d t7 t9 t8+ d t9 t4 t3+ d t4 t6 t5+ d t6 t5 t4+ d t5 t1 t0+ d t1 d t3 d t4 d t5 d t6 d t9 t0 d t7 d t8 d1 d2 d3 d4 d5 d6 d7 d0 d0 d7 count start d t2 t8 t7+ d t8 590 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-37. automatic addition control + ring control block diagram 2 (1-2-phase excitation constant-velocity operation) remark internal ram addresses in the figure are the values when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values in the figure. 1 m memory space macro service control word, macro service channel (internal ram) compare register cr10 timer counter 1 tm1 addition buffer register p0l output latch p0 p00 p02 p01 p03 0fe7ah 123007h output timing: 1233ffh 123000h output data (8 items) d7 d6 d0 . . . msc ffh ffh 14h mpt 12h 33h dsfrp ffh 0eh 12h mpd 30h mr 07h rc 08h 08h channel pointer 7ah tsfrp mode register 3ch low-order 8 bits of cr10 address type c, mpt retained, mpd decremented, 1-byte timer data, automatic addition, ring control, interrupt request generation at msc = 0 low-order 8 bits of p0l address to stepping motor intc10 match t ? 591 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 figure 23-38. automatic addition control + ring control timing diagram 2 (1-2-phase excitation constant-velocity operation) tm1 count value 0h ffffh compare register (cr10) t0 buffer register p0l d6 d5 d4 d3 d2 d1 d0 d7 d6 d7 d0 intc10 d t p00 p02 p03 p01 count start t1 t0+ d t t2 t1+ d t t3 t2+ d t t4 t3+ d t t5 t4+ d t t6 t5+ d t t7 t6+ d t t8 t7+ d t t9 t8+ d t t10 t9+ d t 592 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.8.9 counter mode (1) operation msc is decremented the number of times set in advance to the macro service counter (msc). because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long. figure 23-39. macro service data transfer processing flow (counter mode) macro service request acknowledged reads contents of macro service mode register identifies channel type msc msc-1 others to other macro service processing msc is 16 bits wide counter mode msc = 0? no yes vcie = 1? no yes clears interrupt processing type bit (ism) to 0 clears interrupt request flag (if) to 0 end end (vectored interrupt request is generated) 593 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (2) configuration of macro service channel the macro service channel consists of only a 16-bit macro service counter. the low-order 8 bits of the address of the msc are written to the channel pointer. figure 23-40. counter mode (3) example of using counter mode here is an example of counting the number of edges input to external interrupt pin intp5. figure 23-41. counting number of edges (internal ram) intp5 macro service request msc 0eh high-order 8 bytes low-order 8 bytes channel pointer 7eh mode register 00h counter mode interrupt request is generated when msc = 0. internal bus ofe7eh ? intp5/p26 remark the internal ram address in the figure above is the value when the location 0 instruction is executed. when the location 0fh instruction is executed, add 0f0000h to this value. ? y ? t macro service channel macro service counter (msc) high-order 8 bytes low-order 8 bytes high-order addresses low-order addresses channel pointer mode register 70 594 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.9 when interrupt requests and macro service are temporarily held pending when the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. however, software interrupts are not deferred. ei di brk brkcs rbn reti retb retcs retcsb !addr16 pop psw location 0h or location 0fh popu post mov pswl, a mov pswl, #byte movg sp, #imm24 write instruction and bit manipulation instruction to an interrupt control register note , or the mk0, mk1, imc or ispr register (except bt and bf instructions) pswl bit manipulation instruction (excluding the bt pswl. bit, $addr16, bf pswl. bit, $addr16, set1 cy, not1 cy, and clr1 cy instructions) note interrupt control registers: pic0, pic1, pic2, pic3, pic4, pic5, cic00, cic01, cic10, cic11, cic20, cic21, cic30, adic, seric, sric, csiic1, stic, csiic, seric2, sric2, csiic2, stic2, ieic1, ieic2, wic, csiic3 595 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 cautions 1. when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop : bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. ? interrupts and macro service requests are not serviced until after execution of the instruction following the bf instruction. good example (1) loop : nop bf pic0.7, $loop ? interrupts and macro service requests are serviced after execution of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop : bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (to 0) automatically. br $loop ? interrupts and macro service requests are serviced after next : execution of the br instruction, so that interrupts are never held pending for a long period. 2. for a similar reason, if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. ?? ? ?? ? 596 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.10 instructions whose execution is temporarily suspended by an interrupt or macro service execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. the suspended instruction is resumed after completion of the interrupt service program or macro service processing. temporarily suspended instructions: movm, xchm, movbk, xchbk cmpme, cmpmne, cmpmc, cmpmnc cmpbke, cmpbkne, cmpbkc, cmpbknc sacw 23.11 interrupt and macro service operation timing interrupt requests are generated by hardware. the generated interrupt request sets (to 1) an interrupt request flag. when the interrupt request flag is set (to 1), a time of 8 clocks (0.64 m s: f clk = 12.58 mhz) is taken to determine the priority, etc. following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment processing is performed when the instruction being executed ends. if the instruction being executed is one which temporarily defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (see 23.9 when interrupt requests and macro service are temporarily held pending for deferred instructions). figure 23-42. interrupt request generation and acknowledgment (unit: clocks) interrupt request flag 8 clocks instruction interrupt request acknowledgment processing/macro service processing 597 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.11.1 interrupt acknowledge processing time the time shown in table 23-7 is required to acknowledge an interrupt request. after the time shown in this table has elapsed, execution of the interrupt processing program is started. table 23-7. interrupt acknowledge processing time (unit: clock = 1/f clk ) vector table irom emem branch irom, pram emem pram emem destination stack iram pram emem iram pram emem iram pram emem iram pram emem vectored 26 29 37 + 4n 27 30 38 + 4n 30 33 41 + 4n 31 34 42 + 4n interrupts context 22 C C 23 C C 22 C C 23 C C switching remarks 1. irom: internal rom (with high-speed fetch specified) pram: peripheral ram of internal ram (only when location 0 instruction is executed in the case of branch destination) iram: internal high-speed ram emem: internal rom when external memory and high-speed fetch are not specified 2. n is the number of wait states per byte necessary for writing data to the stack (the number of wait states is the sum of the number of address wait states and the number of access wait states). 3. it the vector table is emem, and if wait states are inserted in reading the vector table, add 2 m to the value of the vectored interrupt in the above table, and add m to the value of context switching, where m is the number of wait states per byte necessary for reading the vector table. 4. it the branch destination is emem and if wait states are inserted in reading the instruction at the branch destination, add that number of wait states. 5. if the stack is occupied by pram and if the value of the stack pointer (sp) is odd, add 4 to the value in the above table. 6. the number of wait states is the sum of the number of address wait states and the number of access wait states. 598 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.11.2 processing time of macro service macro service processing time differs depending on the type of the macro service, as shown in table 23-8. table 23-8. macro service processing time (units: clock = 1/f clk ) processing type of macro service data area iram others type a sfr ? memory 1 byte 24 C 2 bytes 25 C memory ? sfr 1 byte 24 C 2 bytes 26 C type b sfr ? memory 33 35 memory ? sfr 34 36 type c 49 53 counter mode msc 1 017C msc = 0 25 C remarks 1. iram: internal high-speed ram 2. in the following cases in the other data areas, add the number of clocks specified below. ? if the data size is 2 bytes with irom or iram, and the data is located at an odd address: 4 clocks ? if the data size is 1 byte with emem: number of wait states for data access ? if the data size is 2 bytes with emem: 4 + 2n (where n is the number of wait states per byte) 3. if msc = 0 with type a, b, or c, add 1 clock. 4. with type c, add the following value depending on the function to be used and the status at that time. ? ring control: 4 clocks. adds 7 more clocks if the ring counter is 0 during ring control. 599 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.12 restoring interrupt function to initial state if an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, nmi pin input, etc., the entire system must be restored to its initial state. in the m pd784938, interrupt acknowledgment related priority control is performed by hardware. this interrupt acknowledgment related hardware must also be restored to its initial state, otherwise subsequent interrupt acknowledgment control may not be performed normally. a method of initializing interrupt acknowledgment related hardware in the program is shown below. the only way of performing initialization by hardware is by reset input. example movw mk0, #0ffffh; mask all maskable interrupts mov mk1l, #0ffh iresl: cmp ispr, #0; no interrupt service programs running? bz $next movg sp, #retval; forcibly change sp location reti; forcibly terminate running interrupt service program, return address = iresl retval: dw loww (iresl); stack data to return to iresl with reti instruction db 0 db highw (iresl); loww & highw are assembler operators for calculating low-order 16 bits & high-order 16 bits respectively of symbol next next: ? it is necessary to ensure that a non-maskable interrupt request is not generated via the nmi pin during execution of this program. ? after this, on-chip peripheral hardware initialization and interrupt control register initialization are performed. ? when interrupt control register initialization is performed, the interrupt request flags must be cleared (to 0). 600 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 23.13 cautions (1) the in-service priority register (ispr) is read-only. writing to this register may result in misoperation. (2) the watchdog timer mode register (wdm) can only be written to with a dedicated instruction (mov wdm/#byte). (3) the reti instruction must not be used to return from a software interrupt caused by a brk instruction. (4) the retcs instruction must not be used to return from a software interrupt caused by a brkcs instruction. (5) when a maskable interrupt is acknowledged by vectored interruption, the reti instruction must be used to return from the interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (6) the retcs instruction must be used to return from a context switching interrupt. subsequent interrupt related operations will not be performed normally if a different instruction is used. (7) macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. if you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation. (8) the reti instruction must be used to return from a non-maskable interrupt. subsequent interrupt acknowledgment will not be performed normally if a different instruction is used. (9) non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execution (except when a high non-maskable interrupt request is generated during execution of a low-priority non-maskable interrupt service program) and for a certain period after execution of the special instructions shown in 23.9 . therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (sp) value is undefined, in particular after reset release, etc. in this case, depending on the value of the sp, it may happen that the program counter (pc) and program status word (psw) are written to the address of a write-inhibited special function register (sfr) (see table 3-6 in 3.9 special function registers (sfr) ), and the cpu becomes deadlocked, or the pc and psw are written to an unexpected signal is output from a pin, or an address is which ram is not mounted, with the result that the return from the non-maskable interrupt service program is not performed normally and a software upsets occurs. therefore, the program following reset release must be as follows. cseg at 0 dw strt cseg base strt: location 0fh; or location 0 movg sp, #imm24 601 chapter 23 interrupt functions preliminary users manual u13987ej1v0um00 (10) when an interrupt related register is polled using a bf instruction, etc., the branch destination of that br instruction, etc., should not be that instruction. if a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises. bad example loop: bf pic0.7, $loop all interrupts and macro service requests are held pending until pic0.7 is 1. ? interrupts and macro service requests are not serviced until after execution of the instruction following the bf instruction. good example (1) loop: nop bf pic0.7, $loop ? interrupts and macro service requests are serviced after execution of the nop instruction, so that interrupts are never held pending for a long period. good example (2) loop: bt pic0.7, $next using a btclr instruction instead of a bt instruction has the advantage that the flag is cleared (to 0) automatically. br $loop ? interrupts and macro service requests are serviced after execution of the next: br instruction, so that interrupts are never held pending for a long period. (11) for a similar reason to that given in (10), if problems are caused by a long pending period for interrupts and macro service when instructions to which the above applies are used in succession, a time at which interrupts and macro service requests can be acknowledged should be provided by inserting an nop instruction, etc., in the series of instructions. ? ? ?? ? ? 602 preliminary users manual u13987ej1v0um00 [memo] 603 preliminary users manual u13987ej1v0um00 chapter 24 local bus interface function the local bus interface function is provided for the connection of external memory (rom and ram) and i/os. external memory (rom and ram) and i/os are accessed using the rd, wr, and astb pin signals, with pins ad0 to ad7 used as the multiplexed address/data bus and pins a8 to a19 as the address bus. the basic bus interface timing is shown in figures 24-6 and 24-7. also provided are a wait function for interfacing with low-speed memory, a refresh signal output function for refreshing pseudo-static ram, and a bus hold function for connecting devices that have a bus master function, such as a dma controller. 24.1 memory expansion function with the m pd784938, external memory and i/o expansion can be performed by setting the memory expansion mode register (mm). 24.1.1 memory expansion mode register (mm) mm is an 8-bit register that performs external expansion memory control, address wait number specification, and internal fetch cycle control. mm can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the mm format is shown in figure 24-1. reset input sets mm to 20h. 604 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-1. memory expansion mode register (mm) format 7 ifch mm 6 0 mm3 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 astb /clk out 5 aw 4 0 3 mm3 2 mm2 1 mm1 0 mm0 address after reset r/w r/w 20h 0ffc4h mm2 mm1 mm0 mode port 4 port 5 single-chip mode 256-byte expansion mode 1-kbyte expansion mode 4-kbyte expansion mode 16-kbyte expansion mode 64-kbyte expansion mode 256-kbyte expansion mode 1-mbyte expansion mode setting prohibited port port port port port port rd wr port port port port port port a8, a9 port a8 to a11 a8 to a13 a8 to a15 a8 to a15 a8 to a15 a16 to a19 p60 to p63 p64/ rd p65/ wr ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 ad0 to ad7 port a16, a17 port rd wr rd wr astb rd wr rd wr rd wr rd wr other than the above aw address wait specification disabled enabled 1 0 ifch internal rom fetches fetch performed at same speed as external memory all wait control settings valid high-speed fetches performed wait control specification invalid 1 0 605 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.1.2 memory map with external memory expansion the memory map when memory expansion is used is shown in figures 24-2 and 24-3. external devices at the same addresses as the internal rom area, internal ram area and sfr area (excluding the external sfr area (0ffd0h to 0ffdfh)) cannot be accessed. if an access is made to these addresses, the memory or sfr in the m pd784938 has access priority and no astb signal, rd signal, or wr signal is output (these pins remain at the inactive level). the address bus output level remains at the level output prior to this, and the address/data bus output becomes high-impedance. except in 1-mbyte expansion mode, the address output externally is output with the upper part of the address specified by the program masked. example 1: in 256-byte expansion mode, when address 54321h is accessed by the program, the output address is 21h. example 2: in 256-byte expansion mode, when address 67821h is accessed by the program, the output address is 21h. 606 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-2. m pd784935 memory map (1/2) (a) when location 0 instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion modes internal rom internal rom external memory external memory note 1 external memory note 2 fffffh 0ffffh 10000h 17fffh 0ffe0h 0ffcfh 0eb00h 00000h 607 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-2. m pd784935 memory map (2/2) (b) when location 0fh instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom external memory note 2 fffffh fffe0h fffcfh feb00h 17fffh 00000h external memory external memory note 1 608 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-3. m pd784936 memory map (1/2) (a) when location 0 instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion modes internal rom internal rom external memory external memory note 1 external memory note 2 fffffh 0ffffh 10000h 1ffffh 0ffe0h 0ffcfh 0e500h 00000h 609 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-3. m pd784936 memory map (2/2) (b) when location 0fh instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom external memory note 2 fffffh fffe0h fffcfh fe500h 1ffffh 00000h external memory external memory note 1 610 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-4. m pd784937 memory map (1/2) (a) when location 0 instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion modes internal rom internal rom external memory external memory note 1 external memory note 2 fffffh 0ffffh 10000h 2ffffh 0ffe0h 0ffcfh 0df00h 00000h 611 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-4. m pd784937 memory map (2/2) (b) when location 0fh instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom external memory note 2 fffffh fffe0h fffcfh fdf00h 1ffffh 00000h external memory external memory note 1 612 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-5. m pd784938 memory map (1/2) (a) when location 0 instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal rom internal rom internal rom internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion modes internal rom internal rom external memory external memory note 1 external memory note 2 fffffh 0ffffh 10000h 3ffffh 0ffe0h 0ffcfh 0d600h 00000h 613 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-5. m pd784938 memory map (2/2) (b) when location 0fh instruction is executed notes 1. any expansion size area in unshaded part 2. external sfr area sfr sfr sfr sfr sfr note 2 sfr internal ram internal ram internal ram internal rom single-chip mode 1-mbyte expansion mode 256-byte to 256-kbyte expansion mode internal rom internal rom external memory note 2 fffffh fffe0h fffcfh fd600h 1ffffh 00000h external memory external memory note 1 614 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.1.3 basic operation of local bus interface the local bus interface accesses external memory using astb, rd, wr, an address/data bus (ad0 to ad7), and address bus (a8 to a19). when the local bus interface is used, p64, p65, and port 4 automatically operate as rd, wr and ad0 to ad7. on the address bus, only the pins that correspond to the expansion memory size operate as address bus pins. an outline of the memory access timing is shown in figures 24-6 and 24-7. figure 24-6. read timing high address data (input) astb (output) rd (output) ad0 to ad7 a8 to a19 note (output) hi-z hi-z hi-z low address (output) note the number of address bus pins used depends on the expansion mode size. figure 24-7. write timing high address astb (output) ad0 to ad7 (output) a8 to a19 note (output) hi-z hi-z hi-z wr (output) data low address note the number of address bus pins used depends on the expansion mode size. 615 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.2 wait function when a low-speed memory or i/o is connected externally to the m pd784938, waits can be inserted in the external memory access cycle. there are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing the access time. 24.2.1 wait function control registers (1) memory expansion mode register (mm) the ifch bit of mm performs wait control setting for internal rom accesses, and the aw bit performs address wait setting. mm can be read or written to with an 8-bit manipulation instruction. the mm format is shown in figure 24-8. when reset is input, mm is set to 20h, the same cycle as for external memory is used for internal rom accesses, and the address wait function is validated. figure 24-8. memory expansion mode register (mm) format (2) programmable wait control registers (pwc1/pwc2) pwc1 and pwc2 specify the number of waits. pwc1 is an 8-bit register that divides the space from 0 to ffffh into four, and specifies wait control for each of these four spaces. pwc2 is a 16-bit register that divides the space from 10000h to ffffh into four, and specifies wait control for each of these four spaces. pwc1 can be read or written to with an 8-bit manipulation instruction, and pwc2 with a 16-bit manipulation instruction. the pwc1 and pwc2 formats are shown in figure 24-9. the high-order 8 bits of pwc2 are fixed at aah, and therefore ensure that the high-order 8 bits are set to aah. when reset is input, pwc1 is set to aah, and pwc2 to aaaah, and 2-wait insertion is performed on the entire space. 3210 address after reset r/w 0ffc4h r/w 20h ifch 0 aw 0 mm2 mm1 mm0 mm 7654 mm3 aw 0 1 address wait specification disabled enabled ifch 0 1 internal rom fetches fetch performed at same speed as external memory all wait control settings valid high-speed fetches performed wait control specification invalid memory expansion mode settings (see 24.1 memory extension function ) 616 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-9. programmable wait control register (pwc1/pwc2) format (a) programmable wait control register 1 (pwc1) 7 pw31 pwc1 6 pw30 5 pw21 4 pw20 3 pw11 2 pw10 1 pw01 0 pw00 address after reset r/w r/w aah 0ffc7h 000000h to 003fffh pw01 address subject to wait pw00 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 004000h to 007fffh pw11 address subject to wait pw10 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 008000h to 00bfffh pw21 address subject to wait pw20 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 00c000h to 00ffffh note pw31 address subject to wait pw30 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 note except part overlapping internal data area 617 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 (b) programmable wait control register 2 (pwc2) 7 pw71 6 pw70 5 pw61 4 pw60 3 pw51 2 pw50 1 pw41 0 pw40 address after reset r/w r/w aaaah 0ffc8h 15 1 pwc2 14 0 13 1 12 0 11 1 10 0 9 1 8 0 010000h to 01ffffh pw41 address subject to wait pw40 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 020000h to 03ffffh pw51 address subject to wait pw50 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 040000h to 07ffffh pw61 address subject to wait pw60 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 080000h to 0fffffh note pw71 address subject to wait pw70 0 0 1 1 0 1 0 1 wait cycle insertion access wait cycle inserted only for wait pin low-level input period 0 1 2 note except part overlapping internal data area caution when the bus hold function is used, access wait control cannot be performed by means of the wait pin, and 0, 1, or 2 waits must be selected for the entire space. 618 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.2.2 address waits address waits are used to secure the address decoding time. if the aw bit of the memory expansion mode register (mm) is set (to 1), waits are inserted in every memory access note . when an address wait is inserted, the high-level period of the astb signal is extended by one system clock cycle (80 ns: f clk = 12.58 mhz). note except for the internal ram, internal sfrs, and internal rom during high-speed fetch. if it is specified that the internal rom is accessed in the same cycle as the external rom, an address wait state is inserted even when the internal rom is accessed. caution if the pseudo-static ram refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. therefore, do not use the pseudo-static ram refresh function when using the address wait function. figure 24-10. address wait function read/write timing (1/3) (a) read timing with no address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z rd input data low address hi-z note f clk : internal system clock frequency. this signal is present inside the m pd784938 only. 619 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-10. address wait function read/write timing (2/3) (b) read timing with address wait insertion f clk note astb ad0 to ad7 a8 to a19 hi-z hi-z rd hi-z low address input data high address note f clk : internal system clock frequency. this signal is present inside the m pd784938 only. 620 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-10. address wait function read/write timing (3/3) (c) write timing with no address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z (d) write timing with address wait insertion f clk note high address astb ad0 to ad7 a8 to a19 hi-z hi-z wr output data low address hi-z note f clk : internal system clock frequency. this signal is present inside the m pd784938 only. 621 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.2.3 access waits access waits are inserted in the rd or wr signal low-level period, and extend the low-level period by 1/f clk (80 ns: f clk = 12.58 mhz) per cycle. there are two wait insertion methods, using either the programmable wait function that automatically inserts the preset number of cycles, or the external wait function controlled by a wait signal from outside. for wait cycle insertion control, the 1-mbyte memory space is divided into eight as shown in figure 24-11, and control is specified for each space by means of the programmable wait control registers (pwc1/pwc2). waits are not inserted in accesses to internal rom or internal ram using high-speed fetches. in accesses to internal sfrs, waits are inserted at the necessary times regardless of this specification. if access operations are specified as being performed in the same number of cycles as for external rom, waits are inserted also in internal rom accesses in accordance with the pwc1 settings. if there is a space for which control by a wait signal from outside has been selected by means of the pwc1/pwc2, the p66 pin operates as the wait signal input pin. after reset input, the p66 pin operates as a general-purpose input/output port. bus timing in the case of access wait insertion is shown in figures 24-12 to 24-14. caution the external wait function cannot be used when the bus hold function is used. 622 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-11. wait control spaces 512 kbytes 256 kbytes 128 kbytes 64 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes fffffh 80000h 03fffh 7ffffh controlled by bits pw70 & pw71 controlled by bits pw60 & pw61 controlled by pwc2 controlled by pwc1 controlled by bits pw50 & pw51 controlled by bits pw40 & pw41 controlled by bits pw30 & pw31 controlled by bits pw20 & pw21 controlled by bits pw10 & pw11 controlled by bits pw00 & pw01 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 40000h 3ffffh 04000h 00000h 623 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-12. access wait function read timing (1/2) (a) 0 wait cycles set f clk note high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z hi-z rd (output) data (input) low address hi-z (b) 1 wait cycle set f clk note high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z hi-z rd (output) data (input) low address hi-z note f clk : internal system clock frequency. this signal is only present inside the m pd784938. 624 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-12. access wait function read timing (2/2) (c) 2 wait cycles set high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z rd (output) data (input) low address hi-z f clk note note f clk : internal system clock frequency. this signal is only present inside the m pd784938. 625 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-13. access wait function write timing (1/2) (a) 0 wait cycles set f clk note high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z hi-z wr (output) data low address hi-z (b) 1 wait cycle set f clk note high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z hi-z wr (output) data low address hi-z note f clk : internal system clock frequency. this signal is only present inside the m pd784938. 626 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-13. access wait function write timing (2/2) (c) 2 wait cycles set high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z wr (output) data low address hi-z f clk note hi-z note f clk : internal system clock frequency. this signal is only present inside the m pd784938. 627 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 figure 24-14. timing with external wait signal (a) read timing high address astb (output) ad0 to ad7 a8 to a15 (output) hi-z rd (output) data (input) low address hi-z f clk note wait (input) (b) write timing high address astb (output) ad0 to ad7 (output) a8 to a15 (output) hi-z wr (output) data low address hi-z f clk note wait (input) note f clk : internal system clock frequency. this signal is only present inside the m pd784938. 628 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.3 pseudo-static ram refresh function the m pd784938 incorporates a pseudo-static ram refresh function for direct connection of pseudo-static ram. the pseudo-static ram refresh function outputs refresh pulses at any desired intervals. the refresh pulse output interval is specified by the refresh mode register (rfm) setting. the refresh area specification register (rfa) specifies the addresses on which refresh operations can be performed at the same time as memory access operations. this enables bus cycle insertions for refresh operations to be greatly decreased, thus minimizing the reduction in performance due to refresh operations. the m pd784938 is provided with a function for supporting self-refresh operations that offers low power consumption by a pseudo-static ram application system. cautions 1. the refresh function cannot be used when the bus hold function is used. 2. if the pseudo-static ram refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. therefore, do not use the pseudo-static ram refresh function when using the address wait function. 629 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.3.1 control registers (1) refresh mode register (rfm) rfm is an 8-bit register that controls the pseudo-static ram refresh cycle and switching to self-refresh operations. rfm can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. the rfm format is shown in figure 24-15. reset input clears rfm to 00h and sets the refrq pin to port mode, so that it operates as the alternate-function p67 pin. figure 24-15. refresh mode register (rfm) format rflv 0 0 rfen 0 0 rft1 rft0 76543210 rfm 0ffcch address 00h after reset r/w r/w rft1 0 0 1 1 refresh pulse output cycle specification 32/f clk note (2.5 s) 64/f clk (5.1 s) 128/f clk (10.2 s) 256/f clk (20.3 s) rft0 0 1 0 1 f clk = 12.58 mhz rflv 0 1 refrq pin output control port mode self-refresh operation (refrq low level) refresh pulse output enabled rfen 0 1 remark : 0 or 1 note f clk : internal system clock frequency m m m m caution the refresh function cannot be used when the bus hold function is used. in this case, ensure that refreshing is specified as disabled. 630 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 (2) refresh area specification register (rfa) rfa is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time as memory access operations. rfa can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. the rfa format is shown in figure 24-16. reset input clears rfa to 00h. figure 24-16. refresh area specification register (rfa) format rfa7 rfa rfa6 rfa5 rfa4 rfa3 rfa2 rfa1 rfa0 address after reset r/w r/w 00h 0ffcdh refresh specification area 0 1 7654 32 10 080000h to 0fffffh 040000h to 07ffffh 020000h to 03ffffh 010000h to 01ffffh 00c000h to 00ffffh 008000h to 00bfffh 004000h to 007fffh 000000h to 003fffh refreshing performed at same time as memory access operations in corresponding block refreshing performed exclusively from memory access operations in corresponding block (n = 0 to 7) rfan 24.3.2 operations (1) pulse refresh operation to support the pulse refresh cycles of pseudo-static ram, refresh pulses are output from the refrq pin in synchronization with bus cycles. the system clock frequency and bits 1 and 0 (rft1/rft0) of the refresh mode register (rfm) are adjusted so that 512 or more refresh pulses are generated in an 8 ms period. table 24-1. system clock frequency and refresh pulse output cycle when pseudo-static ram is used system clock frequency refresh pulse output cycle specification rft1 rft0 (f clk ) mhz 8.192 < f clk 16 128/f clk 10 4.096 < f clk 8.192 64/f clk 01 2.048 < f clk 4.096 32/f clk 00 these pulse refresh operations are performed so that they do not overlap external memory access operations. during a refresh cycle, an external memory access cycle is held pending (astb, rd, wr, etc. are inactive), and during an external memory access cycle, a refresh cycle is held pending. if there is no overlapping with an external memory access operation, the refresh cycle is performed without affecting cpu instruction execution. 631 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 (a) internal memory accesses in the case of internal memory accesses in which the external pseudo-static ram is not accessed, also, refresh bus cycles are output at the intervals specified by the refresh mode register (rfm) so that the data stored in the pseudo-static ram is retained. in this case, cpu instruction execution is not affected. figure 24-17. pulse refresh operation in internal memory access refrq pin output refresh cycle note refresh timing counter note cycle specified by the rft1 and rft0 bits of the rfm 632 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 (b) external memory accesses when an access is made to an address corresponding to a cleared (to 0) bit in the refresh area specification register (rfa), a refresh pulse is always output from the refrq pin at the same time as the rd signal or wr signal, irrespective of the cycle specified by the refresh mode register (rfm). after refresh pulse output, accesses to internal memory or accesses to addresses corresponding to a set (to 1) bit in the rfa continue, and after the time specified by the rft0 and rft1 bits of the rfm has elapsed, a refresh bus cycle is generated so as not to overlap a memory access cycle, and a refresh pulse is output. in this way, refreshing can be performed while memory that does not need refreshing, such as prom, is being accessed, refresh bus cycle insertions can be reduced, and instruction execution can be performed efficiently. figure 24-18. refresh pulse output operation astb read cycle write cycle read cycle read cycle refresh bus cycle write cycle time specified by rft0 & rft1 bits of rfm in case of access to area in which memory access operations and refresh operations are performed simultaneously time specified by rft0 & rft1 bits of rem. as refresh pulse has not been output, refresh bus cycle is inserted in case of access to area in which memory access operations and refresh operations are performed exclusively refrq rd wr 633 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 (2) self-refresh operation this mode is used to retain the contents of pseudo-static ram in standby mode. (a) self-refresh operation mode setting when bit 4 (rfen) of the refresh mode (rfm) register is set to 1, and bit 7 (rflv) to 0, a low level is output from the refrq pin, and the self-refresh operation mode is specified for the pseudo-static ram. (b) return from self-refresh operation refresh pulse output to the pseudo-static ram is disabled approximately 200 ns note after the refrq pin output level changes from low to high. therefore, the m pd784938 arranges for refresh pulses not to be output during the disabled time by raising the refrq pin in synchronization with the refresh timing counter. to enable this low-to-high transition of the refrq pin level to be recognized, the rflv bit read level is set (to 1) when the refrq pin level changes from low to high. note this time varies according to the speed rank, etc. of the pseudo-static ram. figure 24-19. timing for return from self-refresh operation approximately min. 200 ns note refrq rflv bit software set operation execution self refresh mode refresh timing counter output note refreshing disabled time 634 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.4 bus hold function the bus hold function is provided for the connection of a device that functions as the bus master, such as a dma controller. in response to a request from the bus master device, all local bus interface pins are set to high impedance (except hldak), and local bus interface mastership is passed to that device. the bus hold function cannot be used when the external wait function or refresh function is used. 24.4.1 hold mode register (hldm) hldm is an 8-bit register that specifies enabling/disabling of the bus hold function. hldm format is shown in figure 24-20. when reset is input, hldm is cleared to 00h, so that the bus hold function is disabled. the hldrq and hldak pins are set to port mode and operate as the p66 and p67 pins. figure 24-20. hold mode register (hldm) format 7 hlde hldm 6 0 5 0 4 0 3 0 2 0 1 0 0 0 disabled port enabled hlde p66 p67 hldrq hldak 1 0 address after reset r/w r/w 00h 0ffc5h bus hold enabling/disabling caution the bus hold function must be disabled when the external wait function or refresh function is used. 635 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.4.2 operation when the hlde bit of the hold mode register (hldm) is set (to 1), the bus hold function is enabled. when the bus hold function is enabled, pins p66 and p67 operate as the hldrq and hldak pins respectively. the hldrq pin becomes high-impedance, and the hldak pin outputs a low-level signal. if a high-level signal is input to the hldrq pin when the bus hold function is enabled, at the end of the access operation being executed the address bus (a8 to a19), address/data bus (ad0 to ad7), rd, wr, and astb pins are all set to high- impedance, the hldak pin output level is driven high, and the hold mode is established. while the hldak pin is high (in the hold mode) the m pd784938 does not use the local bus interface, and therefore an external dma controller, etc. is free to access the memory. when the hldrq pin input level changes from high to low, the hold mode is released, the hldak pin level changes from high to low, and then the m pd784938 resumes use of the local bus. a transition to the hold mode is performed between bus cycles, and the instruction being executed may be suspended. also, if a transition to the hold mode is made during execution of an instruction that does not use the local bus interface when a program is fetched from the external memory, the m pd784938 continues execution of prefetched instructions until it comes to an instruction that uses the local bus interface, and suspends instruction execution when there are no more prefetched instructions. when the hold mode is released, execution of the suspended instruction is resumed from the point at which it was suspended. when a program is fetched from the internal rom or ram, execution of instructions until it comes to an instruction that uses the local bus interface continues. figure 24-21. hold mode timing hi-z hi-z hi-z hi-z hi-z hi-z a8 to a19 astb ad0 to ad7 rd hldrq hldak wr 636 chapter 24 local bus interface function preliminary users manual u13987ej1v0um00 24.5 cautions (1) when the bus hold function is used, the external wait function cannot be used (access wait control by means of the wait pin), and 0, 1, or 2 waits must be selected for the entire space. (2) the refresh function cannot be used when the bus hold function is used. in this case, ensure that refreshing is specified as disabled. (3) do not set external wait to the internal rom area. otherwise, the cpu may be in the deadlock status which can be cleared only by reset input. (4) if the pseudo-static ram refresh function is used when the address wait function is used, the refresh pulse is output and, at the same time, the memory is accessed. therefore, do not use the pseudo-static ram refresh function when using the address wait function. conversely do not use the address wait function when the pseudo-static ram refresh function is used. 637 preliminary users manual u13987ej1v0um00 chapter 25 standby function 25.1 configuration and function the m pd784938 has a standby function that enables the system power consumption to be reduced. the standby function includes three modes as follows: ? halt mode........ in this mode the cpu operating clock is stopped. intermittent operation in combination with the normal operation mode enables the total system power consumption to be reduced. ? idle mode......... in this mode the oscillator continues operating while the entire remainder of the system is stopped. normal program operation can be restored at a low power consumption close to that of the stop mode and in a time equal to that of the halt mode. ? stop mode........in this mode the oscillator is stopped and the entire system is stopped. ultra-low power consumption can be achieved, consisting of leakage current only. these modes are set by software. the standby mode (stop/idle/halt mode) transition diagram is shown in figure 25-1, and the standby function block diagram in figure 25-2. figure 25-1. standby mode transition diagram wait of oscillation stabilization program operation macro service macro service request end of 1st service end of macro service macro service request end of 1st service stop setting reset input intw notes 1, 3 , nmi, intp4, intp5 input note 1 idle setting reset input intw notes 1, 3 , nmi, intp4, intp5 input note 1 interrupt request note 2 reset input halt setting masked interrupt request halt (standby) idle (standby) stop (standby) end of oscillation stabilization time notes 1. when intw, intp4, and intp5 are not masked 2. unmasked interrupt request only 3. at subclock operation remark only external input is valid as nmi. the watchdog timer must not be used to release the standby mode (stop, idle, or halt mode) 638 chapter 25 standby function preliminary users manual u13987ej1v0um00 figure 25-2. standby function block diagram extc system cock oscillator fxx fxx/2 fxx/4 fxx/8 frequency divider oscillation stabilization timer (19) osts0 osts1 osts2 extc nmi intp4, intp5 reset rising edge detection rising edge detection falling edge detection falling edge detection selector selector selector esnmi es40, es50 es41, es51 interrupt intc mk ism macro service request selector to peripheral circuit ram protect to peripheral circuit cpu clk hlt f/f idle f/f stp f/f2 stp f/f1 macro service request halt bit setting stop bit setting q s r q q s r q q s r q q s r q valid edge fxx mk ism intw wm3 to watch timer after division by 128 wm6 639 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.2 control registers 25.2.1 standby control register (stbc) stbc is used to select the stop mode setting and the internal system clock. to prevent entry into standby mode due to an inadvertent program loop, stbc can only be written to with a dedicated instruction. this dedicated instruction, mov stbc, #byte, has a special code configuration (4 bytes), and a write is only performed if the 3rd and 4th bytes of the operation code are mutual complements of 1. if the 3rd and 4th bytes of the operation code are not mutual complements of 1, a write is not performed and an operand error interrupt is generated. in this case, the return address saved in the stack area is the address of the instruction that was the source of the error, and thus the address that was the source of the error can be identified from the return address saved in the stack area. if recovery from an operand error is simply performed by means of an retb instruction, an endless loop will result. as an operand error interrupt is only generated in the event of an inadvertent program loop (with the nec assembler, ra78k4, only the correct dedicated instruction is generated when mov stbc, #byte is written), system initialization should be performed by the program. other write instructions (mov stbc, a, and stbc, #byte, set1 stbc.7, etc.) are ignored and do not perform any operation. that is, a write is not performed to stbc, and an interrupt such as an operand error interrupt is not generated. stbc can be read at any time by a data transfer instruction. reset input sets stbc to 30h. the format of stbc is shown in figure 25-3. caution be sure to use a program that executes a nop instruction three times to set the standby mode. example mov stbc, #byte; sets standby mode nop nop nop . . . . . . 640 chapter 25 standby function preliminary users manual u13987ej1v0um00 figure 25-3. standby control register (stbc) format selosc 0 ck1 ck0 0 stp hlt 76543210 stbc 0ffc0h address 30h after reset r/w r/w stp 0 0 1 1 operation mode normal operation mode halt mode stop mode idle mode hlt 0 1 0 1 ck1 0 0 1 1 internal system clock selection f xx (12.58 mhz) f xx /2 (6.29 mhz) f xx /4 (3.15 mhz) f xx /8 (1.57 mhz) ck0 0 1 0 1 (f xx = 12.58 mhz) selosc 0 1 oscillation frequency control 6.29 mhz 12.58 mhz cautions 1. the selosc bit must be overwritten after performing the next setting. stop the iebus (set bit 7 (eniebus) of the bus control register (bcr) to ??) if the watch timer is operated with the main clock selected, stop the watch timer (set bit 3 (wm3) of the watch timer mode register (wm) to ??) 2. if the above settings are not performed, the iebus and watch timer may perform incorrectly. 641 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.2.2 oscillation stabilization time specification register (osts) osts specifies the oscillator operation and the oscillation stabilization time when stop mode is released. the extc bit of osts specifies whether crystal/ceramic oscillation or an external clock is used. stop mode can be set when external clock input is used only when the extc bit is set (to 1). bits osts0 to osts2 of osts select the oscillation stabilization time when stop mode is released. in general, an oscillation stabilization time of at least 40 ms should be selected when a crystal resonator is used, and at least 4 ms when a ceramic oscillator is used. the time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the capacitance of the connected capacitor. therefore, if you want to set a short oscillation stabilization time, you should consu lt the crystal resonator or ceramic resonator manufacturer. osts can be written to only with an 8-bit transfer instruction. reset input clears osts to 00h. the format of osts is shown in figure 25-4. figure 25-4. oscillation stabilization time specification register (osts) format 00000 osts2 osts1 osts0 76543210 osts 0ffcfh address 00h after reset r/w r/w 2 19 /f xx (41.7 ms) 2 18 /f xx (20.8 ms) 2 17 /f xx (10.4 ms) 2 16 /f xx (5.2 ms) 2 15 /f xx (2.6 ms) 2 14 /f xx (1.3 ms) 2 13 /f xx (0.7 ms) setting prohibited osts2 0 0 0 0 1 1 1 1 osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 oscillation stabilization time selection bits (f xx = 12.58 mhz) caution when using the regulator (refer to chapter 5 regulator), set a value of at least 10.4 ms, taking in consideration the regulator output stabilization time. 642 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.3 halt mode 25.3.1 halt mode setting and operating status the halt mode is selected by setting (to 1) the hlt bit of the standby control (stbc) register. the only writes that can be performed on stbc are 8-bit data writes by means of a dedicated instruction. halt mode setting is therefore performed by means of the mov stbc, #byte instruction. caution if halt mode setting is performed when a condition that releases halt mode is in effect, halt mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. to ensure that a definite halt mode setting is made, interrupt requests should be cleared (to 0), etc. before entering halt mode. table 25-1. operating status in halt mode clock oscillator operating internal system clock operating cpu operation stopped note i/o lines retain status prior to halt mode setting peripheral functions continue operating internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 retained rd, wr output high level astb output low level refrq output continue operating hldrq input continue operating (input) hldak output continue operating note macro service processing is executed. 25.3.2 halt mode release halt mode can be released by the following three sources. ? non-maskable interrupt request ? maskable interrupt request (vectored interrupt/context switching/macro service) ? reset input release sources and an outline of operations after release are shown in table 25-2. 643 chapter 25 standby function preliminary users manual u13987ej1v0um00 table 25-2. halt mode release and operations after release release source mk note 1 ie note 2 state on release operation after release reset input normal reset operation non-maskable ? non-maskable interrupt service program interrupt request acknowledgment interrupt request not being executed (nmi pin input/ ? low-priority non-maskable interrupt watchdog timer) service program being executed ? service program for same request being execution of instruction after mov stbc, executed #byte instruction (interrupt request that ? high-priority non-maskable interrupt released halt mode is held pending note 3 ) service program being executed maskable 0 1 ? interrupt service program not being interrupt request acknowledgment interrupt request executed (excluding macro ? low-priority maskable interrupt service service request) program being executed ? prsl bit note 4 cleared (to 0) during execution of priority level 3 interrupt service program ? same-priority maskable interrupt service execution of instruction after mov stbc, program being executed #byte instruction (interrupt request that (if prsl bit note 4 is cleared (to 0), excluding released halt mode is held pending note 3 ) execution of priority level 3 interrupt service program) ? high-priority interrupt service program being executed 00 1 halt mode maintained macro service 0 macro service processing execution request end condition not established ? halt mode again end condition established ? if vcie note 5 = 1: halt mode again if vcie note 5 = 0: same as release by maskable interrupt request 1 halt mode maintained notes 1. interrupt mask bit in individual interrupt request source 2. interrupt enable flag in program status word (psw) 3. pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. bit in interrupt mode control register (imc) 5. bit in macro service mode register of macro service control word in individual macro service request source 644 chapter 25 standby function preliminary users manual u13987ej1v0um00 (1) release by non-maskable interrupt when a non-maskable interrupt is generate, the m pd784938 is released from halt mode irrespective of whether the interrupt acknowledgment enabled state (ei) or disabled state (di) is in effect. when the m pd784938 is released from halt mode, if the non-maskable interrupt that released halt mode can be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service program. if the interrupt cannot be acknowledged, the instruction following the instruction that set the halt mode (the mov stbc, #byte instruction) is executed, and the non-maskable interrupt that released the halt mode is acknowledged when acknowledgment becomes possible. see 23.6 non-maskable interrupt acknowledgment operation for details of non-maskable interrupt acknowledgment. (2) release by maskable interrupt request halt mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt mask flag is 0. when halt mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the halt mode. see 23.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. with macro service, halt mode is released temporarily, service is performed once, then halt mode is restored. when macro service has been performed the specified number of times, halt mode is released if the vcic bit in the macro service mode register of the macro service control word is cleared (to 0). the operation after release in this case is the same as for release by a maskable interrupt described earlier. if the vcie bit is set (to 1), the halt mode is entered again and is released by the next interrupt request. 645 chapter 25 standby function preliminary users manual u13987ej1v0um00 table 25-3. halt mode release by maskable interrupt request release source mk note 1 ie note 2 state on release operation after release maskable 0 1 ? interrupt service program not being interrupt request acknowledgment interrupt request executed (excluding macro ? low-priority maskable interrupt service service request) program being executed ? prsl bit note 4 cleared (to 0) during execution of priority level 3 interrupt service program ? same-priority maskable interrupt service execution of instruction after mov stbc, program being executed #byte instruction (interrupt request that (if prsl bit note 4 is cleared (to 0), excluding released halt mode is held pending note 3 ) execution of priority level 3 interrupt service program) ? high-priority interrupt service program being executed 00 1 halt mode maintained macro service 0 macro service processing execution request end condition not established ? halt mode again end condition established ? if vcie note 5 = 1: halt mode again if vcie note 5 = 0: same as release by maskable interrupt request 1 halt mode maintained notes 1. interrupt mask bit in individual interrupt request source 2. interrupt enable flag in program status word (psw) 3. pending interrupt requests are acknowledged when acknowledgment becomes possible. 4. bit in interrupt mode control register (imc) 5. bit in macro service mode register of macro service control word in individual macro service request source (3) release by reset input the program is executed after branching to the reset vector address, as in a normal reset operation. however, internal ram contents retain their value directly before halt mode was set. 646 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.4 stop mode 25.4.1 stop mode setting and operating status the stop mode is selected by setting (to 1) the stp bit of the standby control register (stbc) register. the only writes that can be performed on stbc are 8-bit data writes by means of a dedicated instruction. stop mode setting is therefore performed by means of the mov stbc, #byte instruction. caution if the stop mode is set when the condition to release the halt mode is satisfied (refer to 25.3.2 halt mode release), the stop mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. to accurately set the stop mode, clear the interrupt request before setting the stop mode. table 25-4. operating status in stop mode clock oscillator oscillation stopped internal system clock stopped cpu operation stopped i/o lines retain state prior to stop mode setting peripheral functions all operation stopped note internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 high-impedance rd, wr output high-impedance astb output high-impedance refrq output retained hldrq input high-impedance hldak output low level note a/d converter operation is stopped, but if the cs bit of the a/d converter mode register (adm) is set (to 1), the current consumption does not decrease. cautions 1. if the stop mode is set when the extc bit of the oscillation stabilization time specification (osts) register is cleared (to 0), the x1 pin is shorted internally to v ss (gnd potential) to suppress clock generator leakage. therefore, when the stop mode is used in a system that uses an external clock, the extc bit of osts must be set (to 1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of osts is cleared (to 0), the m pd784938 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator). 2. the cs bit of the a/d converter mode (adm) register should be cleared (to 0). 647 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.4.2 stop mode release stop mode is released by nmi input, intp4 input, intp5 input, intw input, and reset input. table 25-5. stop mode release and operations after release release source mk note 1 ism note 2 ie note 3 state after release operation after release reset input normal reset operation nmi pin input ? non-maskable interrupt service interrupt request acknowledgment program not being executed ? low-priority non-maskable interrupt service program being executed ? nmi pin input service program being execution of instruction after mov executed stbc, #byte instruction (interrupt ? high-priority non-maskable interrupt request that released stop mode is service program being executed held pending note 4 ) intp4/intp5 0 0 1 ? interrupt service program not being interrupt request acknowledgment pin input, executed intw input ? low-priority maskable interrupt service program being executed ? prsl bit note 5 cleared (to 0) during execution of priority level 3 interrupt service program ? same-priority maskable interrupt execution of instruction after mov service program being executed stbc, #byte instruction (interrupt (if prsl bit note 5 is cleared (to 0), request that released stop mode is excluding execution of priority level 3 held pending note 4 ) interrupt service program) ? high-priority interrupt service program being executed 000 10 stop mode maintained 1 notes 1. interrupt mask bit in individual interrupt request source 2. macro service enable flag in individual interrupt request source 3. interrupt enable flag in program status word (psw) 4. pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. bit in interrupt mode control register (imc) 648 chapter 25 standby function preliminary users manual u13987ej1v0um00 (1) stop mode release by nmi input the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. stop mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (osts). when the m pd784938 is released from stop mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the stop mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the stop mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). see 23.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. figure 25-5. stop mode release by nmi input oscillator f xx /2 stp f/f1 nmi input rising edge specified stp f/f2 oscillator stopped stop oscillation stabilization count time 649 chapter 25 standby function preliminary users manual u13987ej1v0um00 (2) stop mode release by intp4 or intp5 input when masking of interrupts by intp4 and intp5 input is released and macro service is disabled, the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 1 (intm1) is input to the intp4 or intp5 input. following this, stop mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (osts) elapses. when the m pd784938 is released from stop mode, if an interrupt can be acknowledged when the interrupt enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the stop mode. see 23.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. figure 25-6. stop mode release by intp4/intp5 input intp4, intp5 input rising edge specified oscillator f xx /2 stp f/f1 stp f/f2 oscillation stopped stop oscillation stabilization count time (3) stop mode release by reset input when reset input falls from high to low and the reset state is established, the oscillator resumes oscillation. the oscillation stabilization time should be secured while reset is active. thereafter, normal operation is started when reset rises. unlike an ordinary reset operation, data memory retains its contents prior to stop mode setting. 650 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.5 idle mode 25.5.1 idle mode setting and operating status the idle mode is selected by setting (to 1) both the stp bit and the hlt bit of the standby control (stbc) register. the only writes that can be performed on the stbc are 8-bit data writes by means of a dedicated instruction. idle mode setting is therefore performed by means of the mov stbc, #byte instruction. caution if the idle mode is set when the condition to release the halt mode is satisfied (refer to 25.3.2 halt mode release), the idle mode is not set, but the next instruction is executed or execution branches to a vectored interrupt service program. to accurately set the idle mode, clear the interrupt request before setting the idle mode. table 25-6. operating states in idle mode clock oscillator oscillation continued internal system clock stopped cpu operation stopped i/o lines retain state prior to idle mode setting peripheral functions all operation excluding watch timer (wm3 = 1, wm6 = 0) stopped note internal ram retained bus lines ad0 to ad7 high-impedance a8 to a19 high-impedance rd, wr output high-impedance astb output high-impedance refrq output retained hldrq input high-impedance hldak output low level note a/d converter operation is stopped, but if the cs bit of the a/d converter mode register (adm) is set, the current consumption does not decrease. caution the cs bit of the a/d converter mode (adm) register should be reset. 651 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.5.2 idle mode release idle mode is released by nmi input, intp4 input, intp5 input, intw input, or reset input. table 25-7. idle mode release and operations after release release source mk note 1 ism note 2 ie note 3 state after release operation after release reset input normal reset operation nmi pin input ? non-maskable interrupt service interrupt request acknowledgment program not being executed ? low-priority non-maskable interrupt service program being executed ? nmi pin input service program being execution of instruction after mov executed stbc, #byte instruction (interrupt ? high-priority non-maskable interrupt request that released idle mode is service program being executed held pending note 4 ) intp4/intp5 0 0 1 ? interrupt service program not being interrupt request acknowledgment pin input, executed intw input ? low-priority maskable interrupt service program being executed ? prsl bit note 5 cleared (to 0) during execution of priority level 3 interrupt service program ? same-priority maskable interrupt execution of instruction after mov service program being executed stbc, #byte instruction (interrupt (if prsl bit note 5 is cleared (to 0), request that released idle mode is excluding execution of priority level 3 held pending note 4 ) interrupt service program) ? high-priority interrupt service program being executed 000 10 idle mode maintained 1 notes 1. interrupt mask bit in individual interrupt request source 2. macro service enable flag in individual interrupt request source 3. interrupt enable flag in program status word (psw) 4. pending interrupt requests are acknowledged when acknowledgment becomes possible. 5. bit in interrupt mode control register (imc) 652 chapter 25 standby function preliminary users manual u13987ej1v0um00 (1) idle mode release by nmi input idle mode is released when the valid edge specified by external interrupt mode register 0 (intm0) is input to the nmi input. when the m pd784938 is released from idle mode, if a non-maskable interrupt by nmi pin input can be acknowledged, a branch is made to the nmi interrupt service program. if the interrupt cannot be acknowledged (if the idle mode is set in an nmi interrupt service program, etc.), execution is resumed from the instruction following the instruction that set the idle mode, and a branch is made to the nmi interrupt service program when acknowledgment becomes possible (by execution of an reti instruction, etc.). see 23.6 non-maskable interrupt acknowledgment operation for details of nmi interrupt acknowledgment. (2) idle mode release by intp4 or intp5 input when masking of interrupts by intp4 and intp5 input is released and macro service is disabled, idle mode is released when the valid edge specified by external interrupt mode register 1 (intm1) is input to the intp4 or intp5 input. when the m pd784938 is released from idle mode, if an interrupt can be acknowledged when the interrupt enable flag (ie) is set (to 1), a branch is made to the interrupt service program. if the interrupt cannot be acknowledged and if the ie flag is cleared (to 0), execution is resumed from the instruction following the instruction that set the idle mode. see 23.7 maskable interrupt acknowledgment operation for details of interrupt acknowledgment. (3) idle mode release by reset input when reset input falls from high to low and the reset state is established, the oscillator resumes oscillation. the oscillation stabilization time should be secured while reset is active. thereafter, normal operation is started when reset rises. unlike an ordinary reset operation, data memory retains its contents prior to idle mode setting. 653 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.6 check items when stop mode/idle mode is used check items required to reduce the current consumption when stop mode/idle mode is used are shown below. (1) is the output level of each output pin appropriate? the appropriate output level for each pin varies according to the next-stage circuit. you should select the output level that minimizes the current consumption. ? if high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power supply to the port, resulting in an increased current consumption. this applies when the next-stage circuit is a cmos ic, etc. when the power supply is off, the input impedance of a cmos ic is low. in order to suppress the current consumption, or to prevent an adverse effect on the reliability of the cmos ic, low level should be output. if a high level is output, latchup may result when power is turned on again. ? depending on the next-stage circuit, inputting low level may increase the current consumption. in this case, high- level or high-impedance output should be used to reduce the current consumption. ? if the next-stage circuit is a cmos ic, the current consumption of the cmos ic may increase if the output is made high-impedance when power is supplied to it (the cmos ic may also be overheated and damaged). in this case you should output an appropriate level, or pull the output high or low with a resistor. the method of setting the output level depends on the port mode. ? when a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore the on-chip hardware status must be taken into consideration when setting the output level. ? in port mode, the output level can be set by writing to the port output latch and port mode register by software. when a port is in control mode, its output level can be set easily by changing to port mode. 654 chapter 25 standby function preliminary users manual u13987ej1v0um00 (2) is the input pin level appropriate? the voltage level input to each pin should be in the range between v ss potential and v dd potential. if a voltage outside this range is applied, the current consumption will increase and the reliability of the m pd784938 may be adversely affected. also ensure that an intermediate potential is not applied. (3) are pull-up resistors necessary? an unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. a mode should be specified in which pull-up resistors are used only for parts that require them. if there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull- up resistor externally and specify a mode in which the on-chip pull-up resistor is not used. (4) is processing of the address bus, address/data bus, etc., appropriate? in stop mode and idle mode, the address bus, address/data bus, rd and wr pins become high-impedance. normally, these pins are pulled high with a pull-up resistor. if this pull-up resistor is connected to the backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow through the pull-up resistor, and the current consumption will increase. therefore, the pull-up resistor should be connected to the non-backed-up power supply side as shown in figure 25-7. also, in stop mode and idle mode the astb pin also becomes high impedance, and the refrq/hldak pin adopts a fixed level. countermeasures should be taken with reference to the points noted in (to 1). figure 25-7. example of address/data bus processing v dd v dd in/out cmos ic, etc. v ss v ss non-backed-up power supply adn (n = 0 to 7) m pd784938 backed-up power supply the voltage level input to the wait/hldrq pin should be in the range between v ss potential and v dd potential. if a voltage outside this range is applied, the current consumption will increase and the reliability of the m pd784938 may be adversely affected. (5) a/d converter the current flowing to the av dd , av ref1 pins can be reduced by clearing (0) the cs bit (bit 7) of the a/d converter mode register (adm). the current can be further reduced, if required, by cutting the current supply to the av dd , av ref1 pins with external circuitry. make sure that the av dd pin is not at the same potential as the v dd pin. unless power is supplied to the av dd pin in the stop mode, not only does the current consumption increase, but the reliability is also affected. 655 chapter 25 standby function preliminary users manual u13987ej1v0um00 25.7 cautions (1) if halt/stop/idle mode (standby mode hereafter) setting is performed when a condition that release halt mode (refer to 25.3.2 halt mode release ) is satisfied, standby mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed. to ensure that a definite standby mode setting is made, interrupt requests should be cleared, etc. before entering standby mode. (2) when crystal/ceramic oscillation is used, the extc bit must be cleared (to 0) before use. if the extc bit is set (to 1), oscillation will stop. (3) if the stop mode is set when the extc bit of the oscillation stabilization time specification (osts) register is cleared (to 0), the x1 pin is shorted internally to v ss (gnd potential) to suppress clock generator leakage. therefore, when the stop mode is used in a system that uses an external clock, the extc bit of osts must be set (to 1). if stop mode setting is performed in a system to which an external clock is input when the extc bit of the osts is cleared (to 0), the m pd784938 may suffer damage or reduced reliability. when setting the extc bit of osts to 1, be sure to input a clock in phase reverse to that of the clock input to the x1 pin, to the x2 pin (refer to 4.3.1 clock oscillator ). (4) in stop mode and idle mode, the cs bit of the a/d converter mode adm register should be cleared (to 0). 656 preliminary users manual u13987ej1v0um00 [memo] 657 preliminary users manual u13987ej1v0um00 chapter 26 reset function 26.1 reset function when low level is input to the reset input pin, a system reset is affected, the various hardware units are set to the states shown in table 26-2, and all pins except the power supply pins and the x1 and x2 pins are placed in the high- impedance state. table 26-1 shows the pin statuses on reset and after reset release. when the reset input changes from low to high level, the reset state is released, the contents of address 00000h of the reset vector table are set in bits 0 to 7 of the program counter (pc), the contents of address 00001h in bits 8 to 15, and 0000b in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. a reset start can therefore be performed from any address in the base area. the contents of the various registers should be initialized as required in the program in the base area. to prevent misoperation due to noise, the reset input pin incorporates an analog delay noise elimination circuit (see figure 26-1 ). figure 26-1. reset signal acknowledgment delay pc initialization, etc. execution of instruction at reset start address reset start delay delay reset end internal reset signal reset (input) chapter 26 reset function 658 preliminary users manual u13987ej1v0um00 in a reset operation upon powering on, the reset signal must be kept active until the oscillation stabilization time has elapsed. as the time taken for oscillation stabilization is influenced by the crystal oscillator/ceramic resonator used and the capacitance of capacitor connected, please contact the manufacturer of the crystal oscillator/ceramic resonator for details. figure 26-2. power-on reset operation oscillation stabilization time v dd delay pc initialization, etc. execution of instruction at reset start address internal reset signal reset end reset (input) remark f clk : internal system clock frequency table 26-1. pin statuses during reset input and after reset release pin name input/output on reset directly after reset release p00 to p07 input/output hi-z hi-z (input port mode) p10 to p17 input/output hi-z hi-z (input port mode) p20/nmi to p27/si input hi-z hi-z (input port) p30/rxd/si1 to p37/to3 input/output hi-z hi-z (input port mode) p40/ad0 to p47/ad7 input/output hi-z hi-z (input port mode) p50/a8 to p57/a15 input/output hi-z hi-z (input port mode) p60/a16 to p63/a19 input/output hi-z hi-z (input port mode) p64/rd, p65/wr input/output hi-z hi-z (input port mode) p66/wait, p67/refrq input/output hi-z hi-z (input port mode) p70/ani0 to p77/ani7 input/output hi-z hi-z (input port mode) p90 to p97 input/output hi-z hi-z (input port mode) p100 to p107/so3 input/output hi-z hi-z (input port mode) astb/clkout output hi-z 0 pwm0, pwm1 output hi-z low level output tx output hi-z low level output rx input hi-z hi-z (input port) 659 chapter 26 reset function preliminary users manual u13987ej1v0um00 table 26-2. hardware status after reset (1/2) hardware state after reset program counter (pc) set with contents of reset vector table (0000h/0001h). stack pointer (sp) undefined note program status word (psw) 02h on-chip ram data memory undefined note general-purpose registers ports ports 0, 1, 2, 3, 4, 5, 6, 7, 9, 10 undefined (high impedance) port mode registers pm0, 1, 3, 4, 5, 6, 7, 9, 10 ffh port mode control registers (pmc1, pmc3, pmc10) 00h pull-up resistor option register (puol, puoh) 00h real-time output port control register (rtpc) 00h timer/counter timer counters (tm0, tm1w, tm2w, tm3w) 0000h compare registers (cr00, cr01, cr10lw, cr20w, cr30w) undefined capture registers (cr02, cr12w, cr22w) capture/compare registers (cr11w, cr21w) timer control registers (tmc0, tmc1) 00h timer output control register (toc) capture/compare control registers crc0 10h crc1, crc2 00h prescaler mode registers (prm0, prm1) 00h one-shot pulse output control register (ospc) 00h pwm pwm control register (pwmc) 05h pwm prescaler register (pwpr) 00h pwm modulo registers (pwm0, pwm1) undefined a/d converter a/d converter mode register (adm) 00h a/d conversion result register (adcr) undefined a/d current cut select register (iead) 00h rom correction rom correction address register h (corah) 00h rom correction address register l (coral) 0000h rom correction control register (corc) 00h serial interface clocked serial interface mode registers (csim, csim1, csim2, csim3) 00h serial shift registers (sio, sio1, sio2, sio3) undefined asynchronous serial interface mode registers (asim, asim2) 00h asynchronous serial interface status registers (asis, asis2) 00h serial receive buffers (rxb, rxb2) undefined serial transmit shift registers (txs, txs2) undefined baud rate generator control registers (brgc, brgc2) 00h note when halt mode, stop mode, or idle mode is released by reset input, the value before that mode was set is retained. chapter 26 reset function 660 preliminary users manual u13987ej1v0um00 table 26-2. hardware status after reset (2/2) hardware state after reset clock output function (clom) 00h watch timer mode register (wm) 00h memory extension mode register (mm) 20h programmable wait control registers pwc1 aah pwc2 aaaah refresh function refresh mode register (rfm) 00h refresh area specification register (rfa) 00h hold mode register (hldm) 00h interrupts interrupt control registers (pic0, pic1, pic2, pic3, pic4, pic5, cic00, 43h cic01, cic10, cic11, cic20, cic21, cic30, adic, seric, sric, stic, seric2, sric2, stic2, csiic, csiic1, csiic2, ieic1, ieic2, wic, csiic3) interrupt mask registers mk0 ffffh mk1 ffh in-service priority register (ispr) 00h interrupt mode control register (imc) 00h external interrupt mode registers (intm0, intm1) 00h sampling clock selection register (scs0) 00h standby control register (stbc) 30h oscillation stabilization time specification register (osts) 00h internal memory size switching register (ims) ffh iebus controller bus control register (bcr) 00h unit address register (uar) 0000h slave address register (sar) partner address register (par) control data register (cdr) 01h telegraph-length register (dlr) data register (dr) 00h unit status register (usr) interrupt status register (isr) slave status register (ssr) 41h success count register (scr) 01h communication count register (ccr) 20h 661 chapter 26 reset function preliminary users manual u13987ej1v0um00 figure 26-3. reset input timing hi-z other i/o ports reset (input) hi-z astb (output) reset period reset release ?instruction execution period chapter 26 reset function 662 preliminary users manual u13987ej1v0um00 26.2 caution reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached the prescribed voltage. 663 preliminary users manual u13987ej1v0um00 chapter 27 rom correction 27.1 rom correction functions m pd784938 converts part of the program within the mask rom into the program within the internal expansion rom. the use of rom correction enables command bugs discovered in the mask rom to be repaired, and change the flow of the program. rom correction can be used in a maximum of four locations within the internal rom (program). caution note that rom correction cannot perform emulation in the in-circuit emulator (ie-784000-r, ie-784000- r-em). in more detail, the command addresses that require repair from the inactive memory connected to an external microcontroller by a user program and the repair command codes are loaded into the peripheral ram. the above addresses and the internal rom access addresses are compared by the comparator built into the microcontroller during execution of internal rom programs (during command fetch), and internal roms output data is then converted to call command (callt) codes and output when a match is determined. when the callt command codes are changed to valid commands by the cpu and executed, the callt table is referenced, and the process routine and other peripheral ram are branched. at this point, a callt table is prepared for each repair address for referencing purposes. four repair address can be set for the m pd784938. matches with address pointer 0: callt table (0078h) conversion command code: fch matches with address pointer 1: callt table (007ah) conversion command code: fdh matches with address pointer 2: callt table (007ch) conversion command code: feh matches with address pointer 3: callt table (007eh) conversion command code: ffh cautions 1. as it is necessary to reserve four locations for the callt tables when the rom correction function is used (0078h, 007ah, 007ch, 007eh), ensure that these are not used for other applications. however, the callt tables can be used if the rom correction function is not being used. 2. if there are two or more channels for which the correction operation is enabled, do not set the same correction address. 3. be sure to set the address where the start command code is stored as the correction address. the differences between 78k/iv rom correction and 78k/0 rom correction are shown in table 27-1. 664 chapter 27 rom correction preliminary users manual u13987ej1v0um00 table 27-1. differences between 78k/iv rom correction and 78k/0 rom correction difference 78k/iv 78k/0 generated command codes callt instruction peripheral ram (1-byte instruction: fch, fdh, feh, ffh) address comparison conditions instruction fetch only instruction fetch only correction status flag none yes as there is a possibility that the addresses match owing to an invalid fetch, the status is not necessary jump destination address during correction callt table fixed address on the peripheral ram 0078h, 007ah, 007ch, 007eh 665 chapter 27 rom correction preliminary users manual u13987ej1v0um00 27.2 rom correction configuration rom correction is composed of the following hardware. table 27-2. rom correction configuration item configuration register rom correction address register h, l (corah, coral) control register rom correction control register (corc) a rom correction block diagram is shown in figure 27-1, and figure 27-2 shows an example of memory mapping. figure 27-1. rom correction block diagram internal bus program counter (pc) comparator correction address pointer n rom correction address register (corah, coral) match correction branch process request signal (callt command) rom correction control register (corc) corenn corchm remark n = 0 to 3, m = 0, 1 666 chapter 27 rom correction preliminary users manual u13987ej1v0um00 figure 27-2. memory mapping example ( m pd784938) vector table area internal rom high-speed internal ram peripheral ram (correction program) sfr internal ram internal rom (reference table 3) (reference table 2) (reference table 1) (reference table 0) callt table area 03ffffh 00ffffh 00ff00h 00feffh 00d600h 00d5ffh 000000h 000000h 00003fh 000040h 00007fh 00d600h 00fd00h 00feffh 00fcffh 667 chapter 27 rom correction preliminary users manual u13987ej1v0um00 (1) rom correction address register (corah, coral) the register that sets the header address (correction address) of the command within the mask rom that needs to be repaired. a maximum of four program locations can be repaired with rom correction. first of all, the channel is selected with bit 0 (corch0) and bit 1 (corch1) of the rom correction control register (corc), and the address is then set in the specified channels address pointer when the address is written in corah and coral. figure 27-3. rom correction address register (corah, coral) format 70 0 15 coral corah ff79h address 00h after reset r/w r/w ff7ah address 0000h after reset r/w r/w (2) comparator the rom correction address registers h and l (corah, coral) normally compare the corrected address value with the fetch register value. if any of the rom correction control register (corc) bits between bit 4 to bit 7 (coren0 to 3) are 1 and the correct address matches the fetch address value, a table reference instruction (callt) is issued from the rom correction circuit. 27.3 control register for rom correction rom correction is controlled by the rom correction control register (corc). (1) rom correction control register (corc) the register that controls the issuance of the table reference instruction (callt) when the correct address set in rom correction address registers h and l (corah, coral) match the value of the fetch address. this is composed of a correction enable flag (coren0 to 3) that enables or disables match detection with the comparator, and four channel correction pointers. corc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets corc to 00h. 668 chapter 27 rom correction preliminary users manual u13987ej1v0um00 figure 27-4. rom correction control register (corc) format corc coren3 76 5 4321 coren2 coren1 coren0 0 0 corch1 0 corch0 address 0ff88h r/w after reset 00h symbol corenn 0 1 controls the match detection for the rom correction address register and the fetch address. disabled enabled corch1 corch0 0 0 address pointer channel 0 address pointer channel 1 address pointer channel 2 address pointer channel 3 01 10 11 channel selection remark n = 0 to 3 669 chapter 27 rom correction preliminary users manual u13987ej1v0um00 27.4 use of rom correction <1> the correct address and post-correction instruction (correction program) are stored in the microcontroller external non-volatile memory (eeprom). <2> a substitute instruction is read from the non-volatile memory with the use of a serial interface when the initialization program is running after being reset, and this is stored in the peripheral ram and external memory. the correction channel is then selected, the address for the command that requires correction is read and set in the rom correction address registers (corah, coral), and the correction enable flag (coren0 to 3) is set at 1. a maximum of four locations can be set. <3> execute the callt instruction during execution of the corrected address. callt execution program execution (internal rom) correct address executed? no yes <4> callt routine branch when matched with address pointer 0: callt table (0078h) when matched with address pointer 1: callt table (007ah) when matched with address pointer 2: callt table (007ch) when matched with address pointer 3: callt table (007eh) <5> execute substitute instruction <6> add +3 to the stack pointer (sp) <7> restore to any addresses with the branch instruction (br) 670 chapter 27 rom correction preliminary users manual u13987ej1v0um00 27.5 conditions for executing rom correction in order to use the rom correction function, it is necessary for the external environment and program to satisfy the following conditions. (1) external environment must be connected externally to an non-volatile memory, and be configured to read that data. (2) target program the data setting instruction for corc, corah and coral will be previously annotated in the target program (program stored in the rom). the set-up data (the items written in lower-case in the set-up example below) must be read from the external non-volatile memory, and the correct number of required correction pointers must be set. example of four pointer settings mov corc, #00h; specified channel 0 movw coral, # ch0 datal; sets the channel 0 matching address mov corah, # ch0 datah; sets the channel 0 matching address mov corc, #01h; specified channel 1 movw coral, # ch1 datal; sets the channel 1 matching address mov corah, # ch1 datah; sets the channel 1 matching address mov corc, #02h; specified channel 2 movw coral, # ch2 datal; sets the channel 2 matching address mov corah, # ch2 datah; sets the channel 2 matching address mov corc, #chh; specified channel 3 mov coral, # ch3 datah; sets the channel 3 matching address mov corah, # ch3 datal; sets the channel 3 matching address mov corc, #romc or en ; sets 00h when correction is disabled ; sets f0h when correction is operated br $normal br ! ! c or addr; specifies the address of the correction program ; nomal instruction ; next instruction (3) setting the branch instruction in the callt table. in the case of the above program, the header address for the br!!cor_addr instruction is specified. (cor addr indicates the address where the correction program is located.) the reason for this being branched into the callt instruction and br instruction is owing to the fact that only the base area can be branched with callt. there is no necessity to branch into two levels when it is to be attached to the ram base area with the location instruction. 671 preliminary users manual u13987ej1v0um00 chapter 28 m pd78f4938 programming the m pd78f4938 is a flash memory version of the m pd784938 subseries. the m pd78f4938 has on-chip flash memory that allows write, erase, and rewrite of programs in the state in which it is mounted on the substrate. table 28-1 shows the differences between the flash memory version ( m pd78f4938) and the mask rom versions ( m pd784935, 784936, 784937, and 784938). table 28-1. differences between the m pd78f4938 mask rom versions item m pd78f4938 mask rom versions internal rom type flash memory mask rom internal rom capacity 256 kbytes m pd784935: 96 kbytes m pd784936: 128 kbytes m pd784937: 192 kbytes m pd784938: 256 kbytes internal ram capacity 10,240 bytes m pd784935: 5,120 bytes m pd784936: 6,656 bytes m pd784937: 8,192 bytes m pd784938: 10,240 bytes internal memory size switching register (ims) available not available ic pin not available available v pp pin available not available caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass- producing it with the mask rom version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask rom version. 672 chapter 28 m pd78f4938 programming preliminary users manual u13987ej1v0um00 28.1 internal memory size switching register (ims) ims is a register to prevent a certain part of the internal memory from being used by software. by setting the ims, it is possible to establish a memory map that is the same as that of mask rom version with a different internal memory (rom, ram) with capacity. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to ffh. figure 28-1. internal memory size switching register (ims) format ims 1 76 5 4321 1 rom1 rom0 1 1 ram1 0 ram0 address 0fffch w after reset ffh symbol rom1 rom0 0 0 256 kbytes 96 kbytes 128 kbytes 192 kbytes 01 10 11 internal rom capacity selection ram1 ram0 0 0 10,240 bytes 5,120 bytes 8,192 bytes 6,656 bytes 01 10 11 internal ram capacity selection caution ims is not available for mask rom versions ( m pd784935, 784936, 784937, and 784938). the ims settings to create the same memory map as mask rom versions are shown in table 28-2. table 28-2. internal memory size switching register (ims) settings relevant mask rom version ims setting m pd784935 ddh m pd784936 eeh m pd784937 ffh m pd784938 cch 673 chapter 28 m pd78f4938 programming preliminary users manual u13987ej1v0um00 28.2 flash memory programming using flashpro ii and flashpro iii flash memory can be written while mounted on the target system (on-board writing). connect the dedicated flash programmer (flashpro ii (part number fl-pr2), flashpro iii (part number fl-pr3 and fg-fp3)) to the host computer and target system for programming. moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to flashpro ii or flashpro iii. remark fl-pr2 and fl-pr3 are products of naito densei machida mfg. co., ltd. 28.2.1 selecting communication mode the flashpro ii or iii is used to write data into a flash memory by serial communications. select the communication mode for writing from table 28-3. figure 28-2 shows the format used to select the communication mode. each communication mode is selected with the number of v pp pulses shown in table 28-3. table 28-3. communication mode communication mode number of channels pins used number of v pp pulses 3-wire serial i/o 1 sck3/p105 1 si3/p106 so3/p107 uart 1 rxd/p30 8 txd/p31 caution always select the communication mode using the number of v pp pulses shown in table 28-3. figure 28-2. communication mode selection format 10 v v dd v ss v dd v ss v pp reset 12 n v pp pulses flash memory write mode 674 chapter 28 m pd78f4938 programming preliminary users manual u13987ej1v0um00 28.2.2 flash memory programming functions by transmitting and receiving various commands and data by the selected communication mode, operations such as writing to the flash memory are performed. table 28-4 shows the major functions. table 28-4. flash memory programming functions function description batch erase erase the entire memory contents. block erase erase the contents of the specified memory block where one memory block is 16 kbytes. batch blank check checks the erase state of the entire memory. block blank check checks the erase state of the specified block. data write writes to the flash memory based on the start write address and the number of data written (number of bytes). batch verify compares the data input to the contents of the entire memory. block verify compares the data input to the contents of the specified memory block. verification for the flash memory entails supplying the data to be verified from an external source via a serial interface, and then outputting the existence of unmatched data to the external source after referencing the blocks or all of the data. consequently, the flash memory is not equipped with a read function, and it is not possible for third parties to read the contents of the flash memory with the use of the verification function. 675 chapter 28 m pd78f4938 programming preliminary users manual u13987ej1v0um00 28.2.3 connecting flashpro ii or flashpro iii the connection between the flashpro ii or flashpro iii and the m pd78f4938 differs with the communication mode (3- wire serial i/o or uart). figures 28-3 and 28-4 are the connection diagrams in each case. figure 28-3. flashpro ii and flashpro iii connection in 3-wire serial i/o mode v pp v dd reset sck so si v ss v pp v dd reset sck si so v ss flashpro ii or flashpro iii pd78f4938 m figure 28-4. flashpro ii and flashpro iii connection in uart mode v pp v dd reset so si v ss v pp v dd reset rxd txd v ss flashpro ii or flashpro iii pd78f4938 m 676 preliminary users manual u13987ej1v0um00 [memo] 677 preliminary users manual u13987ej1v0um00 chapter 29 instruction operations 29.1 conventions (1) operand identifiers and descriptions (1/2) identifier description r, r note 1 x (r0), a (r1), c (r2), b (r3), r4, r5, r6, r7, r8, r9, r10, r11, e (r12), d (r13), l (r14), h (r15) r1 note 1 x (r0), a (r1), c (r2), b (r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e (r12), d (r13), l (r14), h (r15) r3 v, u, t, w rp, rp note 2 ax (rp0), bc (rp1), rp2, rp3, vp (rp4), up (rp5), de (rp6), hl (rp7) rp1 note 2 ax (rp0), bc (rp1), rp2, rp3 rp2 vp (rp4), up (rp5), de (rp6), hl (rp7) rg, rg vvp (rg4), uup (rg5), tde (rg6), whl (rg7) sfr special function register symbol (see special function register application table ) sfrp special function register symbol (register for which 16-bit operation is possible: see special function register application table ) post note 2 ax (rp0), bc (rp1), rp2, rp3, vp (rp4), up (rp5)/psw, de (rp6), hl (rp7) multiple descriptions are permissible. however, up is only used with push/pop instructions, and psw with pushu/popu instructions. mem [tde], [whl], [tde+], [whl+], [tdeC], [whlC], [vvp], [uup]: register indirect addressing [tde+byte], [whl+byte], [sp+byte], [uup+byte], [vvp+byte]: based addressing imm24 [a], imm24 [b], imm24 [de], imm24 [hl]: indexed addressing [tde+a], [tde+b], [tde+c], [whl+a], [whl+b], [whl+c], [vvp+de], [vvp+hl]: based indexed addressing mem1 all mem except [whl+] and [whlC] mem2 [tde], [whl] mem3 [ax], [bc], [rp2], [rp3], [vvp], [uup], [tde], [whl] notes 1. setting the rss bit to 1 enables r4 to r7 to be used as x, a, c, and b, but this function should only be used when using a 78k/iii series program. 2. setting the rss bit to 1 enables rp2 and rp3 to be used as ax and bc, but this function should only be used when using a 78k/iii series program. 678 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (1) operand identifiers and descriptions (2/2) identifier description note saddr, saddr fd20h to ff1fh immediate data or label saddr1 fe00h to feffh immediate data or label saddr2 fd20h to fdffh, ff00h to ff1fh immediate data or label saddrp fd20h to ff1eh immediate data or label (16-bit operation) saddrp1 fe00h to feffh immediate data or label (16-bit operation) saddrp2 fd20h to fdffh, ff00h to ff1eh immediate data or label (16-bit operation) saddrg fd20h to fefdh immediate data or label (24-bit operation) saddrg1 fe00h to fefdh immediate data or label (24-bit operation) saddrg2 fd20h to fdffh immediate data or label (24-bit operation) addr24 0h to ffffffh immediate data or label addr20 0h to fffffh immediate data or label addr16 0h to ffffh immediate data or label addr11 800h to fffh immediate data or label addr8 0fe00h to 0feffh note immediate data or label addr5 40h to 7eh immediate data or label imm24 24-bit immediate data or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data locaddr 00h or 0fh note the addresses shown here apply when 00h is specified by the location instruction. when 0fh is specified by the location instruction, f0000h should be added to the address values shown. 679 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (2) operand column symbols symbol description + auto-increment C auto-decrement # immediate data ! 16-bit absolute address !! 24-bit/20-bit absolute address $ 8-bit relative address $! 16-bit relative address / bit inversion [ ] indirect addressing [%] 24-bit indirect addressing (3) flag column symbols symbol description (blank) no change 0 cleared to 0 1 set to 1 set or cleared depending on result p p/v flag operates as parity flag v p/v flag operates as overflow flag r previously saved value is restored (4) operation column symbols symbol description jdisp8 signed twos complement data (8 bits) indicating relative address distance between start address of next instruction and branch address jdisp16 signed twos complement data (16 bits) indicating relative address distance between start address of next instruction and branch address pc hw pc bits 16 to 19 pc lw pc bits 0 to 15 680 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (5) number of bytes of instruction that includes mem in operands mem mode register indirect addressing based indexed based indexed addressing addressing addressing number of bytes 1 2 note 352 note one-byte instruction only when [tde], [whl], [tde+], [tdeC], [whl+], or [whlC] is written as mem in an mov instruction. (6) number of bytes of instruction that includes saddr, saddrp, r, or rp in operands for some instructions that include saddr, saddrp, r, or rp in their operands, two bytes entries are given, separated by a slash (/). the entry that applies is shown in the table below. identifier left-hand bytes figure right-hand bytes figure saddr saddr2 saddr1 saddrp saddrp2 saddrp1 rr1 r2 rp rp1 rp2 (7) description of instructions that include mem in operands and string instructions operands tde, whl, vvp, and uup (24-bit registers) can also be written as de, hl, vp, and up respectively. however, they are still treated as tde, whl, vvp, and uup (24-bit registers) when written as de, hl, vp, and up. 681 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 29.2 list of operations (1) 8-bit data transfer instruction: mov mnemonic operands bytes operation flags s z ac p/v cy mov r, #byte 2/3 r ? byte saddr, #byte 3/4 (saddr) ? byte sfr, #byte 3 sfr ? byte !addr16, #byte 5 (saddr16) ? byte !!addr24, #byte 6 (addr24) ? byte r, r 2/3 r ? r a, r 1/2 a ? r a, saddr2 2 a ? (saddr2) r, saddr 3 r ? (saddr) saddr2, a 2 (saddr2) ? a saddr, r 3 (saddr) ? r a, sfr 2 a ? sfr r, sfr 3 r ? sfr sfr, a 2 sfr ? a sfr, r 3 sfr ? r saddr, saddr 4 (saddr) ? (saddr) r, !addr16 4 r ? (addr16) !addr16, r 4 (addr16) ? r r, !!addr24 5 r ? (addr24) !!addr24, r 5 (addr24) ? r a, [saddrp] 2/3 a ? ((saddrp)) a, [%saddrg] 3/4 a ? ((saddrg)) a, mem 1 to 5 a ? (mem) [saddrp], a 2/3 ((saddrp)) ? a [%saddrg], a 3/4 ((saddrg)) ? a mem, a 1 to 5 (mem) ? a pswl, #byte 3 psw l ? byte pswh, #byte 3 psw h ? byte pswl, a 2 psw l ? a pswh, a 2 psw h ? a a, pswl 2 a ? psw l a, pswh 2 a ? psw h r3, #byte 3 r3 ? byte a, r3 2 a ? r3 r3, a 2 r3 ? a 682 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (2) 16-bit data transfer instruction: movw mnemonic operands bytes operation flags s z ac p/v cy movw rp, #word 3 rp ? word saddrp, #word 4/5 (saddrp) ? word sfrp, #word 4 sfrp ? word !addr16, #word 6 (addr16) ? word !!addr24, #word 7 (addr24) ? word rp, rp 2 rp ? rp ax, saddrp2 2 ax ? (saddrp2) rp, saddrp 3 rp ? (saddrp) saddrp2, ax 2 (saddrp2) ? ax saddrp, rp 3 (saddrp) ? rp ax, sfrp 2 ax ? sfrp rp, sfrp 3 rp ? sfrp sfrp, ax 2 sfrp ? ax sfrp, rp 3 sfrp ? rp saddrp, saddrp 4 (saddrp) ? (saddrp) rp, !addr16 4 rp ? (addr16) !addr16, rp 4 (addr16) ? rp rp, !!addr24 5 rp ? (addr24) !!addr24, rp 5 (addr24) ? rp ax, [saddrp] 3/4 ax ? ((saddrp)) ax, [%saddrg] 3/4 ax ? ((saddrg)) ax, mem 2 to 5 ax ? (mem) [saddrp], ax 3/4 ((saddrp)) ? ax [%saddrg], ax 3/4 ((saddrg)) ? ax mem, ax 2 to 5 (mem) ? ax 683 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (3) 24-bit data transfer instruction: movg mnemonic operands bytes operation flags s z ac p/v cy movg rg, #imm24 5 rg ? imm24 rg, rg 2 rg ? rg rg, !!addr24 5 rg ? (addr24) !!addr24, rg 5 (addr24) ? rg rg, saddrg 3 rg ? (saddrg) saddrg, rg 3 (saddrg) ? rg whl, [%saddrg] 3/4 whl ? ((saddrg)) [%saddrg], whl 3/4 ((saddrg)) ? whl whl, mem1 2 to 5 whl ? (mem1) mem1, whl 2 to 5 (mem1) ? whl (4) 8-bit data exchange instruction: xch mnemonic operands bytes operation flags s z ac p/v cy xch r, r 2/3 r ? r a, r 1/2 a ? r a, saddr2 2 a ? (saddr2) r, saddr 3 r ? (saddr) r, sfr 3 r ? sfr saddr, saddr 4 (saddr) ? (saddr) r, !addr16 4 r ? (addr16) r, !!addr24 5 r ? (addr24) a, [saddrp] 2/3 a ? ((saddrp)) a, [%saddrg] 3/4 a ? ((saddrg)) a, mem 2 to 5 a ? (mem) 684 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (5) 16-bit data exchange instruction: xchw mnemonic operands bytes operation flags s z ac p/v cy xchw rp, rp 2 rp ? rp ax, saddrp2 2 ax ? (saddrp2) rp, saddrp 3 rp ? (saddrp) rp, sfrp 3 rp ? sfrp ax, [saddrp] 3/4 ax ? ((saddrp)) ax, [%saddrg] 3/4 ax ? ((saddrg)) ax, !addr16 4 ax ? (addr16) ax, !!addr24 5 ax ? (addr24) saddrp, saddrp 4 (saddrp) ? (saddrp) ax, mem 2 to 5 ax ? (mem) (6) 8-bit operation instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operands bytes operation flags s z ac p/v cy add a, #byte 2 a, cy ? a + byte v r, #byte 3 r, cy ? r + byte v saddr, #byte 3/4 (saddr), cy ? (saddr) + byte v sfr, #byte 4 sfr, cy ? sfr + byte v r, r 2/3 r, cy ? r + r v a, saddr2 2 a, cy ? a + (saddr2) v r, saddr 3 r, cy ? r + (saddr) v saddr, r 3 (saddr), cy ? (saddr) + r v r, sfr 3 r, cy ? r + sfr v sfr, r 3 sfr, cy ? sfr + r v saddr, saddr 4 (saddr), cy ? (saddr) + (saddr) v a, [saddrp] 3/4 a, cy ? a + ((saddrp)) v a, [%saddrg] 3/4 a, cy ? a + ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ? ((saddrp)) + a v [%saddrg], a 3/4 ((saddrg)), cy ? ((saddrg)) + a v a, !addr16 4 a, cy ? a + (addr16) v a, !!addr24 5 a, cy ? a + (addr24) v !addr16, a 4 (addr16), cy ? (addr16) + a v !!addr24, a 5 (addr24), cy ? (addr24) + a v a, mem 2 to 5 a, cy ? a + (mem) v mem, a 2 to 5 (mem), cy ? (mem) + a v 685 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy addc a, #byte 2 a, cy ? a + byte + cy v r, #byte 3 r, cy ? r + byte + cy v saddr, #byte 3/4 (saddr), cy ? (saddr) + byte + cy v sfr, #byte 4 sfr, cy ? sfr + byte + cy v r, r 2/3 r, cy ? r + r + cy v a, saddr2 2 a, cy ? a + (saddr2) + cy v r, saddr 3 r, cy ? r + (saddr) + cy v saddr, r 3 (saddr), cy ? (saddr) + r + cy v r, sfr 3 r, cy ? r + sfr + cy v sfr, r 3 sfr, cy ? sfr + r + cy v saddr, saddr 4 (saddr), cy ? (saddr) + (saddr) + cy v a, [saddrp] 3/4 a, cy ? a + ((saddrp)) + cy v a, [%saddrg] 3/4 a, cy ? a + ((saddrg)) + cy v [saddrp], a 3/4 ((saddrp)), cy ? ((saddrp)) + a + cy v [%saddrg], a 3/4 ((saddrg)), cy ? ((saddrg)) + a + cy v a, !addr16 4 a, cy ? a + (addr16) + cy v a, !!addr24 5 a, cy ? a + (addr24) + cy v !addr16, a 4 (addr16), cy ? (addr16) + a + cy v !!addr24, a 5 (addr24), cy ? (addr24) + a + cy v a, mem 2 to 5 a, cy ? a + (mem) + cy v mem, a 2 to 5 (mem), cy ? (mem) + a + cy v 686 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy sub a, #byte 2 a, cy ? a C byte v r, #byte 3 r, cy ? r C byte v saddr, #byte 3/4 (saddr), cy ? (saddr) C byte v sfr, #byte 4 sfr, cy ? sfr C byte v r, r 2/3 r, cy ? r C r v a, saddr2 2 a, cy ? a C (saddr2) v r, saddr 3 r, cy ? r C (saddr) v saddr, r 3 (saddr), cy ? (saddr) C r v r, sfr 3 r, cy ? r C sfr v sfr, r 3 sfr, cy ? sfr C r v saddr, saddr 4 (saddr), cy ? (saddr) C (saddr) v a, [saddrp] 3/4 a, cy ? a C ((saddrp)) v a, [%saddrg] 3/4 a, cy ? a C ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ? ((saddrp)) C a v [%saddrg], a 3/4 ((saddrg)), cy ? ((saddrg)) C a v a, !addr16 4 a, cy ? a C (addr16) v a, !!addr24 5 a, cy ? a C (addr24) v !addr16, a 4 (addr16), cy ? (addr16) C a v !!addr24, a 5 (addr24), cy ? (addr24) C a v a, mem 2 to 5 a, cy ? a C (mem) v mem, a 2 to 5 (mem), cy ? (mem) C a v 687 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy subc a, #byte 2 a, cy ? a C byte C cy v r, #byte 3 r, cy ? r C byte C cy v saddr, #byte 3/4 (saddr), cy ? (saddr) C byte C cy v sfr, #byte 4 sfr, cy ? sfr C byte C cy v r, r 2/3 r, cy ? r C r C cy v a, saddr2 2 a, cy ? a C (saddr2) C cy v r, saddr 3 r, cy ? r C (saddr) C cy v saddr, r 3 (saddr), cy ? (saddr) C r C cy v r, sfr 3 r, cy ? r C sfr C cy v sfr, r 3 sfr, cy ? sfr C r C cy v saddr, saddr 4 (saddr), cy ? (saddr) C (saddr) C cy v a, [saddrp] 3/4 a, cy ? a C ((saddrp)) C cy v a, [%saddrg] 3/4 a, cy ? a C ((saddrg)) C cy v [saddrp], a 3/4 ((saddrp)), cy ? ((saddrp)) C a C cy v [%saddrg], a 3/4 ((saddrg)), cy ? ((saddrg)) C a C cy v a, !addr16 4 a, cy ? a C (addr16) C cy v a, !!addr24 5 a, cy ? a C (addr24) C cy v !addr16, a 4 (addr16), cy ? (addr16) C a C cy v !!addr24, a 5 (addr24), cy ? (addr24) C a C cy v a, mem 2 to 5 a, cy ? a C (mem) C cy v mem, a 2 to 5 (mem), cy ? (mem) C a C cy v 688 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy cmp a, #byte 2 a C byte v r, #byte 3 r C byte v saddr, #byte 3/4 (saddr) C byte v sfr, #byte 4 sfr C byte v r, r 2/3 r C r v a, saddr2 2 a C (saddr2) v r, saddr 3 r C (saddr) v saddr, r 3 (saddr) C r v r, sfr 3 r C sfr v sfr, r 3 sfr C r v saddr, saddr 4 (saddr) C (saddr) v a, [saddrp] 3/4 a C ((saddrp)) v a, [%saddrg] 3/4 a C ((saddrg)) v [saddrp], a 3/4 ((saddrp)) C a v [%saddrg], a 3/4 ((saddrg)) C a v a, !addr16 4 a C (addr16) v a, !!addr24 5 a C (addr24) v !addr16, a 4 (addr16) C a v !!addr24, a 5 (addr24) C a v a, mem 2 to 5 a C (mem) v mem, a 2 to 5 (mem) C a v 689 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy and a, #byte 2 a ? a byte p r, #byte 3 r ? r byte p saddr, #byte 3/4 (saddr) ? (saddr) byte p sfr, #byte 4 sfr ? sfr byte p r, r 2/3 r ? r r p a, saddr2 2 a ? a (saddr2) p r, saddr 3 r ? r (saddr) p saddr, r 3 (saddr) ? (saddr) r p r, sfr 3 r ? r sfr p sfr, r 3 sfr ? sfr r p saddr, saddr 4 (saddr) ? (saddr) (saddr) p a, [saddrp] 3/4 a ? a ((saddrp)) p a, [%saddrg] 3/4 a ? a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ? ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ? ((saddrg)) a p a, !addr16 4 a ? a (addr16) p a, !!addr24 5 a ? a (addr24) p !addr16, a 4 (addr16) ? (addr16) a p !!addr24, a 5 (addr24) ? (addr24) a p a, mem 2 to 5 a ? a (mem) p mem, a 2 to 5 (mem) ? (mem) a p 690 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy or a, #byte 2 a ? a byte p r, #byte 3 r ? r byte p saddr, #byte 3/4 (saddr) ? (saddr) byte p sfr, #byte 4 sfr ? sfr byte p r, r 2/3 r ? r r p a, saddr2 2 a ? a (saddr2) p r, saddr 3 r ? r (saddr) p saddr, r 3 (saddr) ? (saddr) r p r, sfr 3 r ? r sfr p sfr, r 3 sfr ? sfr r p saddr, saddr 4 (saddr) ? (saddr) (saddr) p a, [saddrp] 3/4 a ? a ((saddrp)) p a, [%saddrg] 3/4 a ? a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ? ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ? ((saddrg)) a p a, !addr16 4 a ? a (addr16) p a, !!addr24 5 a ? a (addr24) p !addr16, a 4 (addr16) ? (addr16) a p !!addr24, a 5 (addr24) ? (addr24) a p a, mem 2 to 5 a ? a (mem) p mem, a 2 to 5 (mem) ? (mem) a p 691 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy xor a, #byte 2 a ? a byte p r, #byte 3 r ? r byte p saddr, #byte 3/4 (saddr) ? (saddr) byte p sfr, #byte 4 sfr ? sfr byte p r, r 2/3 r ? r r p a, saddr2 2 a ? a (saddr2) p r, saddr 3 r ? r (saddr) p saddr, r 3 (saddr) ? (saddr) r p r, sfr 3 r ? r sfr p sfr, r 3 sfr ? sfr r p saddr, saddr 4 (saddr) ? (saddr) (saddr) p a, [saddrp] 3/4 a ? a ((saddrp)) p a, [%saddrg] 3/4 a ? a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ? ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ? ((saddrg)) a p a, !addr16 4 a ? a (addr16) p a, !!addr24 5 a ? a (addr24) p !addr16, a 4 (addr16) ? (addr16) a p !!addr24, a 5 (addr24) ? (addr24) a p a, mem 2 to 5 a ? a (mem) p mem, a 2 to 5 (mem) ? (mem) a p 692 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands bytes operation flags s z ac p/v cy addw ax, #word 3 ax, cy ? ax + word v rp, #word 4 rp, cy ? rp + word v rp, rp 2 rp, cy ? rp + rp v ax, saddrp2 2 ax, cy ? ax + (saddrp2) v rp, saddrp 3 rp, cy ? rp + (saddrp) v saddrp, rp 3 (saddrp), cy ? (saddrp) + rp v rp, sfrp 3 rp, cy ? rp + sfrp v sfrp, rp 3 sfrp, cy ? sfrp + rp v saddrp, #word 4/5 (saddrp), cy ? (saddrp) + word v sfrp, #word 5 sfrp, cy ? sfrp + word v saddrp, saddrp 4 (saddrp), cy ? (saddrp) + (saddrp) v subw ax, #word 3 ax, cy ? ax C word v rp, #word 4 rp, cy ? rp C word v rp, rp 2 rp, cy ? rp C rp v ax, saddrp2 2 ax, cy ? ax C (saddrp2) v rp, saddrp 3 rp, cy ? rp C (saddrp) v saddrp, rp 3 (saddrp), cy ? (saddrp) C rp v rp, sfrp 3 rp, cy ? rp C sfrp v sfrp, rp 3 sfrp, cy ? sfrp C rp v saddrp, #word 4/5 (saddrp), cy ? (saddrp) C word v sfrp, #word 5 sfrp, cy ? sfrp C word v saddrp, saddrp 4 (saddrp), cy ? (saddrp) C (saddrp) v cmpw ax, #word 3 ax C word v rp, #word 4 rp C word v rp, rp 2 rp C rp v ax, saddrp2 2 ax C (saddrp2) v rp, saddrp 3 rp C (saddrp) v saddrp, rp 3 (saddrp) C rp v rp, sfrp 3 rp C sfrp v sfrp, rp 3 sfrp C rp v saddrp, #word 4/5 (saddrp) C word v sfrp, #word 5 sfrp C word v saddrp, saddrp 4 (saddrp) C (saddrp) v 693 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (8) 24-bit operation instructions: addg, subg mnemonic operands bytes operation flags s z ac p/v cy addg rg, rg 2 rg, cy ? rg + rg v rg, #imm24 5 rg, cy ? rg + #imm24 v whl, saddrg 3 whl, cy ? whl + (saddrg) v subg rg, rg 2 rg, cy ? rg C rg v rg, #imm24 5 rg, cy ? rg C imm24 v whl, saddrg 3 whl, cy ? whl C (saddrg) v (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands bytes operation flags s z ac p/v cy mulu r 2/3 ax ? a r muluw rp 2 ax (upper half), rp (lower half) ? ax rp mulw rp 2 ax (upper half), rp (lower half) ? ax rp divuw r 2/3 ax (quotient), r (remainder) ? ax ? r note 1 divux rp 2 axde (quotient), rp (remainder) ? axde ? rp note 2 notes 1. when r = 0, r ? x, ax ? ffffh 2. when rp = 0, pr ? de, axde ? ffffffffh (10) special operation instructions: macw, macsw, sacw mnemonic operands bytes operation flags s z ac p/v cy macw byte 3 axde ? (b) (c) + axde, b ? b + 2, v c ? c + 2, byte ? byte C 1 end if(byte = 0 or p/v = 1) macsw byte 3 axde ? (b) (c) + axde, b ? b + 2, v c ? c + 2, byte ? byte C 1 if byte = 0 then end if p/v = 1 then if overflow axde ? 7fffffffh, end if underflow axde ? 80000000h, end sacw [tde+], [whl+] 4 ax ? |(tde) C (whl)| + ax, v tde ? tde + 2, whl ? whl + 2 c ? c C 1 end if(c = 0 or cy = 1) 694 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands bytes operation flags s z ac p/v cy inc r 1/2 r ? r + 1 v saddr 2/3 (saddr) ? (saddr) + 1 v dec r 1/2 r ? r C1 v saddr 2/3 (saddr) ? (saddr) C 1 v incw rp 2/1 rp ? rp + 1 saddrp 3/4 (saddrp) ? (saddrp) + 1 decw rp 2/1 rp ? rp C 1 saddrp 3/4 (saddrp) ? (saddrp) C 1 incg rg 2 rg ? rg + 1 decg rg 2 rg ? rg C 1 (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands bytes operation flags s z ac p/v cy adjba 2 decimal adjust accumulator after addition p adjbs 2 decimal adjust accumulator after subtract p cvtbw 1 x ? a, a ? 00h if a 7 = 0 x ? a, a ? ffh if a 7 = 1 695 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands bytes operation flags s z ac p/v cy ror r, n 2/3 (cy, r7 ? r0 , rm C 1 ? rm ) n times n = 0 C 7 p rol r, n 2/3 (cy, r0 ? r7 , rm + 1 ? rm ) n times n = 0 C 7 p rorc r, n 2/3 (cy ? r0 , r7 ? cy, rm C 1 ? rm ) n times n = 0 C 7 p rolc r, n 2/3 (cy ? r7 , r0 ? cy, rm + 1 ? rm ) n times n = 0 C 7 p shr r, n 2/3 (cy ? r0 , r7 ? 0, rm C 1 ? rm ) n times n = 0 C 7 0p shl r, n 2/3 (cy ? r7 , r0 ? 0, rm + 1 ? rm ) n times n = 0 C 7 0p shrw rp, n 2 (cy ? rp0 , rp15 ? 0, rpm C 1 ? rpm) n times 0p n = 0 C 7 shlw rp, n 2 (cy ? rp15 , rp0 ? 0, rpm + 1 ? rpm) n times 0p n = 0 C 7 ror4 mem3 2 a 3 C 0 ? (mem3) 3 C 0 , (mem3) 7 C 4 ? a 3 C 0 , (mem3) 3 C 0 ? (mem3) 7 C 4 rol4 mem3 2 a 3 C 0 ? (mem3) 7 C 4 , (mem3) 3 C 0 ? a 3 C 0 , (mem3) 7 C 4 ? (mem3) 3 C 0 (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operands bytes operation flags s z ac p/v cy mov1 cy, saddr.bit 3/4 cy ? (saddr.bit) cy, sfr.bit 3 cy ? sfr.bit cy, x.bit 2 cy ? x.bit cy, a.bit 2 cy ? a.bit cy, pswl.bit 2 cy ? pswl.bit cy, pswh.bit 2 cy ? pswh.bit cy, !addr16.bit 5 cy ? !addr16.bit cy, !!addr24.bit 2 cy ? !!addr24.bit cy, mem2.bit 2 cy ? mem2.bit saddr.bit, cy 3/4 (saddr.bit) ? cy sfr.bit, cy 3 sfr.bit ? cy x.bit, cy 2 x.bit ? cy a.bit, cy 2 a.bit ? cy pswl.bit, cy 2 psw l .bit ? cy pswh.bit, cy 2 psw h .bit ? cy !addr16.bit, cy 5 !addr16.bit ? cy !!addr24.bit, cy 6 !!addr24.bit ? cy mem2.bit, cy 2 mem2.bit ? cy 696 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy and1 cy, saddr.bit 3/4 cy ? cy (saddr.bit) cy, /saddr.bit 3/4 cy ? cy (saddr.bit) cy, sfr.bit 3 cy ? cy sfr.bit cy, /sfr.bit 3 cy ? cy sfr.bit cy, x.bit 2 cy ? cy x.bit cy, /x.bit 2 cy ? cy x.bit cy, a.bit 2 cy ? cy a.bit cy, /a.bit 2 cy ? cy a.bit cy, pswl.bit 2 cy ? cy psw l .bit cy, /pswl.bit 2 cy ? cy psw l .bit cy, pswh.bit 2 cy ? cy psw h .bit cy, /pswh.bit 2 cy ? cy psw h .bit cy, !addr16.bit 5 cy ? cy !addr16.bit cy, /!addr16.bit 5 cy ? cy !addr16.bit cy, !!addr24.bit 2 cy ? cy !!addr24.bit cy, /!!addr24.bit 6 cy ? cy !!addr24.bit cy, mem2.bit 2 cy ? cy mem2.bit cy, /mem2.bit 2 cy ? cy mem2.bit or1 cy, saddr.bit 3/4 cy ? cy (saddr.bit) cy, /saddr.bit 3/4 cy ? cy (saddr.bit) cy, sfr.bit 3 cy ? cy sfr.bit cy, /sfr.bit 3 cy ? cy sfr.bit cy, x.bit 2 cy ? cy x.bit cy, /x.bit 2 cy ? cy x.bit cy, a.bit 2 cy ? cy a.bit cy, /a.bit 2 cy ? cy a.bit cy, pswl.bit 2 cy ? cy psw l .bit cy, /pswl.bit 2 cy ? cy psw l .bit cy, pswh.bit 2 cy ? cy psw h .bit cy, /pswh.bit 2 cy ? cy psw h .bit cy, !addr16.bit 5 cy ? cy !addr16.bit cy, /!addr16.bit 5 cy ? cy !addr16.bit cy, !!addr24.bit 2 cy ? cy !!addr24.bit cy, /!!addr24.bit 6 cy ? cy !!addr24.bit cy, mem2.bit 2 cy ? cy mem2.bit cy, /mem2.bit 2 cy ? cy mem2.bit 697 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy xor1 cy, saddr.bit 3/4 cy ? cy (saddr.bit) cy, sfr.bit 3 cy ? cy sfr.bit cy, x.bit 2 cy ? cy x.bit cy, a.bit 2 cy ? cy a.bit cy, pswl.bit 2 cy ? cy pswl.bit cy, pswh.bit 2 cy ? cy pswh.bit cy, !addr16.bit 5 cy ? cy !addr16.bit cy, !!addr24.bit 2 cy ? cy !!addr24.bit cy, mem2.bit 2 cy ? cy mem2.bit not1 saddr.bit 3/4 (saddr.bit) ? (saddr.bit) sfr.bit 3 sfr.bit ? sfr.bit x.bit 2 x.bit ? x.bit a.bit 2 a.bit ? a.bit pswl.bit 2 pswl.bit ? psw l .bit pswh.bit 2 pswh.bit ? psw h .bit !addr16.bit 5 !addr16.bit ? !addr16.bit !!addr24.bit 2 !!addr24.bit ? !!addr24.bit mem2.bit 2 mem2.bit ? mem2.bit cy 1 cy ? cy set1 saddr.bit 2/3 (saddr.bit) ? 1 sfr.bit 3 sfr.bit ? 1 x.bit 2 x.bit ? 1 a.bit 2 a.bit ? 1 pswl.bit 2 pswl.bit ? 1 pswh.bit 2 pswh.bit ? 1 !addr16.bit 5 !addr16.bit ? 1 !!addr24.bit 2 !!addr24.bit ? 1 mem2.bit 2 mem2.bit ? 1 cy 1 cy ? 11 clr1 saddr.bit 2/3 (saddr.bit) ? 0 sfr.bit 3 sfr.bit ? 0 x.bit 2 x.bit ? 0 a.bit 2 a.bit ? 0 pswl.bit 2 pswl.bit ? 0 pswh.bit 2 pswh.bit ? 0 !addr16.bit 5 !addr16.bit ? 0 !!addr24.bit 2 !!addr24.bit ? 0 mem2.bit 2 mem2.bit ? 0 cy 1 cy ? 00 698 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands bytes operation flags s z ac p/v cy push psw 1 (sp C 2) ? psw, sp ? sp C 2 sfrp 3 (sp C 2) ? sfrp, sp ? sp C 2 sfr 3 (sp C 1) ? sfr, sp ? sp C 1 post 2 {(sp C 2) ? post, sp ? sp C 2} m times note rg 2 (sp C 3) ? rg, sp ? sp C 3 pushu post 2 {(uup C 2) ? post, uup ? uup C 2} m times note pop psw 1 psw ? (sp), sp ? sp + 2 rrrrr sfrp 3 sfrp ? (sp), sp ? sp + 2 sfr 3 sfr ? (sp), sp ? sp + 1 post 2 {post ? (sp), sp ? sp + 2} m times note rg 2 rg ? (sp), sp ? sp + 3 popu post 2 {post ? (uup), uup ? uup + 2} m times note movg sp, #imm24 5 sp ? imm24 sp, whl 2 sp ? whl whl, sp 2 whl ? sp addwg sp, #word 4 sp ? sp + word subwg sp, #word 4 sp ? sp C word incg sp 2 sp ? sp + 1 decg sp 2 sp ? sp C 1 note m = number of registers specified by post 699 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands bytes operation flags s z ac p/v cy call !addr16 3 (sp C 3) ? (pc + 3), sp ? sp C 3, pc hw ? 0, pc lw ? addr16 !!addr20 4 (sp C 3) ? (pc + 4), sp ? sp C 3, pc ? addr20 rp 2 (sp C 3) ? (pc + 2), sp ? sp C 3, pc hw ? 0, pc lw ? rp rg 2 (sp C 3) ? (pc + 2), sp ? sp C 3, pc ? rg [rp] 2 (sp C 3) ? (pc + 2), sp ? sp C 3, pc hw ? 0, pc lw ? (rp) [rg] 2 (sp C 3) ? (pc + 2), sp ? sp C 3, pc ? (rg) $!addr20 3 (sp C 3) ? (pc + 3), sp ? sp C 3, pc ? pc + 3 + jdisp16 callf !addr11 2 (sp C 3) ? (pc + 2), sp ? sp C 3, pc 19 C 12 ? 0, pc11 ? 1, pc 10 C 0 ? addr11 callt [addr5] 1 (sp C 3) ? (pc + 1), sp ? sp C 3, pc hw ? 0, pc lw ? (addr5) brk 1 (sp C 2) ? psw, (sp C 1) 0 C 3 ? (pc + 1) hw , (sp C 4) ? (pc + 1) lw , sp ? sp C 4 pc hw ? 0, pc lw ? (003eh) brkcs rbn 2 pc lw ? rp2, rp3 ? psw, rbs2 C 0 ? n, rss ? 0, ie ? 0, rp3 8 C 11 ? pc hw , pc hw ? 0 ret 1 pc ? (sp), sp ? sp + 3 ret1 1 pc lw ? (sp), pc hw ? (sp + 3) 0 C 3 , rrrrr psw ? (sp + 2), sp ? sp + 4 clears to 0 flag with highest priority of flags of ispr that are set (1) retb 1 pc lw ? (sp), pc hw ? (sp + 3) 0 C 3 , rrrrr psw ? (sp + 2), sp ? sp + 4 retcs !addr16 3 psw ? rp3, pc lw ? rp2, rp2 ? addr16, rrrrr pc hw ? rp3 8 C 11 clears to 0 flag with highest priority of flags of ispr that are set (1) retcsb !addr16 4 psw ? rp3, pc lw ? rp2, rp2 ? addr16, rrrrr pc hw ? rp3 8 C 11 700 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (17) unconditional branch instruction: br mnemonic operands bytes operation flags s z ac p/v cy br !addr16 3 pc hw ? 0, pc lw ? addr16 !!addr20 4 pc ? addr20 rp 2 pc hw ? 0, pc lw ? rp rg 2 pc ? rg [rp] 2 pc hw ? 0, pc lw ? (rp) [rg] 2 pc ? (rg) $addr20 2 pc ? pc + 2 + jdisp8 $!addr20 3 pc ? pc + 3 + jdisp16 701 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operands bytes operation flags s z ac p/v cy bnz $addr20 2 pc ? pc + 2 + jdisp8 if z = 0 bne bz $addr20 2 pc ? pc + 2 + jdisp8 if z = 1 be bnc $addr20 2 pc ? pc + 2 + jdisp8 if cy = 0 bnl bc $addr20 2 pc ? pc + 2 + jdisp8 if cy = 1 bl bnv $addr20 2 pc ? pc + 2 + jdisp8 if p/v = 0 bpo bv $addr20 2 pc ? pc + 2 + jdisp8 if p/v = 1 bpe bp $addr20 2 pc ? pc + 2 + jdisp8 if s = 0 bn $addr20 2 pc ? pc + 2 + jdisp8 if s = 1 blt $addr20 3 pc ? pc + 3 + jdisp8 if p/v s = 1 bge $addr20 3 pc ? pc + 3 + jdisp8 if p/v s = 0 ble $addr20 3 pc ? pc + 3 + jdisp8 if (p/v s) z = 1 bgt $addr20 3 pc ? pc + 3 + jdisp8 if (p/v s) z = 0 bnh $addr20 3 pc ? pc + 3 + jdisp8 if z cy = 1 bh $addr20 3 pc ? pc + 3 + jdisp8 if z cy = 0 bf saddr.bit, $addr20 4/5 pc ? pc + 4 note + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr20 4 pc ? pc + 4 + jdisp8 if sfr.bit = 0 x.bit, $addr20 3 pc ? pc + 3 + jdisp8 if x.bit = 0 a.bit, $addr20 3 pc ? pc + 3 + jdisp8 if a.bit = 0 pswl.bit, $addr20 3 pc ? pc + 3 + jdisp8 if pswl.bit = 0 pswh.bit, $addr20 3 pc ? pc + 3 + jdisp8 if pswh.bit = 0 !addr16.bit, $addr20 6 pc ? pc + 3 + jdisp8 if !addr16.bit = 0 !!addr24.bit, $addr20 3 pc ? pc + 3 + jdisp8 if !!addr24.bit = 0 mem2.bit, $addr20 3 pc ? pc + 3 + jdisp8 if mem2.bit = 0 note when the number of bytes is 4. when 5, the operation is: pc ? pc + 5 + jdisp8. 702 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy bt saddr.bit, $addr20 3/4 pc ? pc + 3 note 1 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr20 4 pc ? pc + 4 + jdisp8 if sfr.bit = 1 x.bit, $addr20 3 pc ? pc + 3 + jdisp8 if x.bit = 1 a.bit, $addr20 3 pc ? pc + 3 + jdisp8 if a.bit = 1 pswl.bit, $addr20 3 pc ? pc + 3 + jdisp8 if psw l .bit = 1 pswh.bit, $addr20 3 pc ? pc + 3 + jdisp8 if psw h .bit = 1 !addr16.bit, $addr20 6 pc ? pc + 3 + jdisp8 if !addr16.bit = 1 !!addr24.bit, $addr20 3 pc ? pc + 3 + jdisp8 if !!addr24.bit = 1 mem2.bit, $addr20 3 pc ? pc + 3 + jdisp8 if mem2.bit = 1 btclr saddr.bit, $addr20 4/5 {pc ? pc + 4 note 2 + jdisp8, (saddr.bit) ? 0} if (saddr.bit) = 1 sfr.bit, $addr20 4 {pc ? pc + 4 + jdisp8, sfr.bit ? 0} if sfr.bit = 1 x.bit, $addr20 3 {pc ? pc + 3 + jdisp8, x.bit ? 0} if x.bit = 1 a.bit, $addr20 3 {pc ? pc + 3 + jdisp8, a.bit ? 0} if a.bit = 1 pswl.bit, $addr20 3 {pc ? pc + 3 + jdisp8, psw l .bit ? 0} if psw l .bit = 1 pswh.bit, $addr20 3 {pc ? pc + 3 + jdisp8, psw h .bit ? 0} if psw h .bit = 1 !addr16.bit, $addr20 6 {pc ? pc + 3 + jdisp8, !addr16.bit ? 0} if !addr16.bit = 1 !!addr24.bit, $addr20 3 {pc ? pc + 3 + jdisp8, !!addr24.bit ? 0} if !!addr24.bit = 1 mem2.bit, $addr20 3 {pc ? pc + 3 + jdisp8, mem2.bit ? 0} if mem2.bit = 1 notes 1. when the number of bytes is 3. when 4, the operation is: pc ? pc + 4 + jdisp8. 2. when the number of bytes is 4. when 5, the operation is: pc ? pc + 5 + jdisp8. 703 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 mnemonic operands bytes operation flags s z ac p/v cy bfset saddr.bit, $addr20 4/5 {pc ? pc + 4 note 2 + jdisp8, (saddr.bit) ? 1} if (saddr.bit) = 0 sfr.bit, $addr20 4 {pc ? pc + 4 + jdisp8, sfr.bit ? 1} if sfr.bit = 0 x.bit, $addr20 3 {pc ? pc + 3 + jdisp8, x.bit ? 1} if x.bit = 0 a.bit, $addr20 3 {pc ? pc + 3 + jdisp8, a.bit ? 1} if a.bit = 0 pswl.bit, $addr20 3 {pc ? pc + 3 + jdisp8, psw l .bit ? 1} if psw l .bit = 0 pswh.bit, $addr20 3 {pc ? pc + 3 + jdisp8, psw h .bit ? 1} if psw h .bit = 0 !addr16.bit, $addr20 6 {pc ? pc + 3 + jdisp8, !addr16.bit ? 1} if !addr16.bit = 0 !!addr24.bit, $addr20 3 {pc ? pc + 3 + jdisp8, !!addr24.bit ? 1} if !!addr24.bit = 0 mem2.bit, $addr20 3 {pc ? pc + 3 + jdisp8, mem2.bit ? 1} if mem2.bit = 0 dbnz b, $addr20 2 b ? b C 1, pc ? pc + 2 + jdisp8 if b 1 0 c, $addr20 2 c ? c C 1, pc ? pc + 2 + jdisp8 if c 1 0 $addr, $addr20 3/4 (saddr) ? (saddr) C 1, pc ? pc + 3 note 1 = jdisp8 if (saddr) 1 0 notes 1. when the number of bytes is 3. when 4, the operation is: pc ? pc + 4 + jdisp8. 2. when the number of bytes is 4. when 5, the operation is: pc ? pc + 5 + jdisp8. (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands bytes operation flags s z ac p/v cy mov stbc, #byte 4 stbc ? byte wdm, #byte 4 wdm ? byte location locaddr 4 sfr, internal data area location address upper word specification sel rbn 2 rss ? 0, rbs2 C 0 ? n rbn, alt 2 rss ? 1, rbs2 C 0 ? n swrs 2 rss ? rss nop 1 no operaton ei 1 ie ? 1 (enable interrupt) di 1 ie ? 0 (disable interrupt) 704 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (20) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operands bytes operation flags s z ac p/v cy movtblw !addr8, byte 4 (addr8 + 2) ? (addr8), byte ? byte C 1, addr8 ? addr8 C 2 end if byte = 0 movw [tde+], a 2 (tde) ? a, tde ? tde + 1, c ? c C 1 end if c = 0 [tdeC], a 2 (tde) ? a, tde ? tde C 1, c ? c C 1 end if c = 0 xchm [tde+], a 2 (tde) ? a, tde ? tde + 1, c ? c C 1 end if c = 0 [tdeC], a 2 (tde) ? a, tde ? tde C 1, c ? c C 1 end if c = 0 movbk [tde+], [whl+] 2 (tde) ? (whl), tde ? tde + 1, whl ? whl + 1, c ? c C 1 end if c = 0 [tdeC], [whlC] 2 (tde) ? (whl), tde ? tde C 1, whl ? whl C 1, c ? c C 1 end if c = 0 xchbk [tde+], [whl+] 2 (tde) ? (whl), tde ? tde +1, whl ? whl + 1, c ? c C 1 end if c = 0 [tdeC], [whlC] 2 (tde) ? (whl), tde ? tde C 1, whl ? whl C 1, c ? c C 1 end if c = 0 cmpme [tde+], a 2 (tde) C a, tde ? tde + 1, c ? c C 1 end if c = 0 or z = 0 v [tdeC], a 2 (tde) C a, tde ? tde C 1, c ? c C 1 end if c = 0 or z = 0 v cmpmne [tde+], a 2 (tde) C a, tde ? tde + 1, c ? c C 1 end if c = 0 or z = 1 v [tdeC], a 2 (tde) C a, tde ? tde C 1, c ? c C 1 end if c = 0 or z = 1 v cmpmc [tde+], a 2 (tde) C a, tde ? tde + 1, c ? c C 1 end if c = 0 or cy = 0 v [tdeC], a 2 (tde) C a, tde ? tde C 1, c ? c C 1 end if c = 0 or cy = 0 v cmpmnc [tde+], a 2 (tde) C a, tde ? tde + 1, c ? c C 1 end if c = 0 or cy = 1 v [tdeC], a 2 (tde) C a, tde ? tde C 1, c ? c C 1 end if c = 0 or cy = 1 v cmpbke [tde+], [whl+] 2 (tde) ? (whl), tde ? tde + 1, v whl ? whl + 1, c ? c C 1 end if c = 0 or z = 0 [tdeC], [whlC] 2 (tde) ? (whl), tde ? tde C 1, v whl ? whl C 1, c ? c C 1 end if c = 0 or z = 0 cmpbkne [tde+], [whl+] 2 (tde) C (whl), tde ? tde + 1, v whl ? whl + 1, c ? c C 1 end if c = 0 or z = 1 [tdeC], [whlC] 2 (tde) C (whl), tde ? tde C 1, v whl ? whl C 1, c ? c C 1 end if c = 0 or z = 1 cmpbkc [tde+], [whl+] 2 (tde) C (whl), tde ? tde + 1, v whl ? whl + 1, c ? c C 1 end if c = 0 or cy = 0 [tdeC], [whlC] 2 (tde) C (whl), tde ? tde C 1, v whl ? whl C 1, c ? c C 1 end if c = 0 or cy = 0 cmpbknc [tde+], [whl+] 2 (tde) C (whl), tde ? tde + 1, v whl ? whl + 1, c ? c C 1 end if c = 0 or cy = 1 [tdeC], [whlC] 2 (tde) C (whl), tde ? tde C 1, v whl ? whl C 1, c ? c C 1 end if c = 0 or cy = 1 705 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 29.3 instructions listed by type of addressing (1) 8-bit instructions (combinations expressed by writing a for r are shown in parentheses) mov, xch, add, addc, sub, subc, and or xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc table 29-1. list of instructions by 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r saddr !!addr24 [saddrp] pswl [whlC] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. if saddr is saddr2 in this combination, there is a short code length instruction. 706 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (2) 16-bit instructions (combinations expressed by writing ax for rp are shown in parentheses) movm, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 29-2. list of instructions by 16-bit addressing 2nd operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp saddrp !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. if saddrp is saddrp2 in this combination, there is a short code length instruction. 4. muluw and divux are the same as mulw. 707 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (3) 24-bit instructions (combinations expressed by writing whl for rg are shown in parentheses) movg, addg, subg, incg, decg, push, pop table 29-3. list of instructions by 24-bit addressing 2nd operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note rg 1st operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no 2nd operand, or the 2nd operand is not an operand address. (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 29-4. list of instructions by bit manipulation instruction addressing 2nd operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit !addr16.bit /!addr16.bit 1st operand !!addr24.bit /!!addr24.bit cy mov1 and1 not1 and1 set1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no 2nd operand, or the 2nd operand is not an operand address. 708 chapter 29 instruction operations preliminary users manual u13987ej1v0um00 (5) call/return instructions/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 29-5. list of instructions by call/return instruction/branch instruction addressing instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address operand basic bc note call call call call call call call callf callt brkcs brk instructions br br br br br br br br ret retcs reti retcsb retb compound bf instructions bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs 709 preliminary users manual u13987ej1v0um00 appendix a development tools the following development tools are available for the development of systems that employ the m pd784938 subseries. figure a-1 shows the development tool configuration. ? support of pc98-nx series unless otherwise specified, products that operate in ibm pc/at tm or compatibles can operate in the pc98-nx series. when using pc98-nx series, refer to the descriptions for ibm pc/at or compatibles. ? windows unless otherwise specified, windows refers the following oss. ? windows 3.1 ? windows 95 ? windows nt ver.4.0 710 appendix a development tools preliminary users manual u13987ej1v0um00 figure a-1. development tool configuration (1/2) (1) when using in-circuit emulator ie-78k4-ns ? assembler package ? c compiler package ? c library source file ? device file language processing software ? system simulator ? integrated debugger ? device file ? real-time os ? os software for embedding flash memory writing adapter in-circuit emulator emulation probe conversion socket target system host machine (pc) emulation board on-chip flash memory version flash memory programming environment flash programmer debugging tools interface adapter, pc card interface, etc. power supply unit 711 appendix a development tools preliminary users manual u13987ej1v0um00 figure a-1. development tool configuration (2/2) (2) when using in-circuit emulator ie-784000-r ? assembler package ? c compiler package ? c library source file ? device file language processing software ? system simulator ? integrated debugger ? device file ? real-time os ? os software for embedding flash memory writing adapter in-circuit emulator emulation probe conversion socket target system host machine (pc or ews) interface adapter i/o emulation board probe board emulation probe conversion board emulation board on-chip flash memory version flash memory programming environment flash programmer debugging tools interface board remark items in broken line boxes differ according to the development environment. refer to a.3.1 hardware . 712 appendix a development tools preliminary users manual u13987ej1v0um00 a.1 language processing software ra78k4 assembler package cc78k4 c compiler package df784937 note cc78k4-l c library source file note the df784937 can be used in common with the ra78k4, cc78k4, sm78k4, id78k4-ns, and id78k4. this assembler converts programs written in mnemonics into an object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with an optional device file (df784937). 713 appendix a development tools preliminary users manual u13987ej1v0um00 remark in the part number differs depending on the host machine and os used. m s ra78k4 m s cc78k4 m s df784937 m s cc78k4-l host machine os supply medium aa13 pc-9800 series windows (japanese version) note 3.5-inch 2hd fd ab13 ibm pc/at or compatibles windows (japanese version) note 3.5-inch 2hc fd bb13 windows (english version) note 3p16 hp9000 series 700 tm hp-ux (rel. 10.10) dat (dds) hp-ux 3k13 sparcstation tm sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt 3r13 news tm (risc) news-os (rel. 6.1) 3.5-inch 2hc fd note can be operated in dos environment. a.2 flash memory programming tools flashpro ii (part number fl-pr2) flash programmer dedicated to microcontrollers with on-chip flash memory. flashpro iii (part number fl-pr3, pg-fp3) flash programmer fa-100gf note flash memory writing adapter used connected to the flashpro ii, flashpro iii. flash memory writing adapter ? fa-100gf: for 100-pin plastic qfp (gf-3ba type) note under development remark fl-pr2, fl-pr3, and fa-100gf are products of naito densei machida mfg. co., ltd. phone: +81-44-822-3813 naito densei machida mfg. co., ltd. 714 appendix a development tools preliminary users manual u13987ej1v0um00 a.3 debugging tools a.3.1 hardware (1/2) (1) when using the in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-c pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if interface adapter ie-784937-ns-em1 note emulation board np-100gf emulation probe ev-9200gf-100 conversion socket (refer to figures a-2 and a-3 ) note under development remarks 1. np-100gf is a product of naito densei machida mfg. co., ltd. phone: +81-44-822-3813 naito densei machida mfg. co., ltd. 2. ev-9200gf-100 is sold in units of five. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/iv series product. it corresponds to integrated debugger (id78k4-ns). this emulator should be used in combination with power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this adapter is used for supplying power from a receptacle of 100-v to 200-v ac. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-78k4-ns host machine (c bus supported). this is pc card and interface cable required when using the pc-9800 series notebook- type computer as the ie-78k4-ns host machine (pcmcia socket supported). this adapter is required when using the ibm pc/at or compatibles as the ie-78k4-ns host machine (isa bus supported). this adapter is required when connecting a personal computer that includes a pci bus as the ie-78k4-ns host machine. this board is used to emulate the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic qfp (gf-3ba type). this conversion socket connects the np-100gf to the target system board designed to mount a 100-pin plastic qfp (gf-3ba type). 715 appendix a development tools preliminary users manual u13987ej1v0um00 a.3.1 hardware (2/2) (2) when using the in-circuit emulator ie-784000-r ie-784000-r in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-78000-r-sv3 interface adapter ie-784000-r-em emulation board ie-784937-ns-em1 note or ie-784937-sl-em1 emulation board ie-78k4-r-ex3 note emulation probe conversion board ep-78064gf-r emulation probe ev-9200gf-100 conversion socket (refer to figures a-2 and a-3 ) note under development remark ev-9200gf-100 is sold in units of five. the ie-784000-r is an in-circuit emulator that can be used in all members of the 78k/iv series. use in combination with the separately purchased ie-784000-r-em and ie-784937-ns- em1. for debugging, connect to the host machine. using in combination with the mandatory, separately purchased, integrated debugger (id78k4) and device file, allows debugging on the source program level in c language and structured assembly language. the c0 coverage function provides efficient debugging and program inspection. connecting with the host machine by either ethernet? or a dedicated bus requires a separately purchased interface adapter. this adapter is required when using the pc-9800 series computer (except notebook type) as the ie-784000-r host machine (c bus supported). this adapter is required when using the ibm pc/at or compatibles as the ie-784000-r host machine (isa bus supported). this is adapter and cable required when using an ews computer as the ie-784000-r host machine, and is used connected to the board in the ie-784000-r. 10base-5 is supported for ethernet, but a commercially available conversion adapter is required for other formats. the emulation board that is used with all units in the 78k/iv series. board for emulating peripheral hardware that is inherent to a device. 100-pin conversion board required when using the ie-784937-ns-em1 on the ie-784000-r. this probe is used to connect the in-circuit emulator to the target system and is designed for 100-pin plastic qfp (gf-3ba type). this conversion socket connects the ep-78064gf-r to the target system board designed to mount a 100-pin plastic qfp (gf-3ba type). 716 appendix a development tools preliminary users manual u13987ej1v0um00 a.3.2 software (1/2) sm78k4 this system simulator is used to perform debugging at c source level or assembler level system simulator while simulating the operation of the target system on a host machine. this simulator runs on windows. use of the sm78k4 allows the execution of application logical testing and performance testing on an independent basis from hardware development without having to use an in-circuit emulator, thereby providing higher development efficiency and software quality. the sm78k4 should be used in combination with the optional device file (df784937). part number: m s sm78k4 remark in the part number differs depending on the host machine and os used. m s sm78k4 host machine os supply medium aa13 pc-9800 series windows (japanese version) 3.5-inch 2hd fd ab13 ibm pc/at or compatibles windows (japanese version) 3.5-inch 2hc fd bb13 windows (english version) 717 appendix a development tools preliminary users manual u13987ej1v0um00 a.3.2 software (2/2) id78k4-ns note integrated debugger (supporting in-circuit emulator ie-78k4-ns) id78k4 integrated debugger (supporting in-circuit emulator ie-784000-r) note under development remark in the part number differs depending on the host machine and os used. m s id78k4-ns host machine os supply medium aa13 pc-9800 series windows (japanese version) 3.5-inch 2hd fd ab13 ibm pc/at or compatibles windows (japanese version) 3.5-inch 2hc fd bb13 windows (english version) m s id78k4 host machine os supply medium aa13 pc-9800 series windows (japanese version) 3.5-inch 2hd fd ab13 ibm pc/at or compatibles windows (japanese version) 3.5-inch 2hc fd bb13 windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 solaris (rel. 2.5.1) 1/4 inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd this debugger is a control program to debug 78k/iv series microcontrollers. it adopts a graphical user interface, which is equivalent visually and operationally to windows or osf/motif?. it also has an enhanced debugging function for c language programs, and thus trace results can be displayed on screen in c-language level by using the windows integration function which links a trace result with its source program, disas- sembled display, and memory display. in addition, by incorporating function modules such as task debugger and system performance analyzer, the efficiency of debugging programs, which run on real-time oss can be improved. it should be used in combination with the optional device file (df784937). part number: m s id78k4-ns, m s id78k4 718 appendix a development tools preliminary users manual u13987ej1v0um00 a.4 drawings of conversion socket (ev-9200gf-100) and recommended board mounting pattern mount the ep-78064gf-r in combination on the board. figure a-2. package drawing of ev-9200gf-100 (reference) (unit: mm) ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0e item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f 719 appendix a development tools preliminary users manual u13987ej1v0um00 figure a-3. recommended board mounting pattern of ev-9200gf-100 (reference) (unit: mm) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1e item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution 720 appendix a development tools preliminary users manual u13987ej1v0um00 a.5 check sheet for m pd784938 subseries development tools the following development tools are necessary for using the m pd784938 subseries products. check if the necessary tools are at hand (the dotted line in the table below indicates either of the tools above or below the line should be selected) . ? host machine: pc-9800 series order code check remark ie-784000-r ie-784000-r-em ie-784937-r-em1 ie-784937-ns-em1 ie-70000-98-if-b (other than notebook type personal computer), ie-70000-98-if-c ie-70000-98n-if (for notebook type personal computer) ie-78000r-sv3 ie-78k4-r-ex3 ep-78064gf-r ev-9200gf-100 fa-100gf (necessary for using flash memory version) m saa13id78k4 (3.5") m s5a13df784937 (3.5") m s5a10df784937 (5") m s5a13ra78k4 (3.5") m s5a10ra78k4 (5") m s5a13cc78k4 (3.5") note 1 m s5a10cc78k4 (5") note 1 m s5a13cc78k4-l (3.5") note 2 m s5a10cc78k4-l (5") note 2 notes 1. necessary for using the c compiler. 2. necessary for remodelling the library of the c compiler. 721 appendix a development tools preliminary users manual u13987ej1v0um00 ? host machine: ibm pc/at order code check remark ie-784000-r ie-784000-r-em ie-784937-r-em1 ie-784937-ns-em1 ie-70000-pc-if-b, ie-70000-pc-if-c ie-78000r-sv3 ie-78k4-r-ex3 ep-78064gf-r ev-9200gf-100 fa-100gf (necessary for using flash memory version) m sbb13id78k4 (3.5") (english version) m sab13id78k4 (3.5") (japanese version) m s5a13df784937 (3.5") m s5a10df784937 (5") m s5a13ra78k4 (3.5") m s5a10ra78k4 (5") m s5a13cc78k4 (3.5") note 1 m s5a10cc78k4 (5") note 1 m s5a13cc78k4-l (3.5") note 2 m s5a10cc78k4-l (5") note 2 notes 1. necessary for using the c compiler. 2. necessary for remodelling the library of the c compiler. 722 preliminary users manual u13987ej1v0um00 [memo] 723 preliminary users manual u13987ej1v0um00 appendix b embedded software the following embedded software products are available for efficient program development and maintenance of the m pd784938 subseries. real-time os (1/2) rx78k/iv rx78k/iv is a real-time os conforming to the m itron specifications. real-time os tool (configurator) for generating nucleus of rx78k/iv and plural information tables is supplied. used in combination with an optional assembler package (ra78k4) and device file (df784937). 724 appendix b embedded software preliminary users manual u13987ej1v0um00 real-time os (2/2) mx78k4 mx78k4 is an os for m itron specification subsets. a nucleus for the mx78k4 is also os included as a companion product. this manages tasks, events, and time. in the task management, determining the task execution order and switching from task to the next task are performed. 725 preliminary users manual u13987ej1v0um00 appendix c register index c.1 register name index [a] a/d conversion result register (adcr) ... 406 a/d converter mode register (adm) ... 407 a/d current cut select register (iead) ... 410 asynchronous serial interface mode register (asim) ... 428, 433 asynchronous serial interface mode register 2 (asim2) ... 428, 433 asynchronous serial interface status register (asis) ... 434 asynchronous serial interface status register 2 (asis2) ... 434 [b] baud rate generator control register (brgc) ... 451 baud rate generator control register 2 (brgc2) ... 451 bus control register (bcr) ... 484 [c] capture/compare control register 0 (crc0) ... 223 capture/compare control register 1 (crc1) ... 279 capture/compare control register 2 (crc2) ... 314 capture/compare register (cr11/cr11w, cr21/cr21w) ... 275, 310 capture register (cr02, cr12/cr12w, cr22/cr22w) ... 220, 275, 310 clock output mode register (clom) ... 513 clocked serial interface mode register (csim) ... 459 clocked serial interface mode register 1 (csim1) ... 428, 443 clocked serial interface mode register 2 (csim2) ... 428, 443 clocked serial interface mode register 3 (csim3) ... 459 communication count register (ccr) ... 499 compare register (cr00, cr01, cr10/cr10w, cr20/cr20w, cr30/cr30w) ... 220, 275, 310, 375 control data register (cdr) ... 487 [d] data register (dr) ... 491 [e] external interrupt mode register 0 (intm0) ... 518 external interrupt mode register 1 (intm1) ... 519 [h] hold mode register (hldm) ... 634 [i] in-service priority register (ispr) ... 540 internal memory size switching register (ims) ... 82 interrupt control register ... 533 726 appendix c register index preliminary users manual u13987ej1v0um00 interrupt mask register (mk0h, mk0l, mk1h, mk1l) ... 538 interrupt mode control register (imc) ... 541 interrupt status register (isr) ... 494 [m] macro service mode register ... 567 memory expansion mode register (mm) ... 603, 615 [o] one-shot pulse output control register (ospc) ... 225 oscillation stabilization time specification register (osts) ... 109, 641 [p] partner address register (par) ... 486 port 0 (p0) ... 119 port 0 buffer register (p0l, p0h) ... 204 port 0 mode register (pm0) ... 120 port 1 (p1) ... 126 port 1 mode control register (pmc1) ... 131 port 1 mode register (pm1) ... 131 port 2 (p2) ... 137 port 3 (p3) ... 143 port 3 mode control register (pmc3) ... 149 port 3 mode register (pm3) ... 148 port 4 (p4) ... 155 port 4 mode register (pm4) ... 156 port 5 (p5) ... 162 port 5 mode register (pm5) ... 163 port 6 (p6) ... 169 port 6 mode register (pm6) ... 175 port 7 (p7) ... 179 port 7 mode register (pm7) ... 180 port 9 (p9) ... 183 port 9 mode register (pm9) ... 184 port 10 (p10) ... 188 port 10 mode control register (pmc10) ... 193 port 10 mode register (pm10) ... 193 prescaler mode register 0 (prm0) ... 222, 377 prescaler mode register 1 (prm1) ... 278, 313 program status word (pswl) ... 543 programmable wait control register 1 (pwc1) ... 616 programmable wait control register 2 (pwc2) ... 617 pull-up resistor option register h (puoh) ... 187, 197 pull-up resistor option register l (puol) ... 123, 135, 141, 153, 159, 166, 178 pwm control register (pwmc) ... 397 pwm modulo register 0 (pwm0) ... 398 pwm modulo register 1 (pwm1) ... 398 pwm prescaler register (pwpr) ... 398 727 appendix c register index preliminary users manual u13987ej1v0um00 [r] real-time output port control register (rtpc) ... 203 refresh area specification register (rfa) ... 630 refresh mode register (rfm) ... 629 rom correction adress register h (corah) ... 667 rom correction adress register l (coral) ... 667 rom correction control register (corc) ... 667 [s] sampling clock selection register (scs0) ... 520 serial receive buffer (rxb) ... 431 serial receive buffer 2 (rxb2) ... 431 serial shift register (sio) ... 458 serial shift register 1 (sio1) ... 442 serial shift register 2 (sio2) ... 442 serial shift register 3 (sio3) ... 457 serial transmit shift register (txs) ... 431 serial transmit shift register 2 (txs2) ... 431 slave address register (sar) ... 486 slave status register (ssr) ... 498 standby control register (stbc) ... 108, 639 success count register (scr) ... 499 [t] telegraph length register (dlr) ... 490 timer control register 0 (tmc0) ... 221, 376 timer control register 1 (tmc1) ... 277, 312 timer output control register (toc) ... 224, 315 timer counter 0 (tm0) ... 220 timer counter 1 (tm1/tm1w) ... 275 timer counter 2 (tm2/tm2w) ... 310 timer counter 3 (tm3/tm3w) ... 375 [u] unit address register (uar) ... 486 unit status register (usr) ... 492 [w] watch timer mode register (wm) ... 393 watchdog timer mode register (wdm) ... 389, 542 728 appendix c register index preliminary users manual u13987ej1v0um00 c.2 register symbol index [a] adcr : a/d conversion result register ... 406 adic : interrupt control register ... 535 adm : a/d converter mode register ... 407 asim : asynchronous serial interface mode register ... 428, 433 asim2 : asynchronous serial interface mode register 2 ... 428, 433 asis : asynchronous serial interface status register ... 434 asis2 : asynchronous serial interface status register 2 ... 434 [b] bcr : bus control register ... 484 brgc : baud rate generator control register ... 451 brgc2 : baud rate generator control register 2 ... 451 [c] ccr : communication count register ... 499 cdr : control data register ... 486 cic00 : interrupt control register ... 534 cic01 : interrupt control register ... 534 cic10 : interrupt control register ... 534 cic11 : interrupt control register ... 534 cic20 : interrupt control register ... 535 cic21 : interrupt control register ... 535 cic30 : interrupt control register ... 535 clom : clock output mode register ... 513 corah : rom correction address register h ... 667 coral : rom correction address register l ... 667 corc : rom correction control register ... 667 cr00 : compare register ... 220 cr01 : compare register ... 220 cr02 : capture register ... 220 cr10/cr10w : compare register ... 275 cr11/cr11w : capture/compare register ... 275 cr12/cr12w : capture register ... 275 cr20/cr20w : compare register ... 310 cr21/cr21w : capture/compare register ... 310 cr22/cr22w : capture register ... 310 cr30/cr30w : compare register ... 375 crc0 : capture/compare control register 0 ... 223 crc1 : capture/compare control register 1 ... 279 crc2 : capture/compare control register 2 ... 314 csiic : interrupt control register ... 536 csiic1 : interrupt control register ... 536 csiic2 : interrupt control register ... 536 csiic3 : interrupt control register ... 537 csim : clocked serial interface mode register ... 459 729 appendix c register index preliminary users manual u13987ej1v0um00 csim1 : clocked serial interface mode register 1 ... 428, 443 csim2 : clocked serial interface mode register 2 ... 428, 443 csim3 : clocked serial interface mode register 3 ... 459 [d] dlr : telegraph length register ... 490 dr : data register ... 491 [h] hldm : hold mode register ... 634 [i] iead : a/d current cut select register ... 410 ieic1 : interrupt control register ... 537 ieic2 : interrupt control register ... 537 imc : interrupt mode control register ... 541 ims : internal memory size switching register ... 82 intm0 : external interrupt mode register 0 ... 518 intm1 : external interrupt mode register 1 ... 519 ispr : in-service priority register ... 540 isr : interrupt status register ... 494 [m] mk0h : interrupt mask register h ... 538 mk0l : interrupt mask register l ... 538 mk1h : interrupt mask register 1h ... 538 mk1l : interrupt mask register 1l ... 538 mm : memory expansion mode register ... 603, 615 [o] ospc : one-shot pulse output control register ... 225 osts : oscillation stabilization time specification register ... 109, 641 [p] p0 : port 0 ... 119 p0h : port 0 buffer register h ... 204 p0l : port 0 buffer register l ... 204 p1 : port 1 ... 126 p2 : port 2 ... 137 p3 : port 3 ... 143 p4 : port 4 ... 155 p5 : port 5 ... 162 p6 : port 6 ... 169 p7 : port 7 ... 179 p9 : port 9 ... 183 p10 : port 10 ... 188 par : partner address register ... 486 pic0 : interrupt control register ... 534 730 appendix c register index preliminary users manual u13987ej1v0um00 pic1 : interrupt control register ... 534 pic2 : interrupt control register ... 534 pic3 : interrupt control register ... 534 pic4 : interrupt control register ... 535 pic5 : interrupt control register ... 535 pm0 : port 0 mode register ... 120 pm1 : port 1 mode register ... 131 pm3 : port 3 mode register ... 148 pm4 : port 4 mode register ... 156 pm5 : port 5 mode register ... 163 pm6 : port 6 mode register ... 175 pm7 : port 7 mode register ... 180 pm9 : port 9 mode register ... 184 pm10 : port 10 mode register ... 193 pmc1 : port 1 mode control register ... 131 pmc3 : port 3 mode control register ... 149 pmc10 : port 10 mode control register ... 193 prm0 : prescaler mode register 0 ... 222, 377 prm1 : prescaler mode register 1 ... 278, 313 pswl : program status word ... 543 puoh : pull-up resistor option register h ... 187, 197 puol : pull-up resistor option register l ... 123, 135, 141, 153, 159, 166, 178 pwc1 : programmable wait control register 1 ... 616 pwc2 : programmable wait control register 2 ... 617 pwm0 : pwm modulo register 0 ... 398 pwm1 : pwm modulo register 1 ... 398 pwmc : pwm control register ... 397 pwpr : pwm prescaler register ... 398 [r] rfa : refresh area specification register ... 630 rfm : refresh mode register ... 629 rtpc : real-time output port control register ... 203 rxb : serial receive buffer ... 431 rxb2 : serial receive buffer 2 ... 431 [s] sar : slave address register ... 486 scr : success count register ... 499 scs0 : sampling clock selection register ... 520 seric : interrupt control register ... 535 seric2 : interrupt control register ... 536 sio : serial shift register ... 458 sio1 : serial shift register 1 ... 442 sio2 : serial shift register 2 ... 442 sio3 : serial shift register 3 ... 457 sric : interrupt control register ... 535 sric2 : interrupt control register ... 536 731 appendix c register index preliminary users manual u13987ej1v0um00 ssr : slave status register ... 498 stbc : standby control register ... 108, 639 stic : interrupt control register ... 536 stic2 : interrupt control register ... 536 [t] tm0 : timer counter 0 ... 220 tm1/tm1w : timer counter 1 ... 275 tm2/tm2w : timer counter 2 ... 310 tm3/tm3w : timer counter 3 ... 375 tmc0 : timer control register 0 ... 221, 376 tmc1 : timer control register 1 ... 277, 312 toc : timer output control register ... 224, 315 txs : serial transmit shift register ... 431 txs2 : serial transmit shift register 2 ... 431 [u] uar : unit address register ... 486 usr : unit status register ... 492 [w] wdm : watchdog timer mode register ... 389, 542 wic : interrupt control register ... 537 wm : watch timer mode register ... 393 732 preliminary users manual u13987ej1v0um00 [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 99.1 name company from: tel. fax facsimile message |
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